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AM6442: GPMC memory address

GR
Genius 3186 points
Part Number: AM6442


Tool/software:

Hello,

May I have question about GPMC?

Q1

I found GPMC0_DATA is 0x0 5000 0000 to 0x0 57FF FFFF in Table 2-1. MAIN Domain Memory Map.

But in Table 12-3241. GPMC Memory Map, GPMC0_DATA is 0x00 2000 0000 to 0x00 27FF FFFF.

Which is correct?

In AM62 series, I saw E2E thread that say correct GPMC0_DATA is 0x0 5000 0000 to 0x0 57FF FFFF, So I think Table 12-3241. GPMC Memory Map is Typo.

Q2

I found max size of each memory.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1349234/faq-am24x-am64x-am62x-what-are-the-maximum-sizes-of-nand-or-nor-or-psram-memories-that-can-be-connected-to-gpmc-for-the-am24x-am64x-am62x

Why NAND size is NA? and S.NO1 is up to 256MB??

I believe AM64's GPMC address make limit, up to 128MB.

Q3

Just make sure.

Total size of eacs GPMC chip select is limit up to 128MB?

for example 

 CS0->64MB, CS1->64MB, CS2/CS3->not config => AM64 can read ALL memory of CS0 and CS1

 CS0->128MB, CS1->64MB, CS2/CS3->not config => AM64 can read ALL of CS0 but CS1 can't readable

 CS0->256MB, CS1/CS2/CS30->not config => AM64 can read lower 128MB of CS0

Is all correct?

Best regards,

GR

 

  • 0
    TI__Mastermind 48446 points

    Hello GR,

    I am looking at your queries and you may expect reply in one or two days .

    Regards,

    Anil.

  • +1 in reply to Swargam Anil
    TI__Mastermind 48446 points

    Hello GR,

    Sorry for the delayed reply.

    Please see my comments below.

    The NAND device does not address mapped memory to the SOC.

    Which means that SOC has to send commands to write and read the pages.

    In this case, there is no size limit to SOC for interface NAND devices.

    For the coming to NOR/PSRAM memories, the entire NOR memory size can be mapped to SOC address space . In this case there is a size limit.

    This address 0x5000 0000 to 0x57FF FFFF is correct.

    GR said:
    I believe AM64's GPMC address make limit, up to 128MB.

    Yes , the CS size is limited to 128MB only .

    The SOC can support 256MB configuration but it can read only 128MB.

    GR said:

     CS0->64MB, CS1->64MB, CS2/CS3->not config => AM64 can read ALL memory of CS0 and CS1

     CS0->128MB, CS1->64MB, CS2/CS3->not config => AM64 can read ALL of CS0 but CS1 can't readable

     CS0->256MB, CS1/CS2/CS30->not config => AM64 can read lower 128MB of CS0

    Yes, the above understanding is correct .

    Regards,

    Anil.

  • 0 in reply to Swargam Anil
    Genius 3186 points

    Hello Anil,

    Thanks for your information.

    I understand.

    Best regards,

    GR