About dm8148 mmc mux

Dear Viet Dinh,

I have a similar problem,

I want to enable DM8148 MMC2 in U-boot & Kernel,

I can detect MMC2 in kernel now, but I can not detect MMC2 in uboot,

I have already setup OMAP_HSMMC_BASE and CM_ALWON_HSMMC_CLKCTRL for MMC2,

but it fail in drivers/mmc/omap_hsmmc.c:mmc_send_cmd(),

Do I miss anything?

Thanks.

Hi,

Can you please attach your changes to u-boot?

Have you modify PINMUX for MMC2?

How does it fail?

Regards,

Marcin

Dear Marcin,

pinmux in mux.h is already setup correct, so I do not modify pinmux for mmc2

It fail at mmc_send_cmd with IE_CTO error.

below is our changes

diff --git a/arch/arm/include/asm/arch-ti81xx/cpu.h b/arch/arm/include/asm/arch-ti81xx/cpu.h
index 79997d5..b6a7022 100644
--- a/arch/arm/include/asm/arch-ti81xx/cpu.h
+++ b/arch/arm/include/asm/arch-ti81xx/cpu.h
@@ -310,6 +310,8 @@
 
 #ifdef CONFIG_TI814X
 #define CM_ALWON_HSMMC_CLKCTRL        (PRCM_BASE + 0x1620)
+#define CM_ALWON_HSMMC1_CLKCTRL             (PRCM_BASE + 0x1620)
+#define CM_ALWON_HSMMC2_CLKCTRL             (PRCM_BASE + 0x1624)
 #endif
 
 #ifdef CONFIG_TI814X
diff --git a/arch/arm/include/asm/arch-ti81xx/mmc_host_def.h b/arch/arm/include/asm/arch-ti81xx/mmc_host_def.h
index ca6bf62..d9718d5 100644
--- a/arch/arm/include/asm/arch-ti81xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-ti81xx/mmc_host_def.h
@@ -32,6 +32,7 @@
 # define OMAP_HSMMC_BASE        0x48060100
 #elif defined(CONFIG_TI814X)
 # define OMAP_HSMMC_BASE        0x481D8100
+# define OMAP_HSMMC_BASE1        0x47810100
 #endif
 
 typedef struct hsmmc {
diff --git a/board/ti/i62/i62.c b/board/ti/i62/i62.c
index eb095e0..5d504a6 100644
--- a/board/ti/i62/i62.c
+++ b/board/ti/evm/evm.c
@@ -785,9 +785,12 @@ void per_clocks_enable(void)
     while((__raw_readl(CM_ALWON_ETHERNET_0_CLKCTRL) & 0x30000) != 0);
     __raw_writel(0x2, CM_ALWON_ETHERNET_1_CLKCTRL);
     /* HSMMC */
-    __raw_writel(0x2, CM_ALWON_HSMMC_CLKCTRL);
-    while(__raw_readl(CM_ALWON_HSMMC_CLKCTRL) != 0x2);
-
+    __raw_writel(0x2, CM_ALWON_HSMMC1_CLKCTRL);
+    while(__raw_readl(CM_ALWON_HSMMC1_CLKCTRL) != 0x2);
+    /* HSMMC2 */
+    __raw_writel(0x2, CM_ALWON_HSMMC2_CLKCTRL);
+    while(__raw_readl(CM_ALWON_HSMMC2_CLKCTRL) != 0x2);
+    
     /*
      * McASP2
      * select mcasp2 clk from sys_clk_22 (OSC 0)
@@ -1483,6 +1486,7 @@ U_BOOT_CMD(
 int board_mmc_init(bd_t *bis)
 {
         omap_mmc_init(0);
+        omap_mmc_init(1);
         return 0;
 }
 #endif
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index cf4ea16..1df1ee8 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -317,29 +319,56 @@ sd_send_op_cond(struct mmc *mmc)
 
 int mmc_send_op_cond(struct mmc *mmc)
 {
-    int timeout = 1000;
+    int timeout = 10000;
     struct mmc_cmd cmd;
     int err;
 
      /* Some cards seem to need this */
     mmc_go_idle(mmc);
 
+     /* Asking to the card its capabilities */
+     cmd.cmdidx = MMC_CMD_SEND_OP_COND;
+     cmd.resp_type = MMC_RSP_R3;
+     cmd.cmdarg = 0;
+     cmd.flags = 0;
+
+     err = mmc_send_cmd(mmc, &cmd, NULL);
+
+     if (err)
+         return err;
+
+     udelay(1000);
+
     do {
         cmd.cmdidx = MMC_CMD_SEND_OP_COND;
         cmd.resp_type = MMC_RSP_R3;
-        cmd.cmdarg = OCR_HCS | mmc->voltages;
-        cmd.flags = 0;
+        cmd.cmdarg = (mmc->voltages &
+                (cmd.response[0] & OCR_VOLTAGE_MASK)) |
+                (cmd.response[0] & OCR_ACCESS_MODE);
+
+        if (mmc->host_caps & MMC_MODE_HC)
+            cmd.cmdarg |= OCR_HCS;
 
+        cmd.flags = 0;
         err = mmc_send_cmd(mmc, &cmd, NULL);
 
         if (err)
             return err;
 
         udelay(1000);
     } while (!(cmd.response[0] & OCR_BUSY) && timeout--);
 
     if (timeout <= 0)
         return UNUSABLE_ERR;
 
     mmc->version = MMC_VERSION_UNKNOWN;
     mmc->ocr = cmd.response[0];
@@ -402,13 +431,20 @@ int mmc_change_freq(struct mmc *mmc)
 
     mmc->card_caps |= MMC_MODE_4BIT;
 
     err = mmc_send_ext_csd(mmc, ext_csd);
 
     if (err)
         return err;
 
-    if (ext_csd[212] || ext_csd[213] || ext_csd[214] || ext_csd[215])
+    printf ("mmc->capacity = %lu\n", (long unsigned int)mmc->capacity);
+    if (ext_csd[212] || ext_csd[213] || ext_csd[214] || ext_csd[215])
+//    if ((ext_csd[212] || ext_csd[213] || ext_csd[214] || ext_csd[215]) &&
+//        (mmc->capacity > (2u * 1024 * 1024 * 1024)))
+    {
         mmc->high_capacity = 1;
+        printf("Setting high capacity\n");
+    }
 
     cardtype = ext_csd[196] & 0xf;
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 6fad068..9a9a70d 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -31,6 +31,10 @@
 #include <asm/io.h>
 #include <asm/arch/mmc_host_def.h>
 
+/* common definitions for all OMAPs */
+#define SYSCTL_SRC    (1 << 25)
+#define SYSCTL_SRD    (1 << 26)
+
 /* If we fail after 1 second wait, something is really bad */
 #define MAX_RETRY_MS    1000
 
@@ -137,7 +147,8 @@ static int mmc_init_setup(struct mmc *mmc)
         MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
         HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 
-    dsor = 240;
+    dsor = 480;
+    printf("mmc_init_setup:dsor = %d\n",dsor);
     mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
         (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
     mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
@@ -163,6 +174,28 @@ static int mmc_init_setup(struct mmc *mmc)
 }
 
 
+/*
+ * MMC controller internal finite state machine reset
+ *
+ * Used to reset command or data internal state machines, using respectively
+ * SRC or SRD bit of SYSCTL register
+ */
+static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
+{
+    ulong start;
+
+    mmc_reg_out(&mmc_base->sysctl, bit, bit);
+
+    start = get_timer(0);
+    while ((readl(&mmc_base->sysctl) & bit) != 0) {
+        if (get_timer(0) - start > MAX_RETRY_MS) {
+            printf("%s: timedout waiting for sysctl %x to clear\n",
+                __func__, bit);
+            return;
+        }
+    }
+}
+
 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
             struct mmc_data *data)
 {
@@ -249,10 +282,18 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
         }
     } while (!mmc_stat);
 
-    if ((mmc_stat & IE_CTO) != 0)
+    printf("mmc_stat = %x\n", mmc_stat);
+
+    if ((mmc_stat & IE_CTO) != 0)
+    {
+        printf("error:IE_CTO\n");
+        mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
         return TIMEOUT;
-    else if ((mmc_stat & ERRI_MASK) != 0)
+    } else if ((mmc_stat & ERRI_MASK) != 0)
+    {
+        //printf("ERRI_MASK\n");
         return -1;
+    }
 
     if (mmc_stat & CC_MASK) {
         writel(CC_MASK, &mmc_base->stat);
@@ -302,6 +343,9 @@ static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size)
             }
         } while (mmc_stat == 0);
 
+        if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
+            mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+
         if ((mmc_stat & ERRI_MASK) != 0)
             return 1;
 
@@ -353,6 +397,9 @@ static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int size)
             }
         } while (mmc_stat == 0);
 
+        if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
+            mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+
         if ((mmc_stat & ERRI_MASK) != 0)
             return 1;
 
@@ -461,7 +512,17 @@ int omap_mmc_init(int dev_index)
         return 1;
     }
 #else
-    mmc->priv = (hsmmc_t *)OMAP_HSMMC_BASE;
+    switch (dev_index) {
+    case 0:
+        mmc->priv = (hsmmc_t *)OMAP_HSMMC_BASE;
+        break;
+    case 1:
+        mmc->priv = (hsmmc_t *)OMAP_HSMMC_BASE1;
+        break;
+    default:
+        mmc->priv = (hsmmc_t *)OMAP_HSMMC_BASE;
+        return 1;
+    }
 #endif
 
     mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
diff --git a/include/mmc.h b/include/mmc.h
index 8973bc7..e1e47c2 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -44,6 +44,7 @@
 #define MMC_MODE_HS_52MHz    0x010
 #define MMC_MODE_4BIT        0x100
 #define MMC_MODE_8BIT        0x200
+#define MMC_MODE_HC             0x800
 
 #define SD_DATA_4BIT    0x00040000
 
@@ -93,6 +94,8 @@
 
 #define OCR_BUSY    0x80000000
 #define OCR_HCS        0x40000000
+#define OCR_VOLTAGE_MASK    0x007FFF80
+#define OCR_ACCESS_MODE        0x60000000
 
 #define MMC_VDD_165_195        0x00000080    /* VDD voltage 1.65 - 1.95 */
 #define MMC_VDD_20_21        0x00000100    /* VDD voltage 2.0 ~ 2.1 */

update status,

After mux PINCNTL126 to SD2_CMD,

It has another problem.

EVM#mmc rescan 1
mmc_read_data: timedout waiting for status!
mmc_send_cmd: timedout waiting for cmddis!
EVM#mmcinfo 1
mmc_read_data: timedout waiting for status!
mmc_send_cmd: timedout waiting for cmddis!
Device: OMAP SD/MMC
Manufacturer ID: 15
OEM: 100
Name: M4G1F
Tran Speed: 25000000
Rd Block Len: 512
MMC version 4.0
High Capacity: Yes
Capacity: 2197796421632
Bus Width: 1-bit