Tool/software:
Hi supporting team,
From a previous thread, I learned that RESET voltage must drop before DVDD and CVDD for the IC to power down properly. Is there an interval required between when RESET drops to a level below 0.8V, which is the maximum voltage at which RESET is guaranteed to be read as a logic LOW and when DVDD drops below 2.7V, which is the minimum operating level?
Thanks and Best Regards,
