TDA4VH-Q1: CPSW9g interrupt

Tony Tang

Part Number: TDA4VH-Q1

Tool/software:

#1. There is one Tx and one Rx interrupt for the CPSW9g, but there are 9 ports, if use 8 MAC mode, can it implement 8 separate TX and RX interrupt for each port?

#2. If all ports share the same Tx and Rx interrupt, how does it distinguish each port data on the upstream port?

22 days ago

0 Doredla Sudheer Kumar 22 days ago

TI__Mastermind 45180 points

Hi,

Tony Tang said:
. There is one Tx and one Rx interrupt for the CPSW9g

Tx & Rx interrupts of CPSW9G are from UDMA.
CPSW can support Max 8 Tx channels and multiple Rx flows. Default 8 Tx channel and 1 Rx flow enabled.

Tony Tang said:
#2. If all ports share the same Tx and Rx interrupt, how does it distinguish each port data on the upstream port?

Each CPSW port has separate netdev registration with network stack, Please refer to "am65_cpsw_nuss_register_ndevs" API.

Tx path Interface is tied to port, these are directed traffic, packets will be sent from that port.
In Rx path CPSW accept the packet, based on descriptor header information port number will be fetched in driver and mapping to corresponding port ndev to submit to application.

For more details refer to

Rx Packet:

am65_cpsw_nuss_rx_packets() from am65-cpsw-nuss driver for Rx packet process and submit to network stack.

Tx Packet:

am65_cpsw_nuss_ndo_slave_xmit() from am65-cpsw-nuss driver for Tx packet process and submit to DMA.

Best Regards,
Sudheer

0 Tony Tang 22 days ago in reply to Doredla Sudheer Kumar

TI__Mastermind 27272 points

Hi Sudheer,

Doredla Sudheer Kumar said:
Tx & Rx interrupts of CPSW9G are from UDMA

So is there only one interrupt? or can be multiple?

From this post, CPSW-3G uses VLAN tags to distinguish port, is it same for CPSW9g?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1336076/sk-am62-how-to-know-eth0-interrupts

0 Doredla Sudheer Kumar 22 days ago in reply to Tony Tang

TI__Mastermind 45180 points

Hi,

Tony Tang said:
Doredla Sudheer Kumar said:
Tx & Rx interrupts of CPSW9G are from UDMA

So is there only one interrupt? or can be multiple?

It can be multiple, As per above 8 Tx channels -> 8 Tx interrupts, 1 Rx flow -> 1 Rx interrupt.

Tony Tang said:
From this post, CPSW-3G uses VLAN tags to distinguish port, is it same for CPSW9g?

No as I have mentioned above, Host Port will add port information to Tx packet information in UDMA descriptor.
Using above, we can identify packet came from which external port.

Best Regards,
Sudheer

0 chen chen 17 days ago in reply to Doredla Sudheer Kumar

Intellectual 251 points

About Rx. In the Rx_poll function, the driver can obtain the port_id of the data through desc_rx. DMA data already carries port information. I have more questions
1, cpsw9g has eight ports, whether the ports share a dma channel to transmit data to ringbuff. Whether eight ports share a ringbuff.
2. Whether the network protocol accesses the ringbuff data directly or copies the ringbuff data once and then releases the ringbuff.

Thanks

0 Doredla Sudheer Kumar 17 days ago in reply to chen chen

TI__Mastermind 45180 points

Hi,

chen chen said:
the driver can obtain the port_id of the data through desc_rx. DMA data already carries port information

Yes from descriptor driver obtains the port information.

chen chen said:
1, cpsw9g has eight ports, whether the ports share a dma channel to transmit data to ringbuff. Whether eight ports share a ringbuff

Data from external 8 ports will land on Internal host port Tx FIFO, from host to it will reach to driver by DMA.

Yes, all 8 ports information will be passed over same ring buffer and same dma channel.

chen chen said:
2. Whether the network protocol accesses the ringbuff data directly or copies the ringbuff data once and then releases the ringbuff

Driver will release the ring buffer after copying to skb buffer for network access.

Ring buffer will not be shared to network stack.

Best Regards,

Sudheer

0 chen chen 16 days ago in reply to Doredla Sudheer Kumar

Intellectual 251 points

About Tx

I found that the driver (SDK 10.00.00.08) request 8 common->txchns.
Each port has its own tx_chn. Does that mean they have their own dma channel and ringbuff? Not sharing the same channel.

Our company is based on SDK 09.01.00.06 development.The driver only requested a TX channel, does that mean they also share a ringbuff

Thanks

0 Doredla Sudheer Kumar 16 days ago in reply to chen chen

TI__Mastermind 45180 points

Hi,

chen chen said:
I found that the driver (SDK 10.00.00.08) request 8 common->txchns.
Each port has its own tx_chn. Does that mean they have their own dma channel and ringbuff? Not sharing the same channel.

Yes. 8 Tx channels with own ring buffers but all copy to same Host Port Rx FIFO.
Sorry, the channel selection is based on software queue passed from network stack. Driver will register 8 soft queues with network stack.
We can map soft queues to priorities and select specific priority go to specific channel.

if same priority send from multiple ports then all will be sent to Host Port Rx via same Tx channel using same ring buffer i.e. each port can send data from all 8 Tx channels as per packet priority.

Tx Descriptor information holds the port number, which is used by Host Port for transfer of packet to that corresponding port.
Please refer to slave_xmit API for more details.

chen chen said:
Our company is based on SDK 09.01.00.06 development.The driver only requested a TX channel, does that mean they also share a ringbuff

Yes, default 1 channel enabled even in Tx side.
If you want you can change the no.of Tx channels using ethtool -L option.
Please refer to SDK documentation for more details about query/set channels.
https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j7200/10_00_07_03/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW2g.html#interrupt-pacing

Query channels:
# ethtool-l DEVNAME

Set channels:
# ethtool -L DEVNAME

Best Regards,
Sudheer

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TDA4VH-Q1: CPSW9g interrupt