Tool/software:
Hi JJD,
We have simulated our AM62Px design. Our schematics and layout follows the SK-AM62P-LP: CK & ADDR_CTRL - it is routed in T topology when all group signals are routed on same layer and the T split portion for CA/CKE/CK signals are on an additional layer. CS0_A,CS1_A, CS0_B, CS1_B are not splitted same as in EVK layout/schematics. layout implementation is same as in the EVK. All Groups signals are matched to 0.1ps.
We used the models recommended here https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1405692/faq-using-ddr-ibis-models-for-am64x-am62x-am62ax-am62px
We have simulated at 3733 MTs and results show that the CS signals are not passing the EYE diagram, however, the CS signals are synced with the CK clock. (note, their amplitude is also different since they they have a 80Ohm PU/PD as recommended in the above thread),
Removing the CS signals, the eye is clear. see below pics
My questions are:
1. Are the results shown in regards to CS signals satisfying?
2. Should CS signals meet the eye requirement as well? (as far as I know they are control signals running at a lower frequency then the CK/CA signals).
3. Since CS signals are already matched 0.1ps to ADDR/CK/CKE, should we add a delay so they are aligned with the rest of the group? what is the maximum skew allowed for CS signals?
4. It seems the rise time of CS signals is faster then other groups signals, perhaps it is due to the extra copper available in other signals which pass also T split. Is there any action which needs to be taken in regards to this?
--update on Q3: We have tested added a delay and CS is now more aligned to the ADDR/CKE signals (see below). please advise if this modification is preferred:
Would appreciate any additional inputs on simulation of these signals.
Thank you for your advice,
John
