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Original question:

AM4372: power up/down sequence

AM4372: simplified power sequencing

Kanae
Mastermind 9885 points
Part Number: AM4372
Other Parts Discussed in Thread: TPS65218D0

Tool/software:

Hi Support Team,

I am referring to the following thread to ask questions
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/747742/am4372-power-up-down-sequence

Q1: Is my understanding correct as follows?

- When all VDDSHVx are 3.3V, even if they are started by the simplified power sequencing shown in Figure 5-8,
  it should be stopped in the reverse order of the startup.

- If all the power supplies are shut down at the same time, the voltage difference between VDDS and VDDSHVx should always be less than 2V.

Q2: However, 5.12.1.3 also includes the following description, and if it is as described, the sequence in Fig. 5-8, where 3.3V is started up first
      (3.3V → 1.8V, so when shutting down, 1.8V → 3.3V is used to shut down?)       
      Which has higher priority, shutting off in the reverse order of startup or shutting off VDDS and VDDS_CLKOUT after VDDSHVx?

      “The VDDS, VDDS_CLKOUT power supply must ramp down after all 3.3-V VDDSHVx [x=1-11] power supplies.”

Q3: What is the possible fault if the shutdown sequence cannot be met?
       Is it possible that the customer's application may cause the power supply to be cut off,
       which in the worst case scenario could lead to CPU damage?

Best Regards,
Kanae

  • 0
    TI__Guru**** 159249 points

    Hello Kanae

    Thank you for the query.

    I am reviewing the inputs.

    Oue device expert is on vacation till the 6th of Jan. Please expect delay in response.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru 59735 points

    Figure 5-8 only applies when using the internal IOLDO to source the VDDS and VDDS_CLKOUT terminals. In this use case, the IOLDO must be powered from the same 3.3V power source that is sourcing the VDDSHVx power rails operating at 3.3V. The IOLDO will ensure the potential difference between any VDDSHVx power rail operating at 3.3V will never exceed the 2V difference allowed relative to the 1.8V VDDS and VDDS_CLKOUT power rails being powered by IOLDO. This occurs because the IOLDO output voltage will track the IOLDO input voltage as it rises from 0V to 1.8V and falls from 1.8V to 0V. The IOLDO output voltage remains at 1.8V while the IOLDO input voltage is greater than 1.8V. So, the worst-case voltage difference for this use case is about 3.3V - 1.8V = 1.5V.

    VDDS and VDDS_CLKOUT must ramp-up before, ramp-down after, or at the same time as any VDDSHVx power rail operating at 3.3V. Any VDDSHVx power rail operating at 3.3V must never have a potential greater than the potential applied to VDDS and VDDS_CLKOUT plus 2V when ramping at the same time as VDDS and VDDS_CLKOUT.

    The AM437x device may be damaged if your system allows any VDDSHVx power rail operating at 3.3V to have a potential greater than the potential applied to VDDS and VDDS_CLKOUT plus 2V.

    Regards,
    Paul

  • 0 in reply to peaves
    Mastermind 9885 points

    Hi Paul,

    Thank yo for your support.

    Our customer has the following comments and additional questions.

    *************************************************************************************************************

    I understand that under the above conditions, the sequence between VDDS and VDDS_CLKOUT
    and VDDSHVx need not be considered as long as the 3.3V supply source is the same.

    Q1. My understanding is as follows.

    - In case of any startup sequence, it is recommended that the shutdown sequence be the reverse
     of the startup sequence.

    - Especially for VDDS, VDDS_CLKOUT and VDDSHVx, the potential difference must always be
     less than 2V during the sequence or it may lead to damage.

    Q2. If VDDS, VDDS_CLKOUT, and VDDSHVx ramp down before the other power supplies
     during the shutdown sequence, will this also lead to damage?


    3. Questions about the following statement in the data sheet: 5.12.1.3 Power-Down Sequencing.

    This ensures there would be no spurious current paths during the power-down sequence.

    3-1. what are spurious current paths in the first place?

    3-2. What is the problem when spurious current paths occur?

    *************************************************************************************************************

    Best Regards,
    Kanae

  • 0 in reply to Kanae
    Mastermind 9885 points

    Hi Paul,

    Thank you for your support.
    In addition to the above confirmation, the customer has the following question.

    I think it is desirable to use the recommended IC “TPS65218D0” to protect the startup shutdown sequence,
    but I wonder if the recommended power IC function cannot be used for the type of model that disconnects
    the original power supply from the always-on state, because the original power supply to the recommended IC
    is disconnected in the first place. In such a case, the startup shutdown sequence should be protected.

    If there is any other recommended method to follow the startup shutdown sequence in such a case,
    please let us know.
    Is there any other way than to keep the original power supply on until the shutdown sequence is completed?

    Best Regards,
    Kanae

  • +1 in reply to Kanae
    TI__Guru 59735 points

    The bullets after Q1 appear to be statements rather than questions. Are they asking if the statements are true?  If so, the answer is yes. 

    The VDDS and VDDS_CLKOUT relationship to VDDSHVx is the only one that I 'm aware of that will damage the device. The other power sequence requirements are defined to provide predictable operation during power-up and power-down. However, there may be unknown spurious current paths that occur and there is a chance they may damage the device. 

    We only validated the operation of the device with the power sequence defined in the datasheet, so any deviation from the sequence may produce unexpected results.

    One example of a spurious current path would be when you apply potential to an IO that is not fail-safe when it doesn't have power applied. The potential applied to the IO is likely to turn on ESD protection circuits that would allow unexpected injection current to flow from the IO to other power rails which may be connected to the power rails of attached devices. The ESD circuit passing the current was only designed to protect the IO from short duration ESD events rather than carrying steady-state current. This spurious current could damage the ESD circuits in the processor and/or cause false start-up issues for attached devices. There could be many spurious current paths through a device when the recommended power sequence is not followed. Some of these paths may be unknown to TI since we only validate the device operation with the recommended sequence. Therefore, we encourage everyone to follow the recommended sequencing of power rails.

  • +1 in reply to peaves
    TI__Guru 59735 points

    I agree PMICs may not be able to complete the power-down sequence if the applied power decays too quickly. This can be prevented by providing an early power failure detect circuit that triggers the PMIC power-down sequence along with enough capacitance to hold the PMIC input valid until it has time complete its power-down sequence.

    Regards,
    Paul