• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 404 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM62A7: Questions about SBL M4 Firmware Loading, Third-Party HSM Stack, and Security Handover

Cesc Yang
Prodigy 231 points
Part Number: AM62A7

Tool/software:

Hello TI experts,

I have three technical questions regarding the AM62Ax series processors:

1. SBL M4 Firmware Loading
In the AM62Ax Sitara Processors Technical Reference Manual, Section 5.2.3 "Boot Process Flow," it states:
SBL must load the M4 firmware provided by TI otherwise an R5 reset will occur as a preventive measure against software misbehavior.
However, in the SDK SBL example's main() function, I only see the call to Bootloader_socWaitForFWBoot().
Does the "FW" here refer to SYSFW? If so, where exactly is the SYSFW loaded in the SBL?

2. Third-Party HSM Stack
If a third-party HSM stack firmware is flashed, how can we ensure it runs on the HSM core? When sending TISCI messages, how can we guarantee they are directed to the HSM core rather than the TIFS core?

3. Security Handover on AM62Ax
In the SDK example tisci_msg.c, there is a function TISCIApp_procHandover() that uses Security Handover. However, in the official TISCI documentation (Docs » Chapter 6: Topic User Guides » Performing Security Handover), it mentions:
This document is only applicable to devices AM64.
Does this mean the Security Handover guide is not applicable to AM62Ax? If so, what documentation should I reference for Security Handover on AM62Ax?

Thank you in advance for your assistance!

Best regards,
Yang

  • 0
    TI__Guru 70521 points

    Hello,

    1. That description is related to the legacy boot flow. The SDKs use the Combined boot flow where the ROM itself boots the TIFS firmware.

    2. The TISCI protocol is for communicating with the TIFS firmware running on the TIFS core. Please contact your HSM vendor for the communication protocols like IPC it supports.

    3. The Security Handover is not application for AM62 family of devices.

    Regards,

    Prashant

  • 0 in reply to Prashant Shivhare
    Prodigy 231 points

    Hi Prashant,

    Thank you for your detailed response to my previous questions, especially regarding points 1 and 3.

    Regarding point 2, I would like to clarify further:
    We are actually developing an HSM stack for the AM62Ax family. To proceed, I would like to ask the following:

    1. What TI resources can we apply for to assist in HSM development specifically for AM62Ax? How can we apply for them?
    2. Currently, we have access to TIFS v09.00.06, which can be configured for AM62Ax during compilation. Additionally, we have access to security resources, which include the Keywriter software and some architecture-level documentation on security principles. However, these resources do not appear to include any code-level support. Would these, along with TIFS v09.00.06, be sufficient to support HSM development for AM62Ax?
    3. In the MCU Plus SDK and the TIFS package, we couldn’t find inter-core communication configurations (e.g., source and destination parameters for IPC). Are there any examples or references available for this aspect of development?

    Your insights and guidance would be greatly appreciated.

    Best regards,
    Yang

  • 0 in reply to Cesc Yang
    Prodigy 231 points

    Hi Prashant,

    While reviewing the TRM, I found the following information in Section 8.3 about SEC_PROXY:

    The third IPC hardware mechanism is to use SEC_PROXY, which provides an IPC mechanism for carrying large messages for complex communications among processors. It allows processors to read and write messages in small chunks.
    There are two SEC_PROXY instances on the device: one dedicated for IPC for HSM M4F, and the other for the rest of the system. Events generated by SEC_PROXY are sent to interrupt aggregators, which then convert these events into processor interrupts. The utilization of SEC_PROXY is user-defined through memory map allocation, with each processor allocated its own SEC_PROXY region for sending and receiving IPC messages.

    Are there more detailed descriptions available for SEC_PROXY usage in AM62Ax, especially how the memory map allocation and interrupt handling are configured?

    Best regards,
    Yang

  • 0 in reply to Cesc Yang
    TI__Guru 70521 points

    Hi, I am closing this thread as this is continued in your other thread:

    e2e.ti.com/.../am62a7-confirming-hsm-communication-setup-and-firmware-loading