SK-AM64B: AM64x PRU

Hi Murat,

How are you configuring PRU UART? Can you give some insights on this.

Which SDK are you using?

Regards,

Vaibhav

Hello Vaibhav. I am configuring PRU UART from R5-0-0 Core FIFO mode. But i want to make it work with DMA from R5-0-0 Core. I dont understand what should i do because PRU UART support is not mentioned in PDMA. 

However in PRU UART, it is mentioned that there is two DMA events. But as i said i dont know what to do with it. (Receive event (URXEVT) and Transmit event (UTXEVT)) 

I am using SDK 10.0.0.20

Thank you

Hi Murat,

Thanks for confirming about the SDK version. Allow me sometime to check on your query and put my responses here.

Regards,

Vaibhav

Hi Murat,

I have reassigned the thread to the correct expert. You can expect to hear back from them.

Regards,

Vaibhav

Thank you Vaibhav. I am wating for reply.

Murat

Hi Murat,

From my understanding, you have already implemented controlling the PRU hardware UART from R5F0_0 core. Next, you will have to configure to trigger DMA by PRU UART Rx/Tx event. Do correct me if my understanding is wrong.

Our DMA expert is out-of-office this week. Please expect a delay in response time.

Regards,

Nitika

Hello Ntika

Yes, that is my situation. 

Hello Nitika/Murat,

Customers can use PRU DMA and not the MAIN DOMAIN DMA from the R5F core.

Because the MAIN DOMAIN DMA channels are not assigned to PRU UART and  MAIN DOMAIN DMA channels are assigned to MAIN UART's only .

Regards,

Anil.

Hello Anil

I understand. Is there a example for using PRU DMA?

Thank you

Which dma is mentioned here?

6.4.8.3.6 PRU_ICSSG UART DMA Event Support In the FIFO mode, the PRU_ICSSG UART0 generates the following two DMA events: • Receive event (URXEVT): The trigger level for the receiver FIFO (1, 4, 8, or 14 characters) is set with the FIFO control UART_INT_FIFO[7-6] IIR_FIFOEN bitfield. Every time the trigger level is reached or a receiver time-out occurs, the PRU_ICSSG UART0 sends a receive event to the DMA controller. In response, the DMA controller reads the data from the receiver FIFO by way of the receiver buffer register UART_RBR_TBR[7-0] RBR_DATA. Note that the receive event is not asserted if the data at the top of the receiver FIFO is erroneous even if the trigger level has been reached. • Transmit event (UTXEVT): When the transmitter FIFO is empty (when the last byte in the transmitter FIFO has been copied to the transmitter shift register), the PRU_ICSSG UART0 sends an UTXEVT signal to the DMA controller. In response, the DMA controller refills the transmitter FIFO by way of the transmitter holding register (THR) - UART_RBR_TBR[7-0] RBR_DATA. The UTXEVT signal is also sent to the DMA controller when the PRU_ICSSG UART0 is taken out of reset using the [14]UTRST bit in the power and emulation management register (UART_PWR). Activity in DMA channels can be synchronized to these events. In the non-FIFO mode, the PRU_ICSSG UART0 generates no DMA events. Any DMA channel synchronized to either of these events must be enabled at the time the PRU_ICSSG UART0 event is generated. Otherwise, the DMA channel will miss the event and, unless the PRU_ICSSG UART0 generates a new event, no data transfer will occur.

Also in PRU UART, there is a word "EDMA" which is used only 3 times throughout of 10000 page TRM. One of this times it is explained as Embedded DMA, while in AM335, EDMA Stands for Enhanced DMA.

Hello, it has been 17 days since i have asked this question and my problem is not solved yet. Technical Reference Manual is really undetailed about this in my opinion. Please show me a way that i can use PRU DMA for PRU UART.

Thank you

Murat

Hi Murat,

Apologies for the delayed response. I will state the discussion we've had with the dev team so far:

1. The DMA mentioned in section 6.4.8.3.6 of the TRM looks like SoC DMA. We do not have a reference code yet for this implementation but if the events are mapped SoC DMA controller then you might be able to use this method. However currently, we don't have any example which supports this.

2. Alternate way is XFR2DMA. This DMA uses PSIL threads for data exchange over the SoC PSI switch/PSI bus.
We don’t have examples in the SDK but the PRU ICSSG Ethernet team uses this DMA in their firmware today for Ethernet packet exchange.

I will have to get more information on this implementation and get back to you.

Regards,

Nitika

Hello Nitika

If your PRU ICSSG Ethernet team can explain the process to make XFR2DMA that would be great.

Thank you

Hello, i am pinging this thread because my problem is not solved yet.

Best Regards

Murat

Hi Murat,

Thank you for the ping. I misunderstood the Ethernet team's implementation, we use XFR2VBUS hardware accelerator based mem copy and not xfr2dma.

Please find the steps below for XFR2VBUS usage:

You will have to map the PRU internal interrupt signals below to Host 0 or 1. With this configuration you will be able to poll R31 register bits 30/31 to get the UART Rx/Tx interrupts.

1. In Sysconfig, add 2 instances under PRU (ICSS) > INTC Internal Signals Mapping to map Event Signal 4 and 5 to Host 0/1. This will add the PRUICSS_IntcInitData structure to ti_drivers_config.c.

2. In your code, call the PRUICSS_intcInit API to initialise the interrupt controller. Refer here.

3. Next, you will have to write the firmware for the PRU core with the following implementation:

- Poll the bit 30/31 of R31 register to wait for the interrupt.

- Jump to an Event handler if interrupt occurs and clear the interrupt status (refer line 187-188 here)

- Use XFR2VBUS hardware accelerator to read from the FIFO to the memory location and vice versa based on the interrupt. You can refer to programming guide section in the TRM - 6.4.6.3.1.6 XFR2VBUS Programming Model and this E2E.

Regards,

Nitika