J784S4XEVM: How to generate test pattern (PRBS) from SERDES ?

Part Number: J784S4XEVM
Other Parts Discussed in Thread: AM69

Tool/software:

Hello,

We are struggling to get 10G ethernet working on our J784S4XEVM. To make sure the issue is not coming from our hardware connection, I would like to generate a test pattern (ideally PRBS31) on Serdes2 Lane2.

  1. Is there a way to set the serdes in a test mode to generate PRBS31 pattern ?
  2. Is there a way to have the serdes check a received PRBS31 pattern and output the number of bit errors ?
  3. Are there other tools to help tune the serdes channels such as on-die eye diagrams ? 
  4. If the answer is yes to any of the above, can it be applied to any Serdes and bitrate ? (it would help a lot for other links such as PCIe later in our developpement)

Thanks & Regards,

Thibaut

  • Thibaut,

    What is the issue in getting the 10G ethernet to work? Internally we had verified 10G USXGMII to be working before releasing it.

    Yes, we do have the ability to generate PRBS patterns in the SERDES TX.

    offset is 0x4000+(a*0x400)+0x280; a= 0...3.

    And there is on-die eye diagram capability to estimate the eye diagram and yes, it is applicable on all SERDES and all bit rates; although I have not tested it on the PCIe itself.

  • Shreyas,

    Thank you for the answers. The issue for 10G ethernet is handled in another post with my colleague:

    (1) J784S4XEVM: How to configurate the clock to use for 10G XFI - Processors forum - Processors - TI E2E support forums

    Basically, we can get the Jacinto to loop data to itself, but can't get it to communicate with external devices (such as ethernet switch or phy to base-t connector). We are currently looking at potential protocol issues.

    Are there any documentation and/or tools to use the on-die eye diagram ?

    Thanks & regards,

    Thibaut

  • If you have your email, please share it privately and I can send the code out to you.

  • Have you tried to use 1G and does that work without issues? Issue is only with the 10G serdes?

    What is the ref clock freq? USXGMII supports 156.25MHz ref clk.

  • We have used 1G successfuly in SGMII mode, not in USXGMII.

    Ref clock is internally generated by AM69 @156.25MHz.

    At 10G we have checked the register XGMII1_LINK at address 0x0C00 0074, and the register value is 1, which means XGMII1 is up. But we are not sure what this bit actually covers. We're trying to figure out if this only means some kind of activity is detected, or if the Rx CDR PLL locked successfully, if some kind of protocol handshake succeeded, or something similar. Any idea ?

    Thanks & regards,

    Thibaut

  • Thibaut,

    You could check at SERDES offset 0xe000 bits 23/22 to see if the internal PLL1 and PLL0 are locked. PLL1 if not used may not be locked but PLL0 should be locked.

    If you could also share your email, or you could send me an email shreyas.rao (at) ti.com.

    I will also discuss this internally and will reach out.

  • Shreyas,

    PLL was checked in the other thread, it is locked:

    We have 10G working when we connect Jacinto Serdes Tx to Rx, the problem is we cannot connect to any device other Jacinto.

    I sent you my direct email adress via private message, could you send me the on-die eye diagram tool/documentation ?

    Thanks & regards,

    Thibaut

  • Thibaut,

    Replied to you in the private message. Thank you.