DRA821U-Q1: PCIe RefCLK Termination Resistors Disabled?

Luke

Part Number: DRA821U-Q1
Other Parts Discussed in Thread: DRA821, DRA829, TDA4VM, DRA821U

Tool/software:

Hi team,

I remember that on preproduction DRA821 the PCIe RefCLK termination resistors were not disabled by default.

Do you know if the production DRA821U4T5BALMRQ1 chips have the PCIe RefCLK termination resistors disabled as default setting?

Best,

Luke

11 months ago

+1 Takuma Fujiwara 11 months ago

TI__Guru 54283 points

Hi Luke,

I notified Robert who helped out on that previous thread to see if he has different comments for DRA821.

Regards,

Takuma

0 Robert Eschler 11 months ago in reply to Takuma Fujiwara

TI__Guru 53505 points

DRA821 should be same as DRA829/TDA4VM - so linked E2E should still apply.

0 Luke 11 months ago in reply to Robert Eschler

TI__Expert 4070 points

Rob/Takuma,

Understood, thanks for pointing me to the other thread!

Best,

Luke

0 Luke 10 months ago in reply to Luke

TI__Expert 4070 points

Robert/Takuma,

One quick follow up on this one:

I understand that the termination is disabled by default on the DRA821U. Even though this is the case, the SERDES rails still must be powered up before applying a clock to the SERDES reclk inputs... so if my customer is sourcing their clock from a carrier board and sent to the DRA821 on a mezzanine card, they are still going to need to gate the clock output on the carrier board, correct?

Thanks,

Luke

+1 Robert Eschler 10 months ago in reply to Luke

TI__Guru 53505 points

Cannot drive clock into REFCLK pins if processor is not fully powered, so yes would need to gate/disable CLK until device is powered.

0 Luke 10 months ago in reply to Robert Eschler

TI__Expert 4070 points

Perfect, that's what I thought.

Thanks Robert!

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DRA821U-Q1: PCIe RefCLK Termination Resistors Disabled?