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AM62P: Watchdog support in U-Boot (R5) SPL

Christian Neuwirth
Prodigy 120 points
Part Number: AM62P

Tool/software:

Hello TI experts:

We have a need to enable a watchdog in U-Boot SPL, specifically on the R5. However, it seems that there is no support for that in the AM62P (and others AM62x derivatives). Such support becomes available in U-Boot proper  on the A53 only. I have found this forum thread that seem to confirm that:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1315701/am6422-enable-the-mcu-rti_wdt-in-r5-spl

This thread says at the very end "I'm not aware of support on patting RTI_WDT @SPL/u-boot level." I've also tested it myself. Apparently, the device/driver class UCLASS_WDT becomes available in U-Boot proper running on the A53 only even though I’m not sure where or how watchdog support is stripped from the device tree and/or code when U-Boot SPL for either the R5 or the A53 is built.

Obvious questions:

  • Why is there no watchdog support in U-Boot SPL?
  • What do I need to do to enable such support?
  • 0
    TI__Guru** 101240 points

    Hello,

    My assumption is that you just want to make sure that your SPL / uboot does not lock up. If you have a different usecase in mind:

    How long are you planning on running your U-Boot SPL?

    What kind of timeout are you expecting to set?

    Are you expecting SPL to actually pet the watchdog? Or are you simply starting the watchdog, and planning for something later in your boot flow to start petting the watchdog?

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Prodigy 120 points

    Hi Nick,

    Nick Saulnier said:
    Or are you simply starting the watchdog, and planning for something later in your boot flow to start petting the watchdog?

    That was the idea.

    We are designing a new HW platform based on the AM62P and U-Boot SPL locks up occasionally (but rarely). Most probably this is due to a HW issue which will get fixed at some point, but for the time being I was thinking about enabling a watchdog to recover from such failures.

    Does it matter why I'm asking these questions?

  • 0
    Prodigy 120 points

    I figured out how watchdog (device) support is stripped from the device tree. bootph-all (or the lack thereof) does the trick. Probably should have known that.

    There is another issue, though:
    Power and clock management is essentially hard-coded at this stage.
    See arch/arm/mach-k3/am62px/dev-data.c and arch/arm/mach-k3/am62px/clk-data.c in the U-Boot sources.

    In other words:
    Any SoC peripheral one wants to use (on top of what is supported "out of the box") in either R5 or A53 U-Boot SPL needs to be added there.

    However, there is literally no documentation in the source code and the documentation in the TRM of the AM62P is also not entirely clear. For instance:

    • There is no mapping between "Power Domain Name" and its corresponding device ID.
    • I have no idea how I would add support for the PSC WKUP_PSC0.

    The clock trees appear to be documented here. I have not found a corresponding documentation for power management, though.

    Any help would be appreciated.

  • +1 in reply to Christian Neuwirth
    TI__Mastermind 18350 points

    Hi Christian,

    I'm not familiar with the contents of the dev-data.c and clk-data.c files so I'm not sure what the code does in those files.

    Typically Power Domains and LPSCs are assigned relative to the TRM. You can refer to the AM62P TRM Table 6-6. LPSC Features: https://www.ti.com/lit/pdf/spruj83

    Or the DM Firmware defines the PDs and LPSCs the exact same way in the MCU+ SDK source code: <install path>/drivers/device_manager/rm_pm_hal/rm_pm_hal_src/pm/soc/am62px/devices.c

    For clocking, again I'm not familiar with those files. If the file defines the clocks relative to the peripheral level (for example, lets say OSPI needs to be 166MHz) then its most likely following the TISCI protocol that you've linked above. Rather if the file defines the clocks relative to the PLLs and HSDIVs, then refer to the TRM again, section 6.4.5 PLL.

    The Clock Tree Tool is useful for visualizing the whole clocking architecture: https://dev.ti.com/sysconfig/#/config/?args=--product%20%2Fmnt%2Ftirex-content%2Fsitara_ctt_1_1_2%2F.metadata%2Fproduct.json%20--device%20AM62Px

    Best Regards,

    Anshu

  • 0 in reply to Anshu Madwesh
    TI__Genius 15855 points

    Hi Anshu,

    In communicating with Christian today, while he admitted that they still need to run further review of the MCU+ SDK, neither he or I are not sure if this will shed more light on these (documentation) issues highlighted above.  As was pointed out in the earlier posts, the information in the TRM is either incomplete or not easily understood.

    Would it be possible to provide an additional review on this, and comments specific to Christian's most recent post above?

    Thank you,

    Chris

  • 0 in reply to Chris Yorkey
    TI__Guru** 101240 points

    Hello all,

    Apologies for the delayed responses here. I am finally able to start pivoting back to the forums. I am catching up on a lot of threads, so do not be afraid to ping the thread if I have not responded within a couple of business days.

    Are there any updates I should be aware of before spending more time on this thread?

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Prodigy 120 points

    Hi Nick, no there are no updates.

    Thx,
    Chris.

  • 0 in reply to Christian Neuwirth
    TI__Guru** 101240 points

    Hello all,

    Table 6-6. LPSC Features that Anshu pointed to is useful.

    Watchdog timer is called RTI (see later chapter peripherals > Timer Modules > RTI-Windowed Watchdog Timer (WWDT).

    So if you are using WKUP_RTI0, then it would already have power since it uses LPSC_MAIN_DM, same as WKUP_R5FSS0. That is the watchdog timer that would usually be associated with the DM R5F core. That is the R5F core running the R5F half of the SPL:
    https://software-dl.ti.com/processor-sdk-linux/esd/AM62PX/10_00_07_04/exports/docs/linux/Foundational_Components/U-Boot/UG-General-Info.html#boot-flow 

    Similarly, you can see that the RTI associated with each A53 core is on the same LPSC as the A53 core.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Prodigy 120 points

    Sorry for the delay Nick and Anshu.

    The problem with the code I pointed out earlier is that is uses a few literals that don't appear to be documented anywhere. At least the ones that are referring to power domains. For instance (from arch/arm/mach-k3/am62px/dev-data.c):

    static struct ti_pd soc_pd_list[] = {
        [0] = PSC_PD(0, &soc_psc_list[0], NULL),
        [1] = PSC_PD(3, &soc_psc_list[0], &soc_pd_list[0]),
        [2] = PSC_PD(4, &soc_psc_list[0], &soc_pd_list[1]),
        [3] = PSC_PD(13, &soc_psc_list[0], &soc_pd_list[0]),
    };

    I'm referring to the literals used as first argument of the PSC_PD macro. The code uses a bunch of other literals for which I could find documentation here or there. The ones above remain a mystery, though.

    However:
    This code is from TI SDK AM62Px 09.02.01.09. Apparently this has changed with SDK 10.x. Power and clock mgmt appear to be device tree driven now. Also the code in the in the MCU+ SDK pointed out by Anshu appears to be much better documented and makes more sense.

    As such, I consider this issue as resolved. Thx.