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Original question:

TDA4VH-Q1: Adding flow control inside the CPSW9g switch of the SOC Jacinto

TDA4VH-Q1: Adding flow control inside the CPSW9g switch of the SOC Jacinto

Wissam Makhlouf
Prodigy 40 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Hello, I am taking over this thread : TDA4VH-Q1: Adding flow control inside the CPSW9g switch of the SOC Jacinto - Processors forum - Processors - TI E2E support forums

As agreed in December, did you setup a test in which the Jacinto generates pause frames?

Thank you,

Kind regards,

Wissam

  • 0
    TI__Guru 65150 points

    Hi, 

    Let us check on TI EVM and update you on this. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    Thank you

    Kind regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    We are working on this to confirm, expect some update by end of Next week.
    Kindly wait for response.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    Do you have any news regarding this topic?

    Thank you,

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    We have observed pause frames when connecting two TI SoCs using CPSW9G external ports  and transferring data between external ports but, not when transferring the data to Host Port.

    Let me reconfirm the same once, and update you soon.

    Best Regards,
    Sudheer 

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    Thank you for the update. No problem we can the reconfirmation.

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    Wissam Makhlouf said:
    Thank you for the update. No problem we can the reconfirmation.

    Sure, Can you also check by transferring traffic between external ports and keeping CPU at max load in peer side of one of external port.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    When keeping the CPU at max load, we see that the pause frames are received by the external port but not transmitted to the host port, it seems the problem is at switch level.

    Thank you,

    Best regards,
    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    HI, 

    Wissam Makhlouf said:
    When keeping the CPU at max load, we see that the pause frames are received by the external port but not transmitted to the host port, it seems the problem is at switch level

    Pause frames will be honoured by external port itself the same will not be transfer to host port. 

    If external port fifo is full hist port will not forward any packets to it, host port will back pressure to UDMA and will not accept any new packet submission from application. 

    As per my understanding, your issue was don't seen any tx pause frame statists from CPSW. 

    As I have informed above when we are communicating between two SOCs in external forward connection observed pause frames sent from CPSW. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    Sorry I made a mistake, your understanding is right, we don't see any tx pause frame from CPSW.

    I have a question regarding your comment above, is it right that you observed pause frames when sending data from Core A SOC A to Core B SOC B?

    Then when you say this, do you mean that you transmitted data between 2 cores in the same SOC?

    Doredla Sudheer Kumar said:
    not when transferring the data to Host Port

    Thank you,


    Kind regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi, 

    Wissam Makhlouf said:
    I have a question regarding your comment above, is it right that you observed pause frames when sending data from Core A SOC A to Core B SOC B?

    Yes, between two SOCs I.e using two TI EVMs.

    Wissam Makhlouf said:
    Then when you say this, do you mean that you transmitted data between 2 cores in the same SOC?

    No, between two SOCs. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    Sorry for the deyal, I saw that my message didn't go. Indeed if you see pause frames on external ports and not on host port, it means CPSW sends pause frames. Can you share with me the stats to know what we should expect, and the changes you made so that we can reproduce it?

    Thank you,

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    Wissam Makhlouf said:
    Indeed if you see pause frames on external ports and not on host port, it means CPSW sends pause frames. Can you share with me the stats to know what we should expect, and the changes you made so that we can reproduce it?

    Yes, will share the statistics and test setup details along with changes.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello, thank you, by what means do you plan to share it with us?

    Thank you,

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    Wissam Makhlouf said:
    Hello, thank you, by what means do you plan to share it with us?

    Sorry for delay, Due to HW Un-avaiablity capturing logs were delayed.

    Will try to provide the setup diagram and CPSW statistics by end of this week.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru 65150 points

    Hi,

    Please find the below data where I have confirmed pause frame transmission from CPSW MAC Port to avoid packet drops.
    Below captures iperf when flow control enabled, and disabled case.

    Flow control is enabled/disabled by register write of PN_MAC_CTRL register.

    Note:
    In case of ETHFW to check flow control we need to disable "ETHFW_MONITOR_SUPPORT" as no from ETHFW build flags.

    Also, refer to CPSW statistics, when flow control is disabled observe top-of-fifo drop at MAC port and equivalent packet drop in other external port where data has to be forwarded.

     ====== Iteration 5 =====

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 56828
  rxBcastFrames           = 31
  rxMcastFrames           = 6479
  aleDrop                 = 67
  rxOctets                = 61322176
  txGoodFrames            = 51293
  txBcastFrames           = 27
  txMcastFrames           = 948
  txOctets                = 60882800
  octetsFrames64          = 2472
  octetsFrames65to127     = 4958
  octetsFrames128to255    = 33
  octetsFrames256to511    = 46
  octetsFrames1024        = 100612
  netOctets               = 122204976
  portMaskDrop            = 77                                                   
  alePolicyMatch          = 6438                                                 
  txPri[0]                = 51293                                                
  txPriBcnt[0]            = 60880292                                             
                                                                                 
 External Port 2 Statistics                                                      
-----------------------------------------                                        
                                                                                 
 External Port 3 Statistics                                                      
-----------------------------------------                                        
  rxGoodFrames            = 1615293                                              
  rxBcastFrames           = 16                                                   
  rxMcastFrames           = 949                                                  
  rxOctets                = 2450557002                                           
  txGoodFrames            = 1766220                                              
  txBcastFrames           = 21                                                   
  txMcastFrames           = 1550929                                              
  txPauseFrames           = 1544793                                              
  txOctets                = 114460250                                            
  octetsFrames64          = 1547264                                              
  octetsFrames65to127     = 219912                                               
  octetsFrames128to255    = 13                                                   
  octetsFrames256to511    = 41                                                   
  octetsFrames512to1023   = 4                                                    
  octetsFrames1024        = 1614279                                              
  netOctets               = 2565017252                                           
  rxBottomOfFifoDrop      = 389                                                  
  aleUnknownUcast         = 4                                                    
  aleUnknownUcastBcnt     = 298                                                  
  aleUnknownMcast         = 1                                                    
  aleUnknownMcastBcnt     = 72                                                   
  aleUnknownBcast         = 4                                                    
  aleUnknownBcastBcnt     = 1364                                                 
  alePolicyMatch          = 949                                                  
  txPri[0]                = 215304                                               
  txPri[6]                = 6122                                                 
  txPri[7]                = 1                                                    
  txPriBcnt[0]            = 15111684                                             
  txPriBcnt[6]            = 481750                                               
  txPriBcnt[7]            = 64                                                   
                                                                                 
 External Port 5 Statistics                                                      
-----------------------------------------                                        
  rxGoodFrames            = 265624                                               
  rxBcastFrames           = 11                                                   
  rxMcastFrames           = 25                                                   
  aleDrop                 = 22                                                   
  rxOctets                = 75912179                                             
  txGoodFrames            = 1664600                                              
  txBcastFrames           = 22                                                   
  txMcastFrames           = 321                                                  
  txOctets                = 2510727163                                           
  octetsFrames64          = 45                                                   
  octetsFrames65to127     = 215611                                               
  octetsFrames128to255    = 19                                                   
  octetsFrames256to511    = 43                                                   
  octetsFrames512to1023   = 4                                                    
  octetsFrames1024        = 1714502                                              
  netOctets               = 2586639342                                           
  portMaskDrop            = 22                                                   
  aleUnknownUcast         = 4                                                    
  aleUnknownUcastBcnt     = 1438                                                 
  aleUnknownMcast         = 6                                                    
  aleUnknownMcastBcnt     = 587                                                  
  aleUnknownBcast         = 5                                                    
  aleUnknownBcastBcnt     = 1870                                                 
  alePolicyMatch          = 9408                                                 
  txPri[0]                = 1664285                                              
  txPri[6]                = 310                                                  
  txPri[7]                = 5                                                    
  txPriBcnt[0]            = 2510704523                                           
  txPriBcnt[6]            = 22320                                                
  txPriBcnt[7]            = 320                                                  
                                                                                 
 External Port 6 Statistics                                                      
-----------------------------------------                                        
                                                                                 
 External Port 7 Statistics                                                      
-----------------------------------------                                        
                                                                                 
 External Port 8 Statistics                                                      
-----------------------------------------                                        
                                                                                 
 ====== Iteration 6 =====                                                        
                                                                                 
 Port 0 Statistics                                                               
-----------------------------------------                                        
  rxGoodFrames            = 77509                                                
  rxBcastFrames           = 32                                                   
  rxMcastFrames           = 7794                                                 
  aleDrop                 = 67                                                   
  rxOctets                = 85553504                                             
  txGoodFrames            = 70851                                                
  txBcastFrames           = 30                                                   
  txMcastFrames           = 1138                                                 
  txOctets                = 85025776                                             
  octetsFrames64          = 2973                                                 
  octetsFrames65to127     = 5961                                                 
  octetsFrames128to255    = 36                                                   
  octetsFrames256to511    = 50                                                   
  octetsFrames1024        = 139340                                               
  netOctets               = 170579280                                            
  portMaskDrop            = 79                                                   
  alePolicyMatch          = 7751                                                 
  txPri[0]                = 70851                                                
  txPriBcnt[0]            = 85022764                                             
                                                                                 
 External Port 2 Statistics                                                      
-----------------------------------------                                        
                                                                                 
 External Port 3 Statistics                                                      
-----------------------------------------                                        
  rxGoodFrames            = 3212133                                              
  rxBcastFrames           = 18                                                   
  rxMcastFrames           = 1138                                                 
  rxOctets                = 4874227635                                           
  txGoodFrames            = 1881689                                              
  txBcastFrames           = 23                                                   
  txMcastFrames           = 1552177                                              
  txPauseFrames           = 1544793                                              
  txOctets                = 122669721                                            
  octetsFrames64          = 1547774                                              
  octetsFrames65to127     = 335092                                               
  octetsFrames128to255    = 15                                                   
  octetsFrames256to511    = 49                                                   
  octetsFrames512to1023   = 4                                                    
  octetsFrames1024        = 3210888                                              
  netOctets               = 4996897356                                           
  rxBottomOfFifoDrop      = 389                                                  
  rxTopOfFifoDrop         = 1596                                                 
  aleUnknownUcast         = 5                                                    
  aleUnknownUcastBcnt     = 376                                                  
  aleUnknownMcast         = 1                                                    
  aleUnknownMcastBcnt     = 72                                                   
  aleUnknownBcast         = 5                                                    
  aleUnknownBcastBcnt     = 1705                                                 
  alePolicyMatch          = 1138                                                 
  txPri[0]                = 329525                                               
  txPri[6]                = 7370                                                 
  txPri[7]                = 1                                                    
  txPriBcnt[0]            = 23222941                                             
  txPriBcnt[6]            = 579964                                               
  txPriBcnt[7]            = 64                                                   
                                                                                 
 External Port 5 Statistics                                                      
-----------------------------------------                                        
  rxGoodFrames            = 399209                                               
  rxBcastFrames           = 12                                                   
  rxMcastFrames           = 25                                                   
  aleDrop                 = 22                                                   
  rxOctets                = 108150704                                            
  txGoodFrames            = 3279084                                              
  txBcastFrames           = 25                                                   
  txMcastFrames           = 384                                                  
  txOctets                = 4956093944                                           
  octetsFrames64          = 59                                                   
  octetsFrames65to127     = 329915                                               
  octetsFrames128to255    = 21                                                   
  octetsFrames256to511    = 51                                                   
  octetsFrames512to1023   = 4                                                    
  octetsFrames1024        = 3348243                                              
  netOctets               = 5064244648                                           
  portMaskDrop            = 22                                                   
  aleUnknownUcast         = 6                                                    
  aleUnknownUcastBcnt     = 2762                                                 
  aleUnknownMcast         = 6                                                    
  aleUnknownMcastBcnt     = 587                                                  
  aleUnknownBcast         = 6                                                    
  aleUnknownBcastBcnt     = 2244                                                 
  alePolicyMatch          = 9408                                                 
  txPri[0]                = 3278705                                              
  txPri[6]                = 373                                                  
  txPri[7]                = 5                                                    
  txPriBcnt[0]            = 4956065250                                           
  txPriBcnt[6]            = 26856                                                
  txPriBcnt[7]            = 320                                                  
  txPriDrop[0]            = 1596                                                 
  txPriDropBcnt[0]        = 2422728                                              
                                                                                 
 External Port 6 Statistics                                                      
-----------------------------------------                                        
                                                                                 
 External Port 7 Statistics                                                      
-----------------------------------------                                        
                                                                                 
 External Port 8 Statistics                                                      
-----------------------------------------


    Above Iteration-5 is log with flow control enabled, 6 was with flow control disabled.

    As per above observation, flow control at CPSW external port is working as expected.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello, 

    Thank you for your feedback, I have a few questions : 

    • Do you confirm that the Jacinto core receiving the data (with IP address 192.168.1.100) is a R5F using LWIP as Ethernet stack under FreeRTOS?
    • In no flow control case: there are rxBottomOfFifoDrop and rxTopOfFifoDrop. We suppose that statistic of iteration 6 contain statistics of iteration 5, as rxBottomOfFifoDrop value should come from the case with flow control.
    • In no flow control case: you say” observe top-of-fifo drop at MAC port and equivalent packet drop in other external port where data has to be forwarded.” . Which counter do you refer to ?
    • In control flow enable case: In the iperf logs we see there are no retries, and in parallel, we see rxBottomOfFifoDrops, which means frames have been lost at port input .How is this possible (the TRM says: “This statistic should be zero if proper flow control is being followed”) ?

    • You said “Flow control is enabled/disabled by register write of PN_MAC_CTRL register”. We activated this register in our code (see https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1382087/tda4vh-q1-adding-flow-control-inside-the-cpsw9g-switch-of-the-soc-jacinto/5374783#537478) and it didn’t work. Can you provide us the test code you used ?

    • Do you confirm that this flow control will be also possible on the 2 10GbE CPSW ports ?

    Thank you,

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    Wissam Makhlouf said:
    Do you confirm that the Jacinto core receiving the data (with IP address 192.168.1.100) is a R5F using LWIP as Ethernet stack under FreeRTOS?

    No, Please refer to below Diagram for my test environment.

    Wissam Makhlouf said:
    In no flow control case: there are rxBottomOfFifoDrop and rxTopOfFifoDrop. We suppose that statistic of iteration 6 contain statistics of iteration 5, as rxBottomOfFifoDrop value should come from the case with flow control

    Yes, Flow control will send pause frame when bottomOfFIFO case observed at MAC Port.
    Here, there are no tx drop at port-5.

    Wissam Makhlouf said:
    In no flow control case: you say” observe top-of-fifo drop at MAC port and equivalent packet drop in other external port where data has to be forwarded.” . Which counter do you refer to ?

    Port-3 side rxTopOfDrop.
    " rxTopOfFifoDrop         = 1596 "
    Port-5 side Tx Drop.
      txPriDrop[0]            = 1596                                                 
      txPriDropBcnt[0]        = 2422728 

    Wissam Makhlouf said:
    In control flow enable case: In the iperf logs we see there are no retries, and in parallel, we see rxBottomOfFifoDrops, which means frames have been lost at port input .How is this possible (the TRM says: “This statistic should be zero if proper flow control is being followed”) ?

    No drops here, the scenario was created that bottomOfFIFO drop and MAC Port-3 is sending pause frames to TDA4VH in my above setup.
    You can observe the Tx pause frames "txPauseFrames           = 1544793  "
    So, after seeing Pause frames TDA4VH will control Tx traffic so ,there by no Drops.

    Wissam Makhlouf said:
    You said “Flow control is enabled/disabled by register write of PN_MAC_CTRL register”. We activated this register in our code (see https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1382087/tda4vh-q1-adding-flow-control-inside-the-cpsw9g-switch-of-the-soc-jacinto/5374783#537478) and it didn’t work. Can you provide us the test code you used ?

    You can enable through register as well from ETHFW, If you have a doubt read register value and check whether flow control enabled or not?
    PN_MAC_CTRL register will holds the fields for Tx & Rx flow control enable. Please enable both.
    I have used TI SDK as is, just enabled CPSW statistics capture as communicated you earlier Also, I have disabled Monitor Task in ETHFW as it will perform CPSW recovery when bottomOfFIFO drop observed.

    Doredla Sudheer Kumar said:
    Note:
    In case of ETHFW to check flow control we need to disable "ETHFW_MONITOR_SUPPORT" as no from ETHFW build flags.


    Please check as per above.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    Thank you for the details of your test setup, it is more clear now.

    As I understood you observed pause frames when trying to communicate from one external port to another. I think there was a misunderstanding because on our side we did the test like that : 

    The objective is to be able to generate pause frames when blocking the R5F core using the host port. On our side we observed that the host port was still transmitting data even if we blocked R5F core. I think that, by using 2 external ports the port 0 was not used.

    Additionnally, I had another question, is there a threshold for a FIFO storage to start sending pause frames?

    Thank you,

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    Wissam Makhlouf said:
    Additionnally, I had another question, is there a threshold for a FIFO storage to start sending pause frames?

    Ni, we don't have any specific configuration for the FIFO threshold. 

    Wissam Makhlouf said:

    . I think there was a misunderstanding because on our side we did the test like that : 

    The objective is to be able to generate pause frames when blocking the R5F core using the host port. On our side we observed that the host port was still transmitting data even if we blocked R5F core. I think that, by using 2 external ports the port 0 was not used.

    If R5F is blocked, there won't be any traffic from R5F, if clients are enabled then client can send traffic to CPSW. 

    I am not observed the pause frames w. r. to Host port let me check the same once. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    Indeed, the idea was that the R5F is only a receiver and doesn't send anything.

    From our comprehension, when sending data from a pc while blocking the R5F, the port 0 FIFO should get full. If the port 0 FIFO gets full the switch itself should send the pause frames, that's why we expect pause frames.

    Thank you,

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    Wissam Makhlouf said:
    From our comprehension, when sending data from a pc while blocking the R5F, the port 0 FIFO should get full. If the port 0 FIFO gets full the switch itself should send the pause frames, that's why we expect pause frames.

    I think here is it TOP of FIFO Drop. Let me check the same on my end and update you.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru 65150 points

    Hi, 

    Wissam Makhlouf said:
    From our comprehension, when sending data from a pc while blocking the R5F, the port 0 FIFO should get full. If the port 0 FIFO gets full the switch itself should send the pause frames, that's why we expect pause frames

    I have tested the above scenario, observed that external port always forwarding the packets to host port. 

    I haven't observed any drops at Host Port side as packets sent from external port will land in Tx FIFO of host port not Rx FIFO so, we are not observing the pause frames. 

    Let me check with IP team, where tha packets are lost at Host port as no one is reading the data from Tx FIFO. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru 65150 points

    Hi,

    Doredla Sudheer Kumar said:
    Let me check with IP team, where tha packets are lost at Host port as no one is reading the data from Tx FIFO. 

    Yes, There is no back pressure for the Host port receiving traffic from external ports.
    If Host Port back pressures it will block external port to external port forwarding it should not be as per switch behavior.

    Here, application should take care of traffic handling at higher layer like TCP.

    The only way to initiate pause frames from external ports when is not able to forward the traffic to other external ports.
    The same we have confirmed above.

    If you specify your use case and maximum traffic rate, we can provide some inputs if required.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello, 

    Thank you for reaching the IP team and for your feedback.

    So as we understand, if host port back pressures block external port to external port transfer, iit means it blocks the normal behavior of the switch. It means that the behavior between external ports depend on the host port. Can you please clarify the reason to this?

    Thank you for your proposal. On our side, it looks like a bad news, because handling the traffic with TCP will reduce our speed.

    Thank you,

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    Wissam Makhlouf said:
    It means that the behavior between external ports depend on the host port. Can you please clarify the reason to this?

    No, Host Port is independent. It will not impact external port to external port forwarding until it has large amount of packets to occupy the whole bandwidth of Port.

    Wissam Makhlouf said:
    if host port back pressures block external port to external port transfer, iit means it blocks the normal behavior of the switch.

    Above will be one of reason why flow control not apply when forwarding traffic from external port to Host Port.
    It is basically you are asking s/w bottleneck (not scheduling your task to free the DMA to read packets from Host Port) handle in H/W.
    If an exception occurs internally in s/w switch will not function as per your request.
    Above is not the functionality of any switch. It will always allow to switch traffic from external ports.

    Wissam Makhlouf said:
    Thank you for your proposal. On our side, it looks like a bad news, because handling the traffic with TCP will reduce our speed.

    What is your use-case, is your s/w is not reading data from Host Port?
    Also, what is the throughput rate to your Host Port i.e. Internal consuming and how much is forwarding/switching traffic.

    Switching b/w ports will happen at Link rate.

    Please analyze what is needed from your use-case point of view.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    We understand that to observe pause frames from the host port, the maximum bandwidth should be reached on the port itself.

    In our case, we need to read from host port from the two 10G external ports, that's why we thought pause frames would be useful. If you have information on the supported bandwidth it would be welcome.

    Thank you,

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    Wissam Makhlouf said:

    We understand that to observe pause frames from the host port, the maximum bandwidth should be reached on the port itself.

    In our case, we need to read from host port from the two 10G external ports, that's why we thought pause frames would be useful. If you have information on the supported bandwidth it would be welcome.

    Even switch supports to accept 20G form two ports.
    Internal cores like R5F or A72  and s/w stack running can't handle the traffic of 20G.

    Are you planning to run at 20Gbps data handling in R5F or A72 cores?

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    We are planning to distribute this 20G data on multiple cores. We also plan to do some bench to evaluate what is possible.

    Thank you,

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    HI, 

    Wissam Makhlouf said:
    We are planning to distribute this 20G data on multiple cores. We also plan to do some bench to evaluate what is possible.

    20Gb also can't possible from TI SDK software. 

    You need make more customizations and involve all cores and even A72 side also need to make custom driver changes by passing the network stack for data exchange. 

    If you need any DSP & deep learning applications can run on DSP cores in parallelly. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru 65150 points

    Hi,

    Conclusion of this Topic:

    Pause frames originating from the Host Port when Internal cores of SoC (e.g. R5F/A72) are not able to process the packets received at the Host Port is not the expected behavior.
    This situation leads to the following issues:
    1) It blocks traffic from other ports attempting to to reach to Host Port
    2) It also blocks forwarding between external ports.

    Therefore, pause frames are expected only during traffic forwarding between external ports, and only in the case where there's a mismatch in ports speed or congestion caused by traffic from Host Port or other external ports.

    This has been confirmed, and the relevant CPSW statistics have been shared for reference.

    If zero packet drops are expected due to load on internal cores like R5F or A72, the application must implement appropriate logic for flow control from software.

    Kindly let us know, Is there any further assistance needed on this topic.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    Thank you very much for suming up the topic.

    Doredla Sudheer Kumar said:
    No, Please refer to below Diagram for my test environment.

    As we understood from the test you have performed, the pause frames don't come out of the destination port but from the external port that is forwarding data. In your test, port 3 is forwarding data and port 5 is receiving data. When flow control is activated, we can see Tx pause frames from port 3.

    This is totally fine for us that pause frames are sent back from external port and not from host port, and we see that port 3 sends back pause frames when trying to forward data to port 5 (external port). In our case, we want the same mechanism to work, but with port 3 connected to the host port. As we understood, if we replace port 5 with the host port, port 3 no longer sends pause frame.

    Additionally, we observed in the past that host port doesn't have drops, which means drops are not seen from the host port itself, and also from the external port trying to forward data.

    Thank you,

    Best regards,

    Wissam

  • +1 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi Wissam,

    Wissam Makhlouf said:
    n our case, we want the same mechanism to work, but with port 3 connected to the host port. As we understood, if we replace port 5 with the host port, port 3 no longer sends pause frame.

    Yes, Host port is an internal Port of CPSW,  will not send pause frames, and blocks Host Port FIFO.
    The expectation concerning Host Port is not correct, The Explanation is provided in the above summary update.

    Wissam Makhlouf said:
    Additionally, we observed in the past that host port doesn't have drops, which means drops are not seen from the host port itself, and also from the external port trying to forward data.

    Yes, these will be dropped internally at UDMA after the Host Port Rx FIFO.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Hello,

    Thank you for your answer, so pause frames cannot be sent from an external port if the internal port is not available. We will discuss it internally.

    Best regards,

    Wissam

  • 0 in reply to Wissam Makhlouf
    TI__Guru 65150 points

    Hi,

    Sure,  Please let us know if you have any Query.

    Best Regards,
    Sudheer