TDA4AL-Q1: DP83TG721 Phy capabilities always get none

Part Number: TDA4AL-Q1

Tool/software:

hi  TI expert,

I following the guide (PDK API Guide) to add a new Ethernet PHY and driver.

However, it seems stuck in ENABLE status due to "caps"

Is there any config or init missing?

We would like to apply FD1000 to our project.

According to David's reply, it seems that the DP83TG721 cannot read 0x0F as its capabilities.

Are there any other modifications needed to make it suitable for the DP83TG721?

e2e.ti.com/.../5606125

  • After bypass check cap at reg(0x0f) & change the data in dp83tg720 driver (dp83tg721_cs1_slave_init), it seems linked.

    However, still cannot ping to the MCU.

    link_loop.log
    Wrong peripheral type, enter again
    Select peripheral type
    0: CPSW_2G
    
    
    Wrong peripheral type, enter again
    Select peripheral type
    0: CPSW_2G
    
    
    Wrong peripheral type, enter again
    Select peripheral type
    0: CPSW_2G
    
    0
    Select MAC port
    0: ENET_MAC_PORT_1 - RGMII
    0
    EnetBoard_setupPorts: 1 of 1 ports configurations found
    CPU Load: 100%
    Starting lwIP, local interface IP is 192.168.1.200
    EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 1 To 0
    EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:4 From 1 To 0
    EnetMcm: CPSW_2G on MCU NAVSS
    Mdio_open: MDIO manual mode enabled
    PHY 0 is alive
    Cpsw_openPortLink: Cpsw_openPortLink
    
    EnetPhy_bindDriver: PHY 0: OUI:080028 Model:29 Ver:00 <-> 'Dp83tg720' : OK
    Host MAC address: 64:1c:10:22:72:35
    [LWIPIF_LWIP] Enet LLD netif initialized successfully
    status_callback==UP, local interface IP is 192.168.1.200
    Enet lwIP App: Added Network IP address I/F ti0: 192.168.1.200
    Initializing apps
    UDP server listening on port 5001
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    EnetPhy_enableState: PHY 0: enable
    Dp83tg720_readStraps: PHY 0: Strap register is 0x51C0
    
    Dp83tg720_readStraps: PHY 0: Strap: RGMII Mode enabled
    
    Dp83tg720_readStraps: PHY 0: Strap: RX Clock Shift enabled
    
    Dp83tg720_config: PHY 0: Slave Mode enabled
    
    Dp83tg720_chipInit: PHY 0:Dp83tg720_chipInit
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_chipInit: PHY 0: Applying configuration for DP83TG721 CS1 Slave
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_setMiiMode: PHY 0: RGMII Mode enabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII TX Clock Shift disabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII RX Clock Shift enabled
    
    Dp83tg720_configIntr: PHY 0: Disable interrupts
    
    Dp83tg720_setLoopbackCfg: PHY 0: disable loopback
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_printRegs: PHY 0: BMCR    = 0x0140
    
    Dp83tg720_printRegs: PHY 0: BMSR    = 0x0141
    
    Dp83tg720_printRegs: PHY 0: PHYIDR1 = 0x2000
    
    Dp83tg720_printRegs: PHY 0: PHYIDR2 = 0xa290
    
    Dp83tg720_printRegs: PHY 0: PHY_GIGESR = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYSTS  = 0x0004
    
    Dp83tg720_printRegs: PHY 0: PHYCR   = 0x000b
    
    Dp83tg720_printRegs: PHY 0: MISR1   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: MISR2   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: RECR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: BISCR   = 0x0100
    
    Dp83tg720_printRegs: PHY 0: MISR3   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: REG19   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: CDCR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYRCR  = 0x0000
    
    Dp83tg720_printRegs: PHY 0: SGMII_CTRL = 0x007b
    
    Dp83tg720_printRegs: PHY 0: RGMII_CTRL = 0x0128
    
    Dp83tg720_printRegs: PHY 0: RGMII_DELAY_CTRL = 0x0002
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_CONTROL = 0x8001
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_EXT_CASP = 0x0002
    
    EnetPhy_enableState: PHY 0: req caps: FD1000
    EnetPhy_enableState: PHY 0: PHY caps: FD1000
    EnetPhy_enableState: PHY 0: MAC caps: FD1000 FD100 HD100 FD10 HD10
    EnetPhy_enableState: PHY 0: refined caps: FD1000
    EnetPhy_enableState: PHY 0: PHY is not NWAY-capable
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    EnetPhy_enableState: PHY 0: enable
    Dp83tg720_readStraps: PHY 0: Strap register is 0x51C0
    
    Dp83tg720_readStraps: PHY 0: Strap: RGMII Mode enabled
    
    Dp83tg720_readStraps: PHY 0: Strap: RX Clock Shift enabled
    
    Dp83tg720_config: PHY 0: Slave Mode enabled
    
    Dp83tg720_chipInit: PHY 0:Dp83tg720_chipInit
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_chipInit: PHY 0: Applying configuration for DP83TG721 CS1 Slave
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_setMiiMode: PHY 0: RGMII Mode enabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII TX Clock Shift disabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII RX Clock Shift enabled
    
    Dp83tg720_configIntr: PHY 0: Disable interrupts
    
    Dp83tg720_setLoopbackCfg: PHY 0: disable loopback
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_printRegs: PHY 0: BMCR    = 0x0140
    
    Dp83tg720_printRegs: PHY 0: BMSR    = 0x0141
    
    Dp83tg720_printRegs: PHY 0: PHYIDR1 = 0x2000
    
    Dp83tg720_printRegs: PHY 0: PHYIDR2 = 0xa290
    
    Dp83tg720_printRegs: PHY 0: PHY_GIGESR = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYSTS  = 0x0004
    
    Dp83tg720_printRegs: PHY 0: PHYCR   = 0x000b
    
    Dp83tg720_printRegs: PHY 0: MISR1   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: MISR2   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: RECR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: BISCR   = 0x0100
    
    Dp83tg720_printRegs: PHY 0: MISR3   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: REG19   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: CDCR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYRCR  = 0x0000
    
    Dp83tg720_printRegs: PHY 0: SGMII_CTRL = 0x007b
    
    Dp83tg720_printRegs: PHY 0: RGMII_CTRL = 0x0128
    
    Dp83tg720_printRegs: PHY 0: RGMII_DELAY_CTRL = 0x0002
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_CONTROL = 0x8001
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_EXT_CASP = 0x0002
    
    EnetPhy_enableState: PHY 0: req caps: FD1000
    EnetPhy_enableState: PHY 0: PHY caps: FD1000
    EnetPhy_enableState: PHY 0: MAC caps: FD1000 FD100 HD100 FD10 HD10
    EnetPhy_enableState: PHY 0: refined caps: FD1000
    EnetPhy_enableState: PHY 0: PHY is not NWAY-capable
    CPU Load: 3%
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    EnetPhy_enableState: PHY 0: enable
    Dp83tg720_readStraps: PHY 0: Strap register is 0x51C0
    
    Dp83tg720_readStraps: PHY 0: Strap: RGMII Mode enabled
    
    Dp83tg720_readStraps: PHY 0: Strap: RX Clock Shift enabled
    
    Dp83tg720_config: PHY 0: Slave Mode enabled
    
    Dp83tg720_chipInit: PHY 0:Dp83tg720_chipInit
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_chipInit: PHY 0: Applying configuration for DP83TG721 CS1 Slave
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_setMiiMode: PHY 0: RGMII Mode enabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII TX Clock Shift disabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII RX Clock Shift enabled
    
    Dp83tg720_configIntr: PHY 0: Disable interrupts
    
    Dp83tg720_setLoopbackCfg: PHY 0: disable loopback
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_printRegs: PHY 0: BMCR    = 0x0140
    
    Dp83tg720_printRegs: PHY 0: BMSR    = 0x0141
    
    Dp83tg720_printRegs: PHY 0: PHYIDR1 = 0x2000
    
    Dp83tg720_printRegs: PHY 0: PHYIDR2 = 0xa290
    
    Dp83tg720_printRegs: PHY 0: PHY_GIGESR = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYSTS  = 0x0004
    
    Dp83tg720_printRegs: PHY 0: PHYCR   = 0x000b
    
    Dp83tg720_printRegs: PHY 0: MISR1   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: MISR2   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: RECR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: BISCR   = 0x0100
    
    Dp83tg720_printRegs: PHY 0: MISR3   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: REG19   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: CDCR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYRCR  = 0x0000
    
    Dp83tg720_printRegs: PHY 0: SGMII_CTRL = 0x007b
    
    Dp83tg720_printRegs: PHY 0: RGMII_CTRL = 0x0128
    
    Dp83tg720_printRegs: PHY 0: RGMII_DELAY_CTRL = 0x0002
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_CONTROL = 0x8001
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_EXT_CASP = 0x0002
    
    EnetPhy_enableState: PHY 0: req caps: FD1000
    EnetPhy_enableState: PHY 0: PHY caps: FD1000
    EnetPhy_enableState: PHY 0: MAC caps: FD1000 FD100 HD100 FD10 HD10
    EnetPhy_enableState: PHY 0: refined caps: FD1000
    EnetPhy_enableState: PHY 0: PHY is not NWAY-capable
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    EnetPhy_enableState: PHY 0: enable
    Dp83tg720_readStraps: PHY 0: Strap register is 0x51C0
    
    Dp83tg720_readStraps: PHY 0: Strap: RGMII Mode enabled
    
    Dp83tg720_readStraps: PHY 0: Strap: RX Clock Shift enabled
    
    Dp83tg720_config: PHY 0: Slave Mode enabled
    
    Dp83tg720_chipInit: PHY 0:Dp83tg720_chipInit
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_chipInit: PHY 0: Applying configuration for DP83TG721 CS1 Slave
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_setMiiMode: PHY 0: RGMII Mode enabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII TX Clock Shift disabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII RX Clock Shift enabled
    
    Dp83tg720_configIntr: PHY 0: Disable interrupts
    
    Dp83tg720_setLoopbackCfg: PHY 0: disable loopback
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_printRegs: PHY 0: BMCR    = 0x0140
    
    Dp83tg720_printRegs: PHY 0: BMSR    = 0x0141
    
    Dp83tg720_printRegs: PHY 0: PHYIDR1 = 0x2000
    
    Dp83tg720_printRegs: PHY 0: PHYIDR2 = 0xa290
    
    Dp83tg720_printRegs: PHY 0: PHY_GIGESR = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYSTS  = 0x0004
    
    Dp83tg720_printRegs: PHY 0: PHYCR   = 0x000b
    
    Dp83tg720_printRegs: PHY 0: MISR1   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: MISR2   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: RECR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: BISCR   = 0x0100
    
    Dp83tg720_printRegs: PHY 0: MISR3   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: REG19   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: CDCR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYRCR  = 0x0000
    
    Dp83tg720_printRegs: PHY 0: SGMII_CTRL = 0x007b
    
    Dp83tg720_printRegs: PHY 0: RGMII_CTRL = 0x0128
    
    Dp83tg720_printRegs: PHY 0: RGMII_DELAY_CTRL = 0x0002
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_CONTROL = 0x8001
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_EXT_CASP = 0x0002
    
    EnetPhy_enableState: PHY 0: req caps: FD1000
    EnetPhy_enableState: PHY 0: PHY caps: FD1000
    EnetPhy_enableState: PHY 0: MAC caps: FD1000 FD100 HD100 FD10 HD10
    EnetPhy_enableState: PHY 0: refined caps: FD1000
    EnetPhy_enableState: PHY 0: PHY is not NWAY-capable
    CPU Load: 3%
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    EnetPhy_enableState: PHY 0: enable
    Dp83tg720_readStraps: PHY 0: Strap register is 0x51C0
    
    Dp83tg720_readStraps: PHY 0: Strap: RGMII Mode enabled
    
    Dp83tg720_readStraps: PHY 0: Strap: RX Clock Shift enabled
    
    Dp83tg720_config: PHY 0: Slave Mode enabled
    
    Dp83tg720_chipInit: PHY 0:Dp83tg720_chipInit
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_chipInit: PHY 0: Applying configuration for DP83TG721 CS1 Slave
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_setMiiMode: PHY 0: RGMII Mode enabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII TX Clock Shift disabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII RX Clock Shift enabled
    
    Dp83tg720_configIntr: PHY 0: Disable interrupts
    
    Dp83tg720_setLoopbackCfg: PHY 0: disable loopback
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_printRegs: PHY 0: BMCR    = 0x0140
    
    Dp83tg720_printRegs: PHY 0: BMSR    = 0x0141
    
    Dp83tg720_printRegs: PHY 0: PHYIDR1 = 0x2000
    
    Dp83tg720_printRegs: PHY 0: PHYIDR2 = 0xa290
    
    Dp83tg720_printRegs: PHY 0: PHY_GIGESR = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYSTS  = 0x0004
    
    Dp83tg720_printRegs: PHY 0: PHYCR   = 0x000b
    
    Dp83tg720_printRegs: PHY 0: MISR1   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: MISR2   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: RECR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: BISCR   = 0x0100
    
    Dp83tg720_printRegs: PHY 0: MISR3   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: REG19   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: CDCR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYRCR  = 0x0000
    
    Dp83tg720_printRegs: PHY 0: SGMII_CTRL = 0x007b
    
    Dp83tg720_printRegs: PHY 0: RGMII_CTRL = 0x0128
    
    Dp83tg720_printRegs: PHY 0: RGMII_DELAY_CTRL = 0x0002
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_CONTROL = 0x8001
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_EXT_CASP = 0x0002
    
    EnetPhy_enableState: PHY 0: req caps: FD1000
    EnetPhy_enableState: PHY 0: PHY caps: FD1000
    EnetPhy_enableState: PHY 0: MAC caps: FD1000 FD100 HD100 FD10 HD10
    EnetPhy_enableState: PHY 0: refined caps: FD1000
    EnetPhy_enableState: PHY 0: PHY is not NWAY-capable
    Linked.log
    Wrong peripheral type, enter again
    Select peripheral type
    0: CPSW_2G
    
    
    Wrong peripheral type, enter again
    Select peripheral type
    0: CPSW_2G
    
    
    Wrong peripheral type, enter again
    Select peripheral type
    0: CPSW_2G
    
    0
    Select MAC port
    0: ENET_MAC_PORT_1 - RGMII
    0
    EnetBoard_setupPorts: 1 of 1 ports configurations found
    CPU Load: 100%
    Starting lwIP, local interface IP is 192.168.1.200
    EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 1 To 0
    EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:4 From 1 To 0
    EnetMcm: CPSW_2G on MCU NAVSS
    Mdio_open: MDIO manual mode enabled
    PHY 0 is alive
    Cpsw_openPortLink: Cpsw_openPortLink
    
    EnetPhy_bindDriver: PHY 0: OUI:080028 Model:29 Ver:00 <-> 'Dp83tg720' : OK
    Host MAC address: 64:1c:10:22:72:35
    [LWIPIF_LWIP] Enet LLD netif initialized successfully
    status_callback==UP, local interface IP is 192.168.1.200
    Enet lwIP App: Added Network IP address I/F ti0: 192.168.1.200
    Initializing apps
    UDP server listening on port 5001
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    EnetPhy_enableState: PHY 0: enable
    Dp83tg720_readStraps: PHY 0: Strap register is 0x51C0
    
    Dp83tg720_readStraps: PHY 0: Strap: RGMII Mode enabled
    
    Dp83tg720_readStraps: PHY 0: Strap: RX Clock Shift enabled
    
    Dp83tg720_config: PHY 0: Slave Mode enabled
    
    Dp83tg720_chipInit: PHY 0:Dp83tg720_chipInit
    Dp83tg720_resetHw: PHY 0: global hard-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_chipInit: PHY 0: Applying configuration for DP83TG721 CS1 Slave
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_setMiiMode: PHY 0: RGMII Mode enabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII TX Clock Shift disabled
    
    Dp83tg720_configClkShift: PHY 0: RGMII RX Clock Shift enabled
    
    Dp83tg720_configIntr: PHY 0: Disable interrupts
    
    Dp83tg720_setLoopbackCfg: PHY 0: disable loopback
    
    Dp83tg720_reset: PHY 0: global soft-reset
    
    Dp83tg720_isResetComplete: PHY 0: global reset is  complete
    
    Dp83tg720_printRegs: PHY 0: BMCR    = 0x0140
    
    Dp83tg720_printRegs: PHY 0: BMSR    = 0x0141
    
    Dp83tg720_printRegs: PHY 0: PHYIDR1 = 0x2000
    
    Dp83tg720_printRegs: PHY 0: PHYIDR2 = 0xa290
    
    Dp83tg720_printRegs: PHY 0: PHY_GIGESR = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYSTS  = 0x0084
    
    Dp83tg720_printRegs: PHY 0: PHYCR   = 0x000b
    
    Dp83tg720_printRegs: PHY 0: MISR1   = 0x4400
    
    Dp83tg720_printRegs: PHY 0: MISR2   = 0x0000
    
    Dp83tg720_printRegs: PHY 0: RECR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: BISCR   = 0x0100
    
    Dp83tg720_printRegs: PHY 0: MISR3   = 0x0800
    
    Dp83tg720_printRegs: PHY 0: REG19   = 0x0400
    
    Dp83tg720_printRegs: PHY 0: CDCR    = 0x0000
    
    Dp83tg720_printRegs: PHY 0: PHYRCR  = 0x0000
    
    Dp83tg720_printRegs: PHY 0: SGMII_CTRL = 0x007b
    
    Dp83tg720_printRegs: PHY 0: RGMII_CTRL = 0x0128
    
    Dp83tg720_printRegs: PHY 0: RGMII_DELAY_CTRL = 0x0002
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_CONTROL = 0x8001
    
    Dp83tg720_printRegs: PHY 0: MMD1_PMA_PMD_EXT_CASP = 0x0002
    
    EnetPhy_enableState: PHY 0: req caps: FD1000
    EnetPhy_enableState: PHY 0: PHY caps: FD1000
    EnetPhy_enableState: PHY 0: MAC caps: FD1000 FD100 HD100 FD10 HD10
    EnetPhy_enableState: PHY 0: refined caps: FD1000
    EnetPhy_enableState: PHY 0: PHY is not NWAY-capable
    Cpsw_handleLinkUp: Port 1: Link up: 1-Gbps Full-Duplex
    MAC Port 1: link up
    link_callback==UP
    CPU Load: 3%

  • Hi,

    It seems you are using a enet example. Can you put the MAC in foced link mode with speed as 1000 and duplexity as full.

    Regards,
    Tanmay

  • Hi Tanmay,

    Yes, we want to use enet RTOS lwip example to bring up DP83TG721 in mcu.

    I already set speed & full duplexity in examples\utils\V3\enet_board_j721s2_evm.c

    code snippet

    static const EnetBoard_PortCfg gEnetCpbBoard_j7xEthPort[] =
    {
        {    /* "MCU_ENET" */
            .enetType  = ENET_CPSW_2G,
            .instId    = 0U,
            .macPort   = ENET_MAC_PORT_1,
            .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
            .phyCfg    =
            {
                .phyAddr         = 0x00U,
                .isStrapped      = BFALSE,
                .skipExtendedCfg = BFALSE,
                .extendedCfg     = &gEnetCpbBoard_dp83tg720PhyCfg,
                .extendedCfgSize = sizeof(gEnetCpbBoard_dp83tg720PhyCfg),
            },
            .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
            .linkCfg   = { ENET_SPEED_1GBIT, ENET_DUPLEX_FULL },
            .flags     = 0U,
        },
    };

  • Another short question,

    Where is MAC side RGMII rx / tx shift mode config in enet example?

  • Hi,

    Can you try with "isStrapped" property of "phyCfg" set to "BTRUE" instead of "BFALSE".

    I will get back to you on the delay config.

    Regards,
    Tanmay

  • Hi Tanmay,

    Follow your suggestion change "isStrapped" to true and seems phy stuck in linkwait status. 

    static const EnetBoard_PortCfg gEnetCpbBoard_j7xEthPort[] =
    {
        {    /* "MCU_ENET" */
            .enetType  = ENET_CPSW_2G,
            .instId    = 0U,
            .macPort   = ENET_MAC_PORT_1,
            .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
            .phyCfg    =
            {
                .phyAddr         = 0x00U,
                .isStrapped      = BTRUE,
                .skipExtendedCfg = BFALSE,
                .extendedCfg     = &gEnetCpbBoard_dp83tg720PhyCfg,
                .extendedCfgSize = sizeof(gEnetCpbBoard_dp83tg720PhyCfg),
            },
            .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
            .linkCfg   = { ENET_SPEED_1GBIT, ENET_DUPLEX_FULL },
            .flags     = 0U,
        },
    };

    0
    Select MAC port
    0: ENET_MAC_PORT_1 - RGMII
    0
    EnetBoard_setupPorts: 1 of 1 ports configurations found
    CPU Load: 100%
    Starting lwIP, local interface IP is 192.168.1.200
    EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 1 To 0
    EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:4 From 1 To 0
    EnetMcm: CPSW_2G on MCU NAVSS
    Mdio_open: MDIO manual mode enabled
    PHY 0 is alive
    Cpsw_openPortLink: Cpsw_openPortLink
    
    EnetPhy_bindDriver: PHY 0: OUI:080028 Model:29 Ver:00 <-> 'Dp83tg720' : OK
    Host MAC address: 64:1c:10:22:72:35
    [LWIPIF_LWIP] Enet LLD netif initialized successfully
    status_callback==UP, local interface IP is 192.168.1.200
    Enet lwIP App: Added Network IP address I/F ti0: 192.168.1.200
    Initializing apps
    UDP server listening on port 5001
    

  • Hi Tanmay,

    We solve this problem with setting MAC/phy RX/TX shift mode config.