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Original question:

AM62A7: Confirming HSM Communication Setup and Firmware Loading

AM62A7: Question Regarding HSM Secure Proxy

Cesc Yang
Prodigy 231 points
Part Number: AM62A7
Other Parts Discussed in Thread: AM62P

Tool/software:

Hi TI,

I have a 2 questions related to the Secure Proxy configuration and HSM on the AM62A platform:

  1. In the Secure Proxy thread allocation table for SA3_SS0_SEC_PROXY_0, the thread IDs for TIFS_HSM and HSM are listed, but I could not find thread IDs for DM core, MCU core, or A core when communicating with the HSM core.

    At the same time, the hsm_ipc demo defines RX_THREAD_ID as 9 and TX_THREAD_ID as 8.

    Accessing sproxy registers with these macro definition results in hard abort. Are these IDs part of another mapping table that is not documented here? If so, could you clarify where I can find this allocation?

  2. In the table, TIFS_HSM is listed as a Host for both sec_low_priority_rx and sec_HSM_response_tx threads. Why are two TIFS_HSM cores acting as Hosts together? 

Best regards,
Yang

  • +1
    TI__Guru 70371 points

    Hello,

    1. Those allocations are defined by the TIFS for the commnunication between the TIFS & other cores. For HSM to other cores communication, the HSM code itself defines the thread ids mapping.

    For AM62A, the mappings are defined in the file: hsm/src/drivers/sec_proxy/config/am62ax/sec_proxy_config_data.c

    For communication with WKUP R5F core, you would find the following mapping:

    • HSM -> WKUP R5F : TX ID 2 -> RX ID 9
    • WKUP R5F -> HSM : TX ID 8 -> RX ID 0

    That's how the {RX|TX}_THREAD_ID are defined in the HSM IPC example.

    2. The TIFS_HSM is just a virtual host id for a single TIFS core.

    Regards,

    Prashant

  • 0 in reply to Prashant Shivhare
    Prodigy 231 points

    Hello Prashant,

    Thanks yo you support we've resolved the issue regarding the ipc between DM R5 and HSM. We're now trying to integrate the MCU R5 core into the HSM IPC communication and need some guidance.

    1.How do I configure the MCU R5 core for HSM IPC? Should I manually add new configurations, or are there predefined settings I should follow?

    2.When other cores send messages to the HSM, do they all use the same thread ID for HSM reception, or does each core require a unique configuration?

    Thanks for your help.

    Best regards, 

    Yang

  • 0 in reply to Cesc Yang
    TI__Mastermind 20745 points

    Yang,

    Before I can answer this could you please provide the operating system you are running on MCU R5:

    1) Free RTOS

    OR

    2) AutoSAR

    Thanks

    Yogesh

  • 0 in reply to Yogesh Siraswar
    Prodigy 231 points

    Hi Yogesh,

    During development we are running on freertos from mcu plus sdk, but the client will be integrating the content into their environment, which runs on AUTOSAR OS .

    Best Regards,

    Yang

  • 0 in reply to Yogesh Siraswar
    Prodigy 231 points

    Hi Yogesh,

    This matter is quite urgent for us. Would really appreciate any updates for us regarding this issue.

    Thanks,

    Yang

  • 0 in reply to Cesc Yang
    TI__Mastermind 20745 points

    Sorry for delay.

    I didn't get time to test, but you may refer to AM62P mapping in HSM care package:

    • HSM -> MCU R5F : TX ID 2 -> RX ID 13
    • MCU R5F -> HSM : TX ID 12 -> RX ID 0

    Let me know if you run into any issues.

    Thanks

    Yogesh

  • 0 in reply to Yogesh Siraswar
    Prodigy 231 points

    Yogesh,

    I've tried this method but the phenomenon is exactly the same with AM62A7: HSM Care Package - Unable to Run hsm_ipc Example on AM62Ax - Processors forum - Processors - TI E2E support forums.
    I've migrated the project files from r5fss0-0_freertos folder to mcu-r5fss0-0_freertos, with the secure proxy Id changed according to your reply.

    In this case where a message is sent, the thread_id is modified as 12. During debug I can see the code would run here. 

    After this line the code got here:

    Afterthis line, it jumped to the HwiP_data_abort_handler() function located in Hwip_armv7r_handlers_freertos.c.

    The device is in HS-FS state.

    Can you please help clarify the cause of this?

    Regards,
    Yang

  • 0 in reply to Cesc Yang
    TI__Guru 70371 points
    Cesc Yang said:
    Can you please help clarify the cause of this?

    Have you integrated the ids in the HSM package as well?

    Prashant Shivhare said:
    For AM62A, the mappings are defined in the file: hsm/src/drivers/sec_proxy/config/am62ax/sec_proxy_config_data.c

    This only configures the threads for WKUP_R5F and A53 core. You would need to manually configure the threads for MCU R5F core.

  • +1 in reply to Prashant Shivhare
    TI__Guru 70371 points

    Please refer to the following difference between the AM62A and AM62P config data where the later has the threads configured for MCU R5F:

    --- ./hsm-care-package/hsm/src/drivers/sec_proxy/config/am62ax/sec_proxy_config_data.c	2024-02-13 15:47:08.000000000 +0530
+++ ./hsm-care-package/hsm/src/drivers/sec_proxy/config/am62px/sec_proxy_config_data.c	2024-02-22 16:50:06.000000000 +0530
@@ -1,11 +1,11 @@
 /*
  * System Firmware Source File
  *
- * SoC configs for secure proxy for AM62AX device
+ * SoC configs for secure proxy for AM62PX device
  *
- * Data version: 221107_151433
+ * Data version: 231011_130515
  *
- * Copyright (C) 2021-2023 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
  * ALL RIGHTS RESERVED
  */
 
@@ -31,73 +31,99 @@
 
 
 const struct secure_proxy_tx_thread_config soc_secure_proxy_tx_configurations[SOC_MAX_SPT_TX_CONFIG_INSTANCES] = {
-	[AM62AX_MCU_SA3_SS0_SEC_PROXY_0_TX_HSM_LOW_PRIORITY_THR002_CONF028] =			{
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_TX_HSM_LOW_PRIORITY_THR002_CONF026] =			{
 		.host_id		= HOST_ID_HSM,
 		.thread_id		= 2U,
 		.num_credits		= 8U,
 		.threshold		= 1U,
 		.evt_threshold		= SOC_SAFE_EVENT,
 		.evt_error		= SOC_SAFE_EVENT,
-		.rx_thread_instance_id	= AM62AX_MCU_SA3_SS0_SEC_PROXY_0_RX_MCU_0_R5_0_HSM_SEC_LOW_PRIORITY_RX_THR013_CONF019,
+		.rx_thread_instance_id	= AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_MAIN_0_R5_0_HSM_SEC_LOW_PRIORITY_RX_THR013_CONF018,
 	},
-	[AM62AX_MCU_SA3_SS0_SEC_PROXY_0_TX_MCU_0_R5_HSM_SEC_HSM_RESPONSE_TX_THR012_CONF029] =	{
-		.host_id		= HOST_ID_MAIN_0_R5_0,
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_TX_MAIN_0_R5_HSM_SEC_HSM_RESPONSE_TX_THR012_CONF027] =	{
+		.host_id		= HOST_ID_WKUP_0_R5_0,
 		.thread_id		= 8U,
 		.num_credits		= 8U,
 		.threshold		= 1U,
 		.evt_threshold		= SOC_SAFE_EVENT,
 		.evt_error		= SOC_SAFE_EVENT,
-		.rx_thread_instance_id	= AM62AX_MCU_SA3_SS0_SEC_PROXY_0_RX_HSM_RESPONSE_THR000_CONF018,
+		.rx_thread_instance_id	= AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_HSM_RESPONSE_THR000_CONF017,
 	},
-	[AM62AX_MCU_SA3_SS0_SEC_PROXY_0_TX_MPU_0_A72_HSM_SEC_HSM_RESPONSE_TX_THR010_CONF030] =	{
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_TX_MPU_0_A72_HSM_SEC_HSM_RESPONSE_TX_THR010_CONF028] =	{
 		.host_id		= HOST_ID_A53_0,
 		.thread_id		= 10U,
 		.num_credits		= 8U,
 		.threshold		= 1U,
 		.evt_threshold		= SOC_SAFE_EVENT,
 		.evt_error		= SOC_SAFE_EVENT,
-		.rx_thread_instance_id	= AM62AX_MCU_SA3_SS0_SEC_PROXY_0_RX_HSM_RESPONSE_THR000_CONF018,
+		.rx_thread_instance_id	= AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_HSM_RESPONSE_THR000_CONF017,
 	},
-	[AM62AX_MCU_SA3_SS0_SEC_PROXY_0_TX_HSM_LOW_PRIORITY_THR003_CONF031] =			{
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_TX_HSM_LOW_PRIORITY_THR003_CONF029] =			{
 		.host_id		= HOST_ID_HSM,
 		.thread_id		= 3U,
 		.num_credits		= 8U,
 		.threshold		= 1U,
 		.evt_threshold		= SOC_SAFE_EVENT,
 		.evt_error		= SOC_SAFE_EVENT,
-		.rx_thread_instance_id	= AM62AX_MCU_SA3_SS0_SEC_PROXY_0_RX_MCU_0_A72_0_HSM_SEC_LOW_PRIORITY_RX_THR011_CONF020,
+		.rx_thread_instance_id	= AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_MCU_0_A72_0_HSM_SEC_LOW_PRIORITY_RX_THR011_CONF019,
+	},
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_TX_HSM_LOW_PRIORITY_THR002_CONF030] =			{
+		.host_id		= HOST_ID_HSM,
+		.thread_id		= 4U,
+		.num_credits		= 8U,
+		.threshold		= 1U,
+		.evt_threshold		= SOC_SAFE_EVENT,
+		.evt_error		= SOC_SAFE_EVENT,
+		.rx_thread_instance_id	= AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_MCU_0_R5_0_HSM_SEC_LOW_PRIORITY_RX_THR013_CONF018,
+	},
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_TX_MCU_0_R5_HSM_SEC_HSM_RESPONSE_TX_THR012_CONF031] =	{
+		.host_id		= HOST_ID_MCU_0_R5_0,
+		.thread_id		= 12U,
+		.num_credits		= 8U,
+		.threshold		= 1U,
+		.evt_threshold		= SOC_SAFE_EVENT,
+		.evt_error		= SOC_SAFE_EVENT,
+		.rx_thread_instance_id	= AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_HSM_RESPONSE_THR000_CONF017,
 	},
 };
 
 const u16 soc_secure_proxy_rx_configurations_num = SOC_MAX_SPT_RX_CONFIG_INSTANCES;
 
 const struct secure_proxy_rx_thread_config soc_secure_proxy_rx_configurations[SOC_MAX_SPT_RX_CONFIG_INSTANCES] = {
-	[AM62AX_MCU_SA3_SS0_SEC_PROXY_0_RX_HSM_RESPONSE_THR000_CONF018] =					  {
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_HSM_RESPONSE_THR000_CONF017] =					  {
 		.host_id			= HOST_ID_HSM,
 		.thread_id			= 0U,
 		.threshold			= 1U,
 		.evt_threshold			= 0x0002,
 		.evt_error			= 0x0000,
-		.secure_proxy_instance_id	= AM62AX_SPROXY_IDX_SA3_SS0_SEC_PROXY_0,
-		.ring_config_instance_id	= AM62AX_MCU_SA3_SS0_RINGACC_0_RING_0005_CONF_018,
+		.secure_proxy_instance_id	= AM62PX_SPROXY_IDX_SA3_SS0_SEC_PROXY_0,
+		.ring_config_instance_id	= AM62PX_SA3_SS0_RINGACC_0_RING_0005_CONF_017,
 	},
-	[AM62AX_MCU_SA3_SS0_SEC_PROXY_0_RX_MCU_0_R5_0_HSM_SEC_LOW_PRIORITY_RX_THR013_CONF019] =			  {
-		.host_id			= HOST_ID_MAIN_0_R5_0,
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_MAIN_0_R5_0_HSM_SEC_LOW_PRIORITY_RX_THR013_CONF018] =			  {
+		.host_id			= HOST_ID_WKUP_0_R5_0,
 		.thread_id			= 9U,
 		.threshold			= 1U,
 		.evt_threshold			= SOC_SAFE_EVENT,
 		.evt_error			= SOC_SAFE_EVENT,
-		.secure_proxy_instance_id	= AM62AX_SPROXY_IDX_SA3_SS0_SEC_PROXY_0,
-		.ring_config_instance_id	= AM62AX_MCU_SA3_SS0_RINGACC_0_RING_0004_CONF_019,
+		.secure_proxy_instance_id	= AM62PX_SPROXY_IDX_SA3_SS0_SEC_PROXY_0,
+		.ring_config_instance_id	= AM62PX_SA3_SS0_RINGACC_0_RING_0004_CONF_018,
 	},
-	[AM62AX_MCU_SA3_SS0_SEC_PROXY_0_RX_MCU_0_A72_0_HSM_SEC_LOW_PRIORITY_RX_THR011_CONF020] =		  {
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_MCU_0_A72_0_HSM_SEC_LOW_PRIORITY_RX_THR011_CONF019] =		  {
 		.host_id			= HOST_ID_A53_0,
 		.thread_id			= 11U,
 		.threshold			= 1U,
 		.evt_threshold			= SOC_SAFE_EVENT,
 		.evt_error			= SOC_SAFE_EVENT,
-		.secure_proxy_instance_id	= AM62AX_SPROXY_IDX_SA3_SS0_SEC_PROXY_0,
-		.ring_config_instance_id	= AM62AX_MCU_SA3_SS0_RINGACC_0_RING_0003_CONF_020,
+		.secure_proxy_instance_id	= AM62PX_SPROXY_IDX_SA3_SS0_SEC_PROXY_0,
+		.ring_config_instance_id	= AM62PX_SA3_SS0_RINGACC_0_RING_0004_CONF_019,
+	},
+	[AM62PX_MCU_SA3_SS0_SEC_PROXY_0_RX_MCU_0_R5_0_HSM_SEC_LOW_PRIORITY_RX_THR013_CONF018] =			  {
+		.host_id			= HOST_ID_MCU_0_R5_0,
+		.thread_id			= 13U,
+		.threshold			= 1U,
+		.evt_threshold			= SOC_SAFE_EVENT,
+		.evt_error			= SOC_SAFE_EVENT,
+		.secure_proxy_instance_id	= AM62PX_SPROXY_IDX_SA3_SS0_SEC_PROXY_0,
+		.ring_config_instance_id	= AM62PX_SA3_SS0_RINGACC_0_RING_0004_CONF_020,
 	},
 };
-