Tool/software:
Hello engineers from TI:
We designed a development evaluation board with a hardware architecture of DSP (C6657)+FPGA. The DSP and FPGA communicate through SRIO, but we encountered issues while testing the DSP's ability to read and write FPGA memory.
Test content:
DSP writes 4-byte content to the shared memory of FPGA through SRIO.
DSP source address: 0x0c051000
FPGA target address: 0x00020000
size:4 byte
srio param
SRIO_LSU_TRANSFER tparams;
tparams.rapidIOLSB =0x00020000
tparams.dspAddress = 0x0c051000;
tparams.bytecount = 4;
tparams.ttype = Srio_Ttype_Write_NWRITE;
tparams.ftype = Srio_Ftype_WRITE;
tparams.dstID = 0xFF;
tparams.outPortID = 0;
tparams.idSize = 0;
Question:
The data we captured through FPGA debugging tools shows that the target address received by FPGA has changed to 0x0000020004, and the data has also been written to this incorrect address (0x00020004)
figure 1 LSU REG VALUE
figure 2 dsp source memory
figure 3 FPGA scope data
According to the data manual I have learned about SRIO, the registers I configured for SRIO are correct, but I am unable to solve the problem of writing data to the target address 0x00020000 but actually writing it to 0x00020004. I don't know if Ti's engineer can help me analyze the cause of this problem.
Thank you very much.
