Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
HI,
on our Design with AM6421 we used the CLKOUT0 Ball U13 for 50MHz PHY CLK for CPSW RMII1 Interface,
but we have no CLK on the Output Ball U13.
If I configure the sysboot Pins for Ethernet RMII Boot, then 25MHz comes out of CLK0 U13.
We need a configuration for 50HMz CLKOUT independ of boot mode.
We have tried Register setting as follow:
PLL0_CTRL_REG 0x680020
BIT 31 BYPASS
BIT 15 // PLL_EN
BIT 8) // INTL_BYP_EN
BIT 4) // CLK_POSTDIV_EN
PLL0_FREQ_CTRL0 0x680030
Walue 80 // FB_DIV_INT
PLL0_HSDIV_CTRL4 0x680090 // 5.4.6.2.18 PLL0_HSDIV_CTRL4 Register
BIT 15) // CLKOUT_EN
BIT 6-0 // HSDIV = 7
CTRLMMR_CLKOUT_CTRL 0x43008010 // CLKOUT_CTRL Register Address 0x43008010
BIT 0 = 0 // RGMII_MHZ_50_CLK (50 MHz)
BIT 4 = 1 // enables CLKOUT output
Is there some Register setting missing to have the desired 50MHz CLKOUT0?
Many thanks in advance.
with kind regards
Thomas
