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TDA4VP-Q1: eMMC SI timing spec clarifications

Part Number: TDA4VP-Q1
Other Parts Discussed in Thread: TDA4VH-Q1, , TDA4AH-Q1, TDA4AP-Q1

Tool/software:

Hi all,

Looking at your datasheet "TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 SPRSP79B – FEBRUARY 2023 – REVISED DECEMBER 2023", with respect to 200MHz HS400:

  1. Table 6-57:

    1. Can I set the output delay (manually tune) with the mentioned registers? Or those values should be written and relate to the min/max values in the next tables?
      If manual delay is optional –
      1. what is the time resolution?
      2. Can you refer me to an elaborated guide regarding those registers settings
    2. Strobe delay is input, right? Is it delay relative to input data? If so, what is input delay?
  2. Table 6-58:

    1. Is there an SR input limitation for HS400/HS200?
    2. Is there a "valid window size" for HS400/200?
    3. What is the reason behind 8ps trace mismatch limitation? It's a lot tighter than other vendors we work with (50ps with another vendor)
  3. Table 6-84:


    1. As far as I know, HS400 is DDR. That doesn't agree with the timing diagram seen here or the numbers.
    2. Looking at HS4008, which is indeed SDR, like HS200 according to spec -
      How can max delay be 3.28ns? UI is 2.5ns (nominal), and device samples at falling edge of clk, leaving negative (2.5-3.25ns) setup time
  4. Regarding Max/Min voltages for over/under shoots (transients) –
    1. Where can I find max/min allowed voltages for the input CMD/Data/Strobe? Is it under table 6.1?
      If so, is it this section:

      Or this one:

      Is the 2.2V relative to PVT corner (i.e. 400mV above VDD) or is it 2.2V absolute, such that in PVT max I'll have 2.2-1.98=0.202V margin??

 

 

Looking to hear from you,

 

  • Yoel
  • Hi Yoel,

    Table 6-57:

    1. Can I set the output delay (manually tune) with the mentioned registers? Or those values should be written and relate to the min/max values in the next tables?

    These are the recommended tuned values for output delay. You can manually tune by changing the value of the OTAPDLYSEL value.

    • Table 6-58:

      1. Is there an SR input limitation for HS400/HS200?
      2. Is there a "valid window size" for HS400/200?
      3. What is the reason behind 8ps trace mismatch limitation? It's a lot tighter than other vendors we work with (50ps with another vendor)

    1. There is no SR input limitation for HS200 and HS400 specified, but we are going to publish input timing requirements in the next revision of the datasheet as specified:

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    HS4000 tDSMPW Pulse width, MMC0_DS 1.95   ns
    HS4001 tRQ_DAT Input skew, MMC0_DS to MMC0_DAT valid   475 ps
    HS4002 tRQH_DAT Input skew hold, MMC0_DAT invalid to MMC0_DS   475 ps
    HS4003 tRQ_CMD Input skew, MMC0_DS to MMC0_CMD valid   475 ps
    HS4004 tRQH_CMD Input skew hold, MMC0_CMD invalid to MMC0_DS   475 ps

    2. We don't publish a valid window size number, but you can find the valid window based on setup and hold time parameters in the table below.

    3. This is a limitation based on board setup and design.

    Table 6-84:


    1. As far as I know, HS400 is DDR. That doesn't agree with the timing diagram seen here or the numbers.
    2. Looking at HS4008, which is indeed SDR, like HS200 according to spec -
      How can max delay be 3.28ns? UI is 2.5ns (nominal), and device samples at falling edge of clk, leaving negative (2.5-3.25ns) setup time

    These numbers are outdated from the latest update we have made but have not yet been pushed to the datasheet. Here are the latest numbers:

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
      fop(clk) Operating frequency, MMC0_CLK   200 MHz
    HS4005 t(clk) Operating period, MMC0_CLK 5 ns
    HS4006 tw(clkH) Pulse duration, MMC0_CLK high 2.23   ns
    HS4007 tw(clkL) Pulse duration, MMC0_CLK low 2.23   ns
    HS4008 tosu(cmdV-clkH) Output setup time, MMC0_CMD valid to MMC0_CLK rising clock edge 2.54   ns
    HS4009 tosu(dV-clk) Output setup time, MMC0_DAT[7:0] valid to MMC0_CLK rising or falling edge 0.63   ns
    HS4010 toh(clkH-cmdIV) Output hold time, MMC0_CLK rising clock edge to MMC0_CMD invalid 0.98   ns
    HS4011 toh(clk-dIV) Output hold time, MMC0_CLK rising or falling edge to MMC0_DAT[7:0] invalid 0.72   ns

    We also have an updated timing diagram as well that will be pushed to the next revision of the datasheet.

    Regarding question 4, I will have to check with another expert and get back to you.

    Best Regards,

    Matt

  • Section 6.6.4 eMMCPHY Electrical Characteristics contains the electrical parameters for MMC0 IO, including min/max values for inputs/outputs.  Note the comment regarding min/max values for VDDS_MMC0, the -0.3V to 2.2V are absolute max (guaranteed to not damage the device) .  The recommended operating range is 1.71V to 1.89V (from Section 6.4 Recommended Operating Conditions)

  • Hi Robert and thanks for replying. 
    Some follow up questions:

    1. Q1 - 

    These are the recommended tuned values for output delay. You can manually tune by changing the value of the OTAPDLYSEL value.

    1.a.  Can you send a LUT with OTAPDLSEL register value and delay?

    1.b. For the "recommended tuned values for output delay" - Are those the values to comply with the new timing table you sent (HS4008,HS4009,HS4010 & HS4011)?

    2. Can you please share the timing diagrams relevant for these numbers HS4000-HS4010?

    There is no SR input limitation for HS200 and HS400 specified, but we are going to publish input timing requirements in the next revision of the datasheet as specified:
    We also have an updated timing diagram as well that will be pushed to the next revision of the datasheet.

     - Yoel

  • Thanks,
    I might need to clarify. Question is not related to DC voltage from power supply, but to data/cmd/strb inputs, where overshoot or undershoot might occur in "read" mode (transients).

    For table 6.6.4 I was expecting to see VIL min (undershoot) and VIH max (overshoot).
    Or is it in another table? I wish to confirm it's in table 6.1:

    Transient Overshoot and Undershoot specification at IO pin

    and figure 6.1:

    if that is the case - is comment A (Tos+Tus<20%) true? or is it 20% per each?

  • Regarding overshoot/undershoot question - yes Figure 6-1 defines the specification for IO.  The combination of Tos + Tus < 20% of period (not each)

  • Hi Yoel,

    1.a.  Can you send a LUT with OTAPDLSEL register value and delay?

    Please see the latest revision of the TRM registers labeled: J784S4_Registers_Public_20250116. In this sheet, go to the MMCSD0 tab and search for OTAPDLYSEL.

    1.b. For the "recommended tuned values for output delay" - Are those the values to comply with the new timing table you sent (HS4008,HS4009,HS4010 & HS4011)?

    These values are chosen based on tuning characterization to ensure the most safe value in the passing range.

    2. Can you please share the timing diagrams relevant for these numbers HS4000-HS4010?

    May still be subject to change, because it is not pushed to the datasheet officially, but here is what the most up to date diagram looks like.

    Best Regards,

    Matt

  • There is no SR input limitation for HS200 and HS400 specified, but we are going to publish input timing requirements in the next revision of the datasheet as specified:

    Hi Mark,
    Could you also attach these timing diagram?

  • Hi Yoel, 

    A timing diagram for this table is not currently available, but please follow the table below:

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    HS4000 tDSMPW Pulse width, MMC0_DS 1.95   ns
    HS4001 tRQ_DAT Input skew, MMC0_DS to MMC0_DAT valid   475 ps
    HS4002 tRQH_DAT Input skew hold, MMC0_DAT invalid to MMC0_DS   475 ps
    HS4003 tRQ_CMD Input skew, MMC0_DS to MMC0_CMD valid   475 ps
    HS4004 tRQH_CMD Input skew hold, MMC0_CMD invalid to MMC0_DS   475 ps

    Best Regards,

    Matt

  • Regarding the OS - I understand the calculation. 
    Can you explain what is allowed U.S? 

  • The overshoot/undershoot drawing includes both waveforms (OS and US).  Can you please clarify what additional info you are requesting for US?

  • Yes, it does. but it states "...nominal IO supply...".
    So I wonder - 
    1. Does the nominal IO supply refer to PVT supply voltage (min,typ,max)=(1.62,1.8,1.98V)? or always 1.8V?
    2. Is it in addition to DC OS/US allowed (+-0.3V)? 

  • Normal IO supply is the IO voltage you are providing.  So if you are providing 1.70V to the IO power supply, that is your normal IO voltage.

    The +0.3V is a maximum part can sustain without possible getting damaged/shorten lifetime of part.  This is not in addition to the OS/US.

  • Thanks a lot.
    Regarding undershoot - can you explain how undershoot limit is affected by IO voltage supply?
    Regarding he 300mV margin - I understand it's a DC spec, right?
    In that case, I can have 300mV above Vsupply across all UI. right? Can you explain the timing limit (OS+US<20%)? should it be above the 300mV or at Vsupply?
    in the pic below -
    blue line is below the 300mV limit, is it legit input?
    pink line crosses the 300mV and 20% transient limit, so should I calculate time at the red arrow or green arrow?

  • Undershoot is not affected by IO voltage supply.

    The +/-300mV is not the recommended spec - it is the maximum spec. The timing limit (OS+US<20%) is at Vsupply, not in addition to the +/- 300mV value.