TDA4AL-Q1: Activate cache coherency across MAIN domain on A72 (cont.)

Marco K

Prodigy 130 points

Part Number: TDA4AL-Q1

Tool/software:

Hello Support-Team,

I am sorry, but missed the window to reply to the original thread, so I will try to continue here.

From Nihil Dasan:

Hi Marco,

No, if the memory map is unchanged, then there need not be any changes in this file
Then let us focus on this error

[C7x_2 ] 15.527368 s: VX_ZONE_ERROR:[ownTargetCmdDescHandler:1115] object descriptor type is invalid

Is this the first error that you are seeing or are there any others present above this?
Can you share the full logs?

Yes, this is the first error that is encountered, but it does not do so deterministically.
Usually the test run just stops after

[ RUN 0001 ] tivxTestKernelsNotNot.Sizes/0/640x480 ...

Only from time to time I get the error message.

I will attach the full logs.

Thanks and kind regards,
Marco

7 months ago

0 Marco K 7 months ago

Prodigy 130 points

Starting kernel ...

Booting in EL1, bootloader started us in EL2 at 0x00000000800c0000
MMU: 44 bits PA, 1592 MB of RAM
GIC: V3, 992 IRQs, 8 CPUs
GIC: detected 8 redistributors
PSCI: version 1.1, 2 cores
PSCI: Cluster 0 - 2 cores

******************************************************************
*** THIS IS DEBUG PSP VERSION, NOT INTENDED FOR PRODUCTION USE ***
******************************************************************

PikeOS (C) Copyright SYSGO GmbH, Germany
ROM image build: devel-mko@mko-lap-310125-14:09
Kernel build: 5.1-20592, type: noassert tracesys smp standard [gcc]
ASP: "arm_v8hf" ARM v8, endian: little
PSP build: 5.1-testversion-ASSERT
PSP: "cortex-a5x-ti-tda4 (libPSP build: 5.1-21904-ASSERT)" PSP 22047: Texas Instruments TDA4
Features: RETAIL TRACER-SYSCALL OPT SMP(2/64) TF(0)
Configuration limits:
respart:    255
task:       255
thread:     4095
timepart:   255
priority:   256
kprio:      32
interrupts: 1024/1024
TP windows: 256
thr sstack: 8192 B
PI nesting: 4
PikeOS TI SCI KDEV 'ti_sci_prov', Build: 5.1-88
PikeOS TI PM KDEV 'ti_pm', Build: 5.1-66
PikeOS TI INT CONF KDEV 'ti_int_conf_prov', Build: 5.1-90
PikeOS Mutex KDEV 'mutex', Build: 5.1-54
PikeOS TI IPC KDEV 'ti-ipc', Build: 5.1-112
PikeOS TI Mailbox KDEV 'ti-mbox', Build: 5.1-99
PikeOS TI UDMA KDEV 'ti-udma', Build: 5.1-125
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
Resource partition 0 kernel memory refill strategy: dynamic (on demand)
Time stamp counter clock: 200000 kHz, user accessible
System ticker: dynamic mode, resolution 10000 ns
Time partition switch: 10000000 ns, watchdog timeout: 10000000 ns
Time partition synchronization: default
PSP startmode: 0
PSP haltmode: 0
Free memory: 1560152 KiB
PSSW +Ext. FPs +VirtSplit +Messages (Production), Build: 5.1-4562
PIKEOS_MON: Started, version: 5.1-106
Trace Server: version: 5.1-300
<DRV INFO> eth0: Registered MAC address(02:70:34:77:e4:0a) for channel '0'
<DRV INFO> eth0: Registered MAC address(06:70:34:77:e4:0a) for channel '1'
<DRV INFO> eth0: Registered MAC address(0a:70:34:77:e4:0a) for channel '2'
<DRV INFO> eth0: Registered MAC address(0e:70:34:77:e4:0a) for channel '3'
<DRV INFO> eth0: [ALE] IP Address at table entry 0 is <192.168.1.15>
<DRV INFO> eth0: [ALE] Ether-Type at table entry 1 is 0x0800
<DRV INFO> eth0: [ALE] Policer 0 <filt_mac?=0, filt_ip?=1,filt_etype?=1>
<DRV INFO> eth0: [ALE] Policer Thread <val_on_match=1, val_default=0, flow_on_match=83>
am65_cpsw_nuss: Provider "eth0" started, Build: 5.1-46 Production
MUXA: Version: 5.1-551
APP: Init ... !!!
MEM: Init ... !!!
MEM: Init ... Done !!!
     0.000000 s: IPC: Init ... !!!
     0.000000 s: IPC: 5 CPUs participating in IPC !!!
RPMessage_announce : remote -1, endpt 13, name rpmsg_chrdev
RPMessage_announce..... ProcId 3
RPMessage_announce..... ProcId 4
RPMessage_announce..... ProcId 7
RPMessage_announce..... ProcId 8
     0.000000 s: IPC: Init ... Done !!!
    15.458798 s: GTC Frequency = 200 MHz
    15.462942 s: REMOTE_SERVICE: Init ... !!!
    15.467133 s: REMOTE_SERVICE: Init ... Done !!!
APP: Init ... Done !!!
    15.474061 s: VX_ZONE_INIT:Enabled
    15.476832 s: VX_ZONE_ERROR:Enabled
    15.480993 s: VX_ZONE_WARNING:Enabled
[MCU2_0]     10.055891 s: CIO: Init ... Done !!!
[MCU2_0]     10.055941 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]     10.055966 s: CPU is running FreeRTOS
[MCU2_0]     10.055983 s: APP: Init ... !!!
[MCU2_0]     10.056013 s: SCICLIENT: Init ... !!!
[MCU2_0]     10.056130 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
[MCU2_0]     10.056158 s: SCICLIENT: DMSC FW revision 0x9
[MCU2_0]     10.056178 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]     10.056198 s: SCICLIENT: Init ... Done !!!
[MCU2_0]     10.056216 s: UDMA: Init ... !!!
[MCU2_0]     10.057013 s: UDMA: Init ... Done !!!
[MCU2_0]     10.057043 s: UDMA: Init for CSITX/CSIRX ... !!!
[MCU2_0]     10.057440 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0]     10.057469 s: MEM: Init ... !!!
[MCU2_0]     10.057492 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ b9000000 of size 16777216 bytes !!!
[MCU2_0]     10.057534 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 524288 bytes !!!
[MCU2_0]     10.057569 s: MEM: Init ... Done !!!
[MCU2_0]     10.057585 s: IPC: Init ... !!!
[MCU2_0]     10.057612 s: IPC: 5 CPUs participating in IPC !!!
[MCU2_0]     10.057640 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     15.198169 s: IPC: HLOS is ready !!!
[MCU2_0]     15.201583 s: IPC: Init ... Done !!!
[MCU2_0]     15.201619 s: APP: Syncing with 4 CPUs ... !!!
[MCU2_0]     15.201808 s: APP: Syncing with 4 CPUs ... Done !!!
[MCU2_0]     15.201833 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     15.202277 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     15.202310 s: FVID2: Init ... !!!
[MCU2_0]     15.202344 s: FVID2: Init ... Done !!!
[MCU2_0]     15.202364 s: SCICLIENT: Sciclient_pmSetModuleState module=219 state=2
[MCU2_0]     15.202483 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.202517 s: DSS: Init ... !!!
[MCU2_0]     15.202534 s: DSS: Display type is eDP !!!
[MCU2_0]     15.202552 s: DSS: M2M Path is enabled !!!
[MCU2_0]     15.202569 s: DSS: SoC init ... !!!
[MCU2_0]     15.202584 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0
[MCU2_0]     15.202634 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.202657 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2
[MCU2_0]     15.202828 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.202850 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2
[MCU2_0]     15.202977 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.202998 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2
[MCU2_0]     15.203170 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.203195 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2
[MCU2_0]     15.203325 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.203345 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0
[MCU2_0]     15.203508 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.203528 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=158 clk=3 freq=148500000
[MCU2_0]     15.203705 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     15.203725 s: SCICLIENT: Sciclient_pmModuleClkRequest module=158 clk=3 state=2 flag=2
[MCU2_0]     15.203877 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]     15.203898 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=2
[MCU2_0]     15.204030 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.204049 s: DSS: SoC init ... Done !!!
[MCU2_0]     15.204066 s: DSS: Board init ... !!!
[MCU2_0]     15.204081 s: DSS: Turning on DP_PWR pin for eDP adapters ... !!!
[MCU2_0]     15.749753 s: DSS: Turning on DP_PWR pin for eDP adapters ... Done!!!
[MCU2_0]     15.749787 s: DSS: Board init ... Done !!!
[MCU2_0]     15.772762 s: DSS: Display is not connected
[MCU2_0]     15.772803 s: DSS: Init ... Done !!!
[MCU2_0]     15.772822 s: VHWA: VPAC Init ... !!!
[MCU2_0]     15.772839 s: SCICLIENT: Sciclient_pmSetModuleState module=361 state=2
[MCU2_0]     15.772942 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.772966 s: VHWA: LDC Init ... !!!
[MCU2_0]     15.774499 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     15.774528 s: VHWA: MSC Init ... !!!
[MCU2_0]     15.780032 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     15.780059 s: VHWA: NF Init ... !!!
[MCU2_0]     15.780851 s: VHWA: NF Init ... Done !!!
[MCU2_0]     15.780876 s: VHWA: VISS Init ... !!!
[MCU2_0]     15.785959 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     15.785995 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     15.786028 s: VX_ZONE_INIT:Enabled
[MCU2_0]     15.786048 s: VX_ZONE_ERROR:Enabled
[MCU2_0]     15.786064 s: VX_ZONE_WARNING:Enabled
[MCU2_0]     15.787010 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0
[MCU2_0]     15.787109 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF
[MCU2_0]     15.787210 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1
[MCU2_0]     15.787298 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1
[MCU2_0]     15.787391 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2
[MCU2_0]     15.787531 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1
[MCU2_0]     15.787646 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1
[MCU2_0]     15.787760 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2
[MCU2_0]     15.787865 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1
[MCU2_0]     15.787967 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2
[MCU2_0]     15.788057 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX
[MCU2_0]     15.788163 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3
[MCU2_0]     15.788266 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4
[MCU2_0]     15.788369 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5
[MCU2_0]     15.788473 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6
[MCU2_0]     15.788576 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7
[MCU2_0]     15.788692 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8
[MCU2_0]     15.788793 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1
[MCU2_0]     15.788894 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2
[MCU2_0]     15.788991 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3
[MCU2_0]     15.789089 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4
[MCU2_0]     15.789173 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX2
[MCU2_0]     15.789208 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_0]     15.789232 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     15.796088 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     15.796122 s: CSI2RX: Init ... !!!
[MCU2_0]     15.796140 s: SCICLIENT: Sciclient_pmSetModuleState module=136 state=2
[MCU2_0]     15.796204 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.796229 s: SCICLIENT: Sciclient_pmSetModuleState module=38 state=2
[MCU2_0]     15.796295 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.796315 s: SCICLIENT: Sciclient_pmSetModuleState module=39 state=2
[MCU2_0]     15.796372 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.796393 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]     15.796443 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.796463 s: SCICLIENT: Sciclient_pmSetModuleState module=153 state=2
[MCU2_0]     15.796511 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.796634 s: CSI2RX: Init ... Done !!!
[MCU2_0]     15.796655 s: CSI2TX: Init ... !!!
[MCU2_0]     15.796671 s: SCICLIENT: Sciclient_pmSetModuleState module=136 state=2
[MCU2_0]     15.796718 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.796738 s: SCICLIENT: Sciclient_pmSetModuleState module=40 state=2
[MCU2_0]     15.796802 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.796824 s: SCICLIENT: Sciclient_pmSetModuleState module=41 state=2
[MCU2_0]     15.796879 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.796900 s: SCICLIENT: Sciclient_pmSetModuleState module=363 state=2
[MCU2_0]     15.796953 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.796973 s: SCICLIENT: Sciclient_pmSetModuleState module=364 state=2
[MCU2_0]     15.797024 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     15.797084 s: CSI2TX: Init ... Done !!!
[MCU2_0]     15.797103 s: ISS: Init ... !!!
[MCU2_0]     15.797127 s: IssSensor_Init ... Done !!!
[MCU2_0]     15.797177 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     15.797196 s: ISS: Init ... Done !!!
[MCU2_0]     15.797214 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     15.797257 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     15.797277 s: UDMA Copy: Init ... !!!
[MCU2_0]     15.798064 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     15.798121 s: APP: Init ... Done !!!
[MCU2_0]     15.798140 s: APP: Run ... !!!
[MCU2_0]     15.798155 s: IPC: Starting echo test ...
[MCU2_0]     15.798677 s: APP: Run ... Done !!!
[MCU2_0]     15.799268 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C7X_1[.] C7X_2[.]
    15.499681 s: VX_ZONE_INIT:[tivxInitLocal:135] Initialization Done !!!
    16.338346 s: VX_ZONE_INIT:[tivxHostInitLocal:106] Initialization Done for HOST !!!
FS: Init !!!
FS: Mount Filesystem !!!
[MCU2_0]     15.799322 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C7X_1[P] C7X_2[.]
[MCU2_0]     15.799365 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C7X_1[P] C7X_2[P]
[MCU2_1]     10.131156 s: CIO: Init ... Done !!!
[MCU2_1]     10.131205 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]     10.131229 s: CPU is running FreeRTOS
[MCU2_1]     10.131244 s: APP: Init ... !!!
[MCU2_1]     10.131274 s: SCICLIENT: Init ... !!!
[MCU2_1]     10.131387 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
[MCU2_1]     10.131414 s: SCICLIENT: DMSC FW revision 0x9
[MCU2_1]     10.131433 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]     10.131452 s: SCICLIENT: Init ... Done !!!
[MCU2_1]     10.131471 s: UDMA: Init ... !!!
[MCU2_1]     10.132304 s: UDMA: Init ... Done !!!
[MCU2_1]     10.132335 s: MEM: Init ... !!!
[MCU2_1]     10.132358 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ ba000000 of size 16777216 bytes !!!
[MCU2_1]     10.132397 s: MEM: Init ... Done !!!
[MCU2_1]     10.132413 s: IPC: Init ... !!!
[MCU2_1]     10.132441 s: IPC: 5 CPUs participating in IPC !!!
[MCU2_1]     10.132465 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]     15.198193 s: IPC: HLOS is ready !!!
[MCU2_1]     15.201753 s: IPC: Init ... Done !!!
[MCU2_1]     15.201783 s: APP: Syncing with 4 CPUs ... !!!
[MCU2_1]     15.201808 s: APP: Syncing with 4 CPUs ... Done !!!
[MCU2_1]     15.201828 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]     15.202265 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]     15.202299 s: FVID2: Init ... !!!
[MCU2_1]     15.202332 s: FVID2: Init ... Done !!!
[MCU2_1]     15.202351 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]     15.202367 s: SCICLIENT: Sciclient_pmSetModuleState module=58 state=2
[MCU2_1]     15.202452 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     15.202475 s: SCICLIENT: Sciclient_pmSetModuleState module=62 state=2
[MCU2_1]     15.202529 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     15.202550 s: VHWA: DOF Init ... !!!
[MCU2_1]     15.206137 s: VHWA: DOF Init ... Done !!!
[MCU2_1]     15.206172 s: VHWA: SDE Init ... !!!
[MCU2_1]     15.207301 s: VHWA: SDE Init ... Done !!!
[MCU2_1]     15.207329 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]     15.207357 s: VX_ZONE_INIT:Enabled
[MCU2_1]     15.207374 s: VX_ZONE_ERROR:Enabled
[MCU2_1]     15.207389 s: VX_ZONE_WARNING:Enabled
[MCU2_1]     15.208332 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1
[MCU2_1]     15.208427 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE
[MCU2_1]     15.208515 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF
[MCU2_1]     15.208548 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_1]     15.208571 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]     15.208704 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]     15.208727 s: UDMA Copy: Init ... !!!
[MCU2_1]     15.209521 s: UDMA Copy: Init ... Done !!!
[MCU2_1]     15.209553 s: APP: Init ... Done !!!
[MCU2_1]     15.209570 s: APP: Run ... !!!
[MCU2_1]     15.209585 s: IPC: Starting echo test ...
[MCU2_1]     15.210110 s: APP: Run ... Done !!!
[MCU2_1]     15.210517 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C7X_1[P] C7X_2[.]
[MCU2_1]     15.210567 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C7X_1[P] C7X_2[P]
[MCU2_1]     15.799166 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C7X_1[P] C7X_2[P]
[C7x_1 ]     11.492298 s: CIO: Init ... Done !!!
[C7x_1 ]     11.492314 s: ### CPU Frequency = 1000000000 Hz
[C7x_1 ]     11.492325 s: CPU is running FreeRTOS
[C7x_1 ]     11.492334 s: APP: Init ... !!!
[C7x_1 ]     11.492341 s: SCICLIENT: Init ... !!!
[C7x_1 ]     11.492440 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
[C7x_1 ]     11.492454 s: SCICLIENT: DMSC FW revision 0x9
[C7x_1 ]     11.492464 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]     11.492475 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]     11.492484 s: UDMA: Init ... !!!
[C7x_1 ]     11.493277 s: UDMA: Init ... Done !!!
[C7x_1 ]     11.493291 s: MEM: Init ... !!!
[C7x_1 ]     11.493302 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 117000000 of size 268435456 bytes !!!
[C7x_1 ]     11.493325 s: MEM: Init ... Done !!!
[C7x_1 ]     11.493334 s: IPC: Init ... !!!
[C7x_1 ]     11.493350 s: IPC: 5 CPUs participating in IPC !!!
[C7x_1 ]     11.493365 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]     15.198091 s: IPC: HLOS is ready !!!
[C7x_1 ]     15.200077 s: IPC: Init ... Done !!!
[C7x_1 ]     15.200092 s: APP: Syncing with 4 CPUs ... !!!
[C7x_1 ]     15.201809 s: APP: Syncing with 4 CPUs ... Done !!!
[C7x_1 ]     15.201825 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]     15.201999 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]     15.202021 s: VX_ZONE_INIT:Enabled
[C7x_1 ]     15.202032 s: VX_ZONE_ERROR:Enabled
[C7x_1 ]     15.202041 s: VX_ZONE_WARNING:Enabled
[C7x_1 ]     15.202241 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1
[C7x_1 ]     15.202311 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2
[C7x_1 ]     15.202377 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3
[C7x_1 ]     15.202439 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4
[C7x_1 ]     15.202503 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5
[C7x_1 ]     15.202571 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6
[C7x_1 ]     15.202640 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7
[C7x_1 ]     15.202704 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8
[C7x_1 ]     15.202727 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_1 ]     15.202739 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]     15.202892 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]     15.202906 s: APP: Init ... Done !!!
[C7x_1 ]     15.202915 s: APP: Run ... !!!
[C7x_1 ]     15.202923 s: IPC: Starting echo test ...
[C7x_1 ]     15.203037 s: APP: Run ... Done !!!
[C7x_1 ]     15.204372 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C7X_1[s] C7X_2[P]
[C7x_1 ]     15.210510 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C7X_1[s] C7X_2[P]
[C7x_1 ]     15.799187 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C7X_1[s] C7X_2[P]
[C7x_2 ]     12.379303 s: CIO: Init ... Done !!!
[C7x_2 ]     12.379318 s: ### CPU Frequency = 1000000000 Hz
[C7x_2 ]     12.379330 s: CPU is running FreeRTOS
[C7x_2 ]     12.379339 s: APP: Init ... !!!
[C7x_2 ]     12.379346 s: SCICLIENT: Init ... !!!
[C7x_2 ]     12.379449 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
[C7x_2 ]     12.379463 s: SCICLIENT: DMSC FW revision 0x9
[C7x_2 ]     12.379473 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_2 ]     12.379484 s: SCICLIENT: Init ... Done !!!
[C7x_2 ]     12.379494 s: UDMA: Init ... !!!
[C7x_2 ]     12.380287 s: UDMA: Init ... Done !!!
[C7x_2 ]     12.380300 s: MEM: Init ... !!!
[C7x_2 ]     12.380313 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 127000000 of size 16777216 bytes !!!
[C7x_2 ]     12.380335 s: MEM: Init ... Done !!!
[C7x_2 ]     12.380344 s: IPC: Init ... !!!
[C7x_2 ]     12.380360 s: IPC: 5 CPUs participating in IPC !!!
[C7x_2 ]     12.380374 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_2 ]     15.198119 s: IPC: HLOS is ready !!!
[C7x_2 ]     15.200291 s: IPC: Init ... Done !!!
[C7x_2 ]     15.200306 s: APP: Syncing with 4 CPUs ... !!!
[C7x_2 ]     15.201809 s: APP: Syncing with 4 CPUs ... Done !!!
[C7x_2 ]     15.201824 s: REMOTE_SERVICE: Init ... !!!
[C7x_2 ]     15.201999 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_2 ]     15.202024 s: VX_ZONE_INIT:Enabled
[C7x_2 ]     15.202036 s: VX_ZONE_ERROR:Enabled
[C7x_2 ]     15.202046 s: VX_ZONE_WARNING:Enabled
[C7x_2 ]     15.202588 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP-1
[C7x_2 ]     15.202609 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_2 ]     15.202622 s: APP: OpenVX Target kernel init ... !!!
[C7x_2 ]     15.202929 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_2 ]     15.202943 s: UDMA Copy: Init ... !!!
[C7x_2 ]     15.203989 s: UDMA Copy: Init ... Done !!!
[C7x_2 ]     15.204003 s: APP: Init ... Done !!!
[C7x_2 ]     15.204012 s: APP: Run ... !!!
[C7x_2 ]     15.204020 s: IPC: Starting echo test ...
[C7x_2 ]     15.204128 s: APP: Run ... Done !!!
[C7x_2 ]     15.204377 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C7X_1[P] C7X_2[s]
[C7x_2 ]     15.210521 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C7X_1[P] C7X_2[s]
[C7x_2 ]     15.799194 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C7X_1[P] C7X_2[s]
FS: Mounted '172.17.115.1:/var/tcon/target/ti-tda4al/nfs/tiovx/09_01_00_06' to '/nfs'!
FS: done !!!
VxTests version: unknown
VCS version: unknown
Build config: unknown

[ ======== ] Total 23771 tests from 177 test cases
Use global OpenVX context: FALSE

[ -------- ] tests from tivxTestKernelsNotNot
[ RUN 0001 ] tivxTestKernelsNotNot.Sizes/0/640x480 ...
[C7x_2 ]     19.754138 s: VX_ZONE_ERROR:[ownTargetCmdDescHandler:1115] object descriptor type is invalid

0 Gokul S 7 months ago in reply to Marco K

TI__Genius 12010 points

Hi Marco,

Can you share the info on which application are you running and how you are running the application

Regards,
Gokul

0 Marco K 7 months ago in reply to Gokul S

Prodigy 130 points

Hi Gokul,

I run the application vx_app_conformance which I have cross-compiled for PikeOS using our own CDK (GCC 7.5.0), which has been integrated into the concerto infrastructure.
The application is started without argument.

Here is an excerpt of the make vision_apps build log:

[GCC] Compiling C99 main.c
/opt/pikeos-5.1/cdk/arm/v8hf/bin/arm_v8hf-gcc -std=c99 -c -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/apps/tests/app_vx_conformance -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/tiovx/include -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/tiovx/kernels/include -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/tiovx/utils/include -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/tiovx/kernels_j7/include -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/imaging/kernels/include -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/video_io/kernels/include -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/c7x-mma-tidl/arm-tidl/tiovx_kernels/include -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/c7x-mma-tidl/arm-tidl/rt/inc -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vxlib/packages -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/ivision -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/tiadalg/include -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/imaging -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/app_utils -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/platform/j721s2/pikeos/mpu1 -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/platform/j721s2/pikeos -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/platform/j721s2/rtos/common -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/platform/j721s2/rtos -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/tiovx -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/tiovx/conformance_tests -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/c7x-mma-tidl -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/c7x-mma-tidl/ti_dl -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/c7x-mma-tidl/arm-tidl -I/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/sdk_builder/concerto/include -DSOC_J721S2 -DPIKEOS -DJ721S2 -DA72="A72" -DTARGET_NUM_CORES=1 -DTARGET_ARCH=64 -DARCH_64 -DARM -DTARGET_BUILD=1 -Wall -fms-extensions -Wno-write-strings -Wno-format-security -fno-builtin -Wall -Wextra -Wundef -DARM_V8HF -DARM_CPU_V8 -DARM_LPAE -mfix-cortex-a53-835769 -mfix-cortex-a53-843419 -DPIKEOS_BUILD_ID="\"devel-mko@mko-lap-040225-11:26\"" -DPOSIX_LWIP -I/home/mko/src/work/22047-Scala3/testing_ws/pool/posix/lwip/include/opts -I/opt/pikeos-5.1/target/arm/v8hf/posix/lwip/include/opts -I/home/mko/src/work/22047-Scala3/testing_ws/pool/posix/lwip/include -I/opt/pikeos-5.1/target/arm/v8hf/posix/lwip/include -DPOSIX_NFSCL -I/home/mko/src/work/22047-Scala3/testing_ws/pool/posix/nfscl/include -I/opt/pikeos-5.1/target/arm/v8hf/posix/nfscl/include -isystem /home/mko/src/work/22047-Scala3/testing_ws/pool/posix/include -isystem /opt/pikeos-5.1/target/arm/v8hf/posix/include -I/home/mko/src/work/22047-Scala3/testing_ws/pool/include -I/opt/pikeos-5.1/target/arm/v8hf/include -I/home/mko/src/work/22047-Scala3/testing_ws/pool/driver/include -I/opt/pikeos-5.1/target/arm/v8hf/driver/include -DPIKEOS_POSIX -Wno-format-truncation -DBUILD_CT_TIOVX_TEST_KERNELS -DBUILD_CT_TIOVX -DBUILD_CT_TIOVX_INTERNAL -DBUILD_CT_KHR -DBUILD_CT_TIOVX_HWA -std=c99 -g -fno-strict-aliasing -fno-delete-null-pointer-checks -fno-strict-overflow -fno-common -frecord-gcc-switches -Wold-style-definition -Wnested-externs -Wmissing-prototypes -Wstrict-prototypes -Waggregate-return -Wpointer-arith -Wcast-qual -Wwrite-strings -Wshadow -Wdeprecated -Wlogical-op -Wtrampolines -Wsuggest-attribute=format -O1 -foptimize-sibling-calls -fomit-frame-pointer -MMD -MF /home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release/module/apps.tests.app_vx_conformance/main.dep -MT '/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release/module/apps.tests.app_vx_conformance/main.o' /home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/apps/tests/app_vx_conformance/main.c -o /home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release/module/apps.tests.app_vx_conformance/main.o
Linking /home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release/vx_app_conformance.elf
/opt/pikeos-5.1/cdk/arm/v8hf/bin/arm_v8hf-ld -T/opt/pikeos-5.1/target/arm/v8hf/ldscript/app.ld --fix-cortex-a53-843419 -L/home/mko/src/work/22047-Scala3/testing_ws/pool/posix/lwip/lib -L/opt/pikeos-5.1/target/arm/v8hf/posix/lwip/lib -L/home/mko/src/work/22047-Scala3/testing_ws/pool/posix/nfscl/lib -L/opt/pikeos-5.1/target/arm/v8hf/posix/nfscl/lib -L/home/mko/src/work/22047-Scala3/testing_ws/pool/posix/lib -L/opt/pikeos-5.1/target/arm/v8hf/posix/lib -L/home/mko/src/work/22047-Scala3/testing_ws/pool/posix/os/up/ -L/opt/pikeos-5.1/target/arm/v8hf/posix/os/up/ -L/home/mko/src/work/22047-Scala3/testing_ws/pool/lib -L/opt/pikeos-5.1/target/arm/v8hf/lib -L/opt/pikeos-5.1/cdk/arm/v8hf/lib/gcc/aarch64-unknown-elf/7.5.0/ /home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release/module/apps.tests.app_vx_conformance/main.o -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/app_utils/lib/J721S2/A72/PIKEOS/release -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/video_io/lib/J721S2/A72/PIKEOS/release -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/tiovx/lib/J721S2/A72/PIKEOS/release -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/imaging/lib/J721S2/A72/PIKEOS/release -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/ethfw/lib/J721S2/A72/PIKEOS/release -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/ti-perception-toolkit/lib/J721S2/A72/PIKEOS/release -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/c7x-mma-tidl/arm-tidl/tiovx_kernels/lib/J721S2/A72/PIKEOS/release -L/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/lib/J721S2/A72/PIKEOS/release --start-group -lvx_vxu -lvx_framework -lvx_kernels_host_utils -lvx_kernels_target_utils -lvx_platform_psdk_j7 -lvx_kernels_openvx_core -lvx_kernels_openvx_ext -lvx_target_kernels_openvx_ext -lvx_utils -lvx_kernels_hwa -lvx_kernels_video_io -lvx_kernels_tidl -lvx_kernels_tvm -lvx_nested_kernels_tidl -lvx_tutorial -lapp_utils_mem -lapp_utils_ipc -lapp_utils_console_io -lapp_utils_file_io -lapp_utils_remote_service -lapp_utils_perf_stats -lapp_utils_grpx -lapp_utils_draw2d -lapp_utils_hwa -lapp_utils_init -lapp_rtos_pikeos_mpu1_common -lapp_utils_iss -lvx_kernels_imaging -lvx_tiovx_tests -lvx_tiovx_internal_tests -lvx_conformance_tests -lvx_conformance_engine -lvx_conformance_tests_testmodule -lvx_tiovx_tidl_tests -lvx_kernels_openvx_ext_tests -lvx_kernels_test_kernels_tests -lvx_kernels_test_kernels -lvx_target_kernels_source_sink -lvx_kernels_hwa_tests -lvx_kernels_video_io_tests -lvx_tiovx_tvm_tests -lvx_kernels_srv_tests -lvx_applib_tests -lapp_utils_misc -lrpmsg-posix -ladtbase -ladtcrc32 -lconfbin -ladtavl -llwip -lsbuf -lnfscl -lnfsrpc -lrpc_lwip -lm -lc -lpse51 -lvm -lstand -lp4 -lgcc -lgcc_extra --end-group -o /home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release/vx_app_conformance.elf -Map=/home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release/vx_app_conformance.elf.map > /dev/null
mkdir -p /home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release/module/apps.tests.app_vx_conformance_hwa/ 2> /dev/null
touch /home/mko/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/PIKEOS/release/module/apps.tests.app_vx_conformance_hwa/.gitignore

0 Gokul S 7 months ago in reply to Marco K

TI__Genius 12010 points

Hi Marco,

Can you run the conformance test like ./vx_app_conformace after you boot up pikeos and share your entire logs here, this is to isolate the boot logs and application logs.

Regards,
Gokul

0 Marco K 7 months ago in reply to Gokul S

Prodigy 130 points

Hi Gokul,

due to the architecture of the PikeOS POSIX application I cannot completely separate the initialization from the application. I ran the tests again with an inserted 10 sec sleep between the initialization and the start of the test suite.

This is the log after the 10 sec sleep:

Wait 10sec ...
All Initialization done.

VxTests version: unknown
VCS version: unknown
Build config: unknown

[ ======== ] Total 23771 tests from 177 test cases
Use global OpenVX context: FALSE

[ -------- ] tests from tivxTestKernelsNotNot
[ RUN 0001 ] tivxTestKernelsNotNot.Sizes/0/640x480 ...
[C7x_2 ] 19.754138 s: VX_ZONE_ERROR:[ownTargetCmdDescHandler:1115] object descriptor type is invalid

Regards,
Marco

0 Gokul S 7 months ago in reply to Marco K

TI__Genius 12010 points

Hi Marco,

Is the appInit() called before printing "All Initialization done." I am seeing init log when i run the app

attaching the log below,

APP: Init ... !!!
124142.650010 s: MEM: Init ... !!!
124142.650068 s: MEM: Initialized DMA HEAP (fd=5) !!!
124142.650175 s: MEM: Init ... Done !!!
124142.650186 s: IPC: Init ... !!!
124142.706571 s: IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
124142.710697 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
124142.710783 s:  VX_ZONE_INIT:Enabled
124142.710792 s:  VX_ZONE_ERROR:Enabled
124142.710798 s:  VX_ZONE_WARNING:Enabled
124142.713910 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-0 
124142.714101 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-1 
124142.714187 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-2 
124142.714281 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-3 
124142.714291 s:  VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!!
124142.714747 s:  VX_ZONE_INIT:[tivxHostInitLocal:106] Initialization Done for HOST !!!
VxTests version: unknown
VCS version: unknown
Build config: Release

[ ======== ] Total 23857 tests from 202 test cases
Use global OpenVX context: FALSE

Check this once.

Regards,
Gokul

0 Marco K 7 months ago in reply to Gokul S

Prodigy 130 points

Hi Gokul,

yes, appInit() is called without problems.
The output you posted is also present on my side.

Regards,
Marco

0 Gokul S 7 months ago in reply to Marco K

TI__Genius 12010 points

Hi Marco,

can you please share the entire logs from boot to application without leaving anything.

Is the memory map modified ?

we are not sure why this is coming, is there any other demos or tests running properly on pikeOS ?

Regards,
Gokul

0 Marco K 7 months ago in reply to Gokul S

Prodigy 130 points

Hi Gokul,

you can find the entire log in my post from January 31st.

My interpretation of the error is that the initialization of the object descriptor array on the A72 is not correctly propagated to the C71X via the MSMC when the cache for the memory area is configured with the following cache attributes:

ATTR0: 1
ATTR1: 1
ATTR2: 1
SH0: 1
SH1: 1

I also tried with SH0: 0, SH1: 1 to mark the mapping as "outer shareable" without effect.

Are my assumptions reasonable?

Thanks and kind regards,
Marco

0 Gokul S 7 months ago in reply to Marco K

TI__Genius 12010 points

Hi Marco,

Object descriptor array is created by A72 in ddr_shared_memory and it sends the address to the remote cores (c7x) through IPC. IPC memory regions are allocated in ddr and configured as non-cacheable. I don't think MSMC is involving here, let me get back to you with this.

Marco K said:
you can find the entire log in my post from January 31st.

I couldn't able to see the below log from your post, can you check that once.

VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-0

Also can you share the application execution flow, like after booting pikeos you will be running 2 applications vx_app_arm_remote_log.out and vx_app_conformace.out. in what sequence are you starting and when these apps are starting whether before or after booting the remote core.

Regards,
Gokul

0 Marco K 7 months ago in reply to Gokul S

Prodigy 130 points

Hi Gokul,

Gokul S said:
Object descriptor array is created by A72 in ddr_shared_memory and it sends the address to the remote cores (c7x) through IPC. IPC memory regions are allocated in ddr and configured as non-cacheable. I don't think MSMC is involving here, let me get back to you with this.

You are correct about the IPC memory. The A72 sends an IPC with an index in the object descriptor array to the C7X and that index is correctly received, but the content of the object descriptor array is not fully propagated to the C7X.

In vision_apps/platform/j721s2/rtos/app_mem_map.h I found the following:
/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 63.75 MB ] */#define TIOVX_OBJ_DESC_MEM_ADDR (0xAA040000u)#define TIOVX_OBJ_DESC_MEM_SIZE (0x03FC0000u)

If I map this memory non-cached, there is no problem, but I wanted to map it cache-coherent to see if I can gain a performance boost. That is were I see the described problems.

Gokul S said:
I couldn't able to see the below log from your post, can you check that once.

VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MPU-0

It is not there. But the same is true when I start the vx_app_conformance.out binary on Linux.
Also when I search for the tivxPlatformCreateTargetId() I only find that MPU_0 is created as "TIVX_CPU0".
Although that output is not visible as well, I know from previous development work that this target is actually created.

Gokul S said:
Also can you share the application execution flow, like after booting pikeos you will be running 2 applications vx_app_arm_remote_log.out and vx_app_conformace.out. in what sequence are you starting and when these apps are starting whether before or after booting the remote core.

The POSIX layer on which this is implemented does not work like Linux. There is no command line to start multiple applications. PikeOS only loads the vx_app_conformance application binary corresponding to a static configuration. This binary handles the complete TIOVX initialization including triggering the IPC synchronization with the remote processors.

The remote processors are loaded and started before PikeOS boots using either U-Boot or SBL.

Kind regards,
Marco

0 Gokul S 6 months ago in reply to Marco K

TI__Genius 12010 points

Hi Marco,

Marco K said:
If I map this memory non-cached, there is no problem,

Conformance test is running without any issue if its non-cached, is that correct ?

Marco K said:
I wanted to map it cache-coherent to see if I can gain a performance boost.

We have not validated with cache-coherent, when we do that r5f cores are not cache-coherent and needs cache operations,

it wouldn’t provide any benefit as the object descriptors just holds the pointer for the actual data and each object descriptor will be of 1KB in size.

we recommend to go with non-cache configuration.

Regards,
Gokul

0 Marco K 6 months ago in reply to Gokul S

Prodigy 130 points

Hi Gokul,

Gokul S said:
Conformance test is running without any issue if its non-cached, is that correct ?

Correct.

Gokul S said:
We have not validated with cache-coherent, when we do that r5f cores are not cache-coherent and needs cache operations,

it wouldn’t provide any benefit as the object descriptors just holds the pointer for the actual data and each object descriptor will be of 1KB in size.

we recommend to go with non-cache configuration.

Ok. That's fine for me.
Thank you for looking into that.
Much appreciated.

Kind regards,
Marco

Processors

Processors forum

TDA4AL-Q1: Activate cache coherency across MAIN domain on A72 (cont.)