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Original question:

TDA4AH-Q1: CPSW9G SERDES - Port Mapping

TDA4AH-Q1: CPSW9G SERDES - SERDES1 and SERDES2 Allocation

AB
Prodigy 50 points
Part Number: TDA4AH-Q1

Tool/software:

Hi TI Expert,

I need confirmations related to this SERDES allocation/configuration and QSGMII application restriction:

SPRUJ52C Table 12-198. SERDES0/1/2/4 Supported Configurations

                       

Will it be possible to do this configuration to use all SERDES link, at his full capability ?

SERDES0: 1x4L of PCIE1

SERDES1:

Lane0 SGMII3

Lane1 SGMII4

Lane2 PCIE2 Lane0

Lane3 PCIE2 Lane1

SERDES2:

Lane0 QSGMII5 or SGMII5

Lane1 NA

Lane2 USXGMII on SGMII1 (10Gbps)

Lane3 USXGMII on SGMII2 (10Gbps)

Especially the full capability of the 2 USXGMII Links on the same SERDES Block ?

Could you confirm that this configuration, the QSGMII link will not trouble the other link ?

In regards with this information, taken from :

SPRSP79B Table 4-1. Device Comparison  Remark7

If QSGMII is used on any SGMII Port 1 thru 4, then SGMII1/2/3/4 cannot be used for Ethernet functionality since all 4 internal CPSW
ports map to the selected QSGMII SERDES port.

If QSGMII is used on any SGMII Port 5 thru 8, then SGMII5/6/7/8 cannot be used for Ethernet functionality since all 4 internal CPSW
ports map to the selected QSGMII SERDES port.

Regards,

AB

  • 0
    TI__Guru 51190 points

    Hi,

    AB said:
    SERDES0: 1x4L of PCIE1

    Yes, SerDes0 Single link PCIe1 can be used.

    AB said:

    SERDES1:

    Lane0 SGMII3

    Lane1 SGMII4

    Lane2 PCIE2 Lane0

    Lane3 PCIE2 Lane1

    Yes, SerDes1 as SGMII + PCIe2 Multi-link combination can be used.

    AB said:

    SERDES2:

    Lane0 QSGMII5 or SGMII5

    Lane1 NA

    Lane2 USXGMII on SGMII1 (10Gbps)

    Lane3 USXGMII on SGMII2 (10Gbps)

    If you want to use QSGMII then you need to have at least one QSGMII SUB Port.
    As above SGMII3, SGMII4 and USXGMII1/SGMII1, USXGMII2/SGMII2 are used you can use 6,7,8 in QSGMII SUB Ports and QSGMII5 as Main Port.

    If you want to use in SGMII5 then no issue.

    You can use SGMII + USXGMII / QSGMII + USXGMII Multi-link configuration.

    If you want to use SGMII5, SGMII1, SGMII2 then you need enable all 4 lanes of SerDes2.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 50 points

    Hi,

    Thank you for the speedy response.

    Could we use the PCIe0 Lane2 and Lane3, instead of PCIe2 Lane0 and Lane1, to be compatible with the configuration explained above ?

    and at full capability of each SERDES/Lanes ?

    The PCIe2 is linked to the 64bit Domain, who is not directly accessible from the 32 bit domain from R5 Core. It's very restrictive for us.

    Best Regards,

    AB

  • 0 in reply to AB
    TI__Guru 51190 points

    Hi, 

    AB said:
    Could we use the PCIe0 Lane2 and Lane3, instead of PCIe2 Lane0 and Lane1, to be compatible with the configuration explained above ?

    Let me check with our PCIe expert whether we can use Lane2, Lane3 without Lane0, Lane1. 

    AB said:
    and at full capability of each SERDES/Lanes ?

    Yes, you can at max of two functionalities on each Serdes lane. 

    AB said:
    The PCIe2 is linked to the 64bit Domain, who is not directly accessible from the 32 bit domain from R5 Core. It's very restrictive for us

    Okay, understood.

    If you want acess one functionality of SerDes use in Linux A72 and other in RTOS R5F, SerDes to be configured at boot layer at U-boot and use from Linux and RTOS with each different functionality. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru 51190 points

    Hi,

    Doredla Sudheer Kumar said:
    AB said:
    Could we use the PCIe0 Lane2 and Lane3, instead of PCIe2 Lane0 and Lane1, to be compatible with the configuration explained above ?

    Let me check with our PCIe expert whether we can use Lane2, Lane3 without Lane0, Lane1. 

    We never tried using PCIe0 Lane2 and Lane3 without using Lane0 and Lane1.
    We think you can't use only Lane2, Lane3 as "The PCIe controller Lane 0 will always be the master lane for any lane width."

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 50 points

    Hi,

    Doredla Sudheer Kumar said:
    If you want to use SGMII5, SGMII1, SGMII2 then you need enable all 4 lanes of SerDes2.

    Could you explain why you precise that all Lanes of SerDes2 have to be enabled, even if we don't want to use Lane1 ?

    Doredla Sudheer Kumar said:
    We think you can't use only Lane2, Lane3 as "The PCIe controller Lane 0 will always be the master lane for any lane width."

    In this case, could we use the configuration below in order to keep the PCIe0 Lane0 and Lane1 ?

    SERDES1:

    Lane0 PCIE0 Lane0

    Lane1 PCIE0 Lane1

    Lane2 SGMII1

    Lane3 SGMII2

    SERDES2:

    Lane0 QSGMII5 or SGMII5

    Lane1 NA

    Lane2 USXGMII on SGMII7  or SGMII1 (10Gbps)

    Lane3 USXGMII on SGMII8 or SGMII2 (10Gbps)

    Regards,

    AB

  • 0 in reply to AB
    TI__Guru 51190 points

    Hi,

    AB said:
    Doredla Sudheer Kumar said:
    If you want to use SGMII5, SGMII1, SGMII2 then you need enable all 4 lanes of SerDes2.

    Could you explain why you precise that all Lanes of SerDes2 have to be enabled, even if we don't want to use Lane1 ?

    The SerDes driver can't configure the alternative lanes for the same functionalities from Linux driver.
    RTOS driver supports to configure the lanes required.

    AB said:

    SERDES1:

    Lane0 PCIE0 Lane0

    Lane1 PCIE0 Lane1

    Lane2 SGMII1

    Lane3 SGMII2

    SERDES2:

    Lane0 QSGMII5 or SGMII5

    Lane1 NA

    Lane2 USXGMII on SGMII7  or SGMII1 (10Gbps)

    Lane3 USXGMII on SGMII8 or SGMII2 (10Gbps)

    Yes, this is possible.
    SerDes1:
    PCIe + SGMII Multi-link configuration.

    SerDes2:
    Lane2, Lane3 in USXGMII for 10Gbps.
    If 1Gbps link speed is fine then you can use SGMII.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 50 points

    Hi,

    Thank you,

    If we use only SGMII7 and SGMII8 for USXGMII, is the configuration still usable ?

    SERDES1:

    Lane0 PCIE0 Lane0

    Lane1 PCIE0 Lane1

    Lane2 SGMII1

    Lane3 SGMII2

    SERDES2:

    Lane0 QSGMII5 or SGMII5

    Lane1 NA

    Lane2 USXGMII on SGMII7  (10Gbps)

    Lane3 USXGMII on SGMII8  (10Gbps)

    Regards,

    AB

  • 0 in reply to AB
    TI__Guru 51190 points

    Hi, 

    AB said:
    If we use only SGMII7 and SGMII8 for USXGMII, is the configuration still usable ?

    No. 

    Port-7/8 doesn't support USXGMII interface. Only port-1 and port-2 supports USXGMII. 

    Best Regards 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 50 points

    Hi,

    If we choose this clocks for each SERDES, can we use the configuration below ?

    SERDES1:

    Lane0 PCIE0 Lane0

    Lane1 PCIE0 Lane1

    Lane2 USXGMII on SGMII1  (10Gbps)

    Lane3 USXGMII on SGMII2  (10Gbps)

    With an External clock of 156.25MHz for USXGMII

    SERDES2:

    Lane0 QSGMII5

    Lane1 NA

    Lane2 SGMII7

    Lane3 SGMII8

    With an External clock of 100 MHz for SGMII

    Best Regards,

    AB

  • 0 in reply to AB
    TI__Guru 51190 points

    Hi,

    AB said:

    SERDES1:

    Lane0 PCIE0 Lane0

    Lane1 PCIE0 Lane1

    Lane2 USXGMII on SGMII1  (10Gbps)

    Lane3 USXGMII on SGMII2  (10Gbps)

    With an External clock of 156.25MHz for USXGMII

    Above is SerDes Multi-link configuration with PCIe + USXGMII / PCIe + SGMII

    PCIe + USXGMII needs 100Hz clock for PCIe and 156.25MHz clock for USXGMII
    PCIe + SGMII needs 100MHz clock for PCIe and SGMII as well.

    TI SoC TDA4AH is capable of supplying clocks required for SerDes i.e. using internal clocks for SerDes.
    If required you can feed external clocks as well for SerDes.

    AB said:

    SERDES2:

    Lane0 QSGMII5

    Lane1 NA

    Lane2 SGMII7

    Lane3 SGMII8

    With an External clock of 100 MHz for SGMII

    Above is SerDes Multi-link configuration with QSGMII + SGMII.
    Both interfaces will use 100Mz clock.
    As mentioned above if required you can feed external clock as well.

    Best Regards,
    Sudheer