DMA transfer never finishes sometimes when reading data from NAND flash

Jiri,

Given the random occurrence of this problem it is difficult to say what could be the issue without more information. It will be necessary to know

1) how the DMA is configured

2) what other activities is the DSP doing while this data transfer is going on

3) if you have other DMA transfers at the same time

4)  is another peripheral accessing the same DMA data buffer in parallel

If you can encounter this in debug mode, you can halt program execution and note down the state of the DMA channel, if the addresses are correct, whether it has completed part of the transfer and waiting for more data from flash and the state of the EMIF, etc.

Have you noticed this behavior on multiple boards? It could be that you have a bad NAND flash. It will be a good experiment if you are able to swap out the NAND flash.

Regards,

Sunil

Hello Sunil,

Thank you for your answer. The DMA is configured the same way as in the CSL NAND DMA Example. I use DMA for transfers between CPU and NAND flash only. In one time it should be active one DMA transfer only. The problem is probably related to USB communication because it happens when USB communication is running. But now I have made a test I have read data via USB periodically every 1 second for about 1 hour and it all was ok.

When I transfer the data via USB I use the DMA but USB module has its own DMA controller, right? Can USB DMA controller affect the DMA transfer between CPU and NAND flash?

I tried the software and hardware (by watchdog) reset when the DMA transfer remained unfinished. In this situation the initialization of the CSL NAND module is not success. The CSL NAND_Setup function never ends. I have found the problem is at this line: CSL_FINS(hNand->regs->AWCCR2, EMIF_AWCCR2_CS2_WAIT, nandConfig->asyncWaitCfg->nandPort). It should read from and write to AWCCR2 register, right? But it fails and the debbuger write these error messages:

Can't Single Step Target Program: Error 0x00000022/-2130 Error during: Memory, Execution,  Cannot access memory address at 0x00000800
Trouble Reading PC Register: Error 0x00000004/-1143 Error during: Register,  The memory at 0x00000000 continually indicated it was 'not ready' All memory operations currently in progress were aborted in order to regain control of the processor. This is considered a catastrophic event, but the debugger should  still be able to access memory and CPU registers. System state has been altered.  It is strongly advised that the processor should be reset before resuming execution,

Isn't it a sign that is something wrong with the C5505 device? It does not help repetitive CPU reset nor reloading the program. It helps to switch off and on the supply voltage.

Now I am not able to try another board but I will try it next week.

Regards,

Jiri

Hello,

Now I am able to induce the problem easily. When I start to read from NAND flash and to request for the data via USB from PC periodically and simultaneously the problem occurs in a short time (seconds). The buffers for these two operations are different. (The data are read from NAND flash to one buffer and the data for PC are in another buffer.) Requests for the data via USB are serviced successfuly also thereafter what the problem with reading the NAND flash occurs.

When I check the state of DMA controller (registers from address 0x0F00) I see that addresses are correct but the source address is always about 16 B greather from start address than the destination address (BURSTMODE is set to 4 = 64 B). The transfer length is 2112 B (DMACH1TCR1). The value of DMACH1TCR2 registr is 0xE020.

But there is problem with reading the EMIF registers. When I try to read registers from address 0x1000 or 0x1064 the debbuger writes this error message:

Trouble Reading Memory Block at 0x1064 on Page 2 of Length 0x40:
Error 0x80000002/-1143
Fatal Error during: Memory,
The memory at 0x000020CA continually indicated it was 'not ready'
All memory operations currently in progress were aborted in order
to regain control of the processor.
This is considered a catastrophic event, but the debugger should
still be able to access memory and CPU registers.
System state has been altered.  It is strongly advised
that the processor should be reset before resuming execution,

I am not able to read these registers even when i perform CPU reset. Is it the C5505 bug? How can the C5505 device get to this state?

Best regards,

Jiri

Hello,

I have evaluated this problem as a C5505 bug. My workaround is to set BURSTMODE = 0 = 4B (Transfer Control Register 2). With this setting it works fine.

Best regards,

Jiri