PROCESSOR-SDK-J784S4: Clarification on SerDES Loopback Configuration

Romain Guilloteau

Tool/software:

Hi,

We have identified a section in the TRM that mentions the SerDES can be configured in loopback mode: "Serial bit stream and parallel word loopback for both line and parallel side."

We need confirmation on the following:
1. If `CSL_SERDES_LOOPBACK_SER` is used to enable loopback, does it simulate the connection of the TX differential pair to the RX?
2. Does `CSL_SERDES_LOOPBACK_LINE` behave as if the input and output are connected on the peripheral side?

Thank you.

Best regards,
Romain

6 months ago

0 Chris Tsongas 6 months ago

TI__Genius 14420 points

Your question has been initially assigned to Shreyas

0 Romain Guilloteau 6 months ago in reply to Chris Tsongas

Prodigy 110 points

Hi,

I was wondering if anyone from the support team has had a chance to look into it or has any insights to share?

Thank you!

Best regards,
Romain

0 ShreyasRao 6 months ago in reply to Romain Guilloteau

TI__Guru 62060 points

Romain,

Sorry for the late reply during my OoO.

SERial loopback would be an internal TX to RX loopback.

0 ShreyasRao 6 months ago in reply to ShreyasRao

TI__Guru 62060 points

I have not done the Loopback_line so I am not sure what that would do, I will have to look into that.

0 ShreyasRao 5 months ago in reply to ShreyasRao

TI__Guru 62060 points

Line side loopback involves RX pins loopback to TX pins bypassing the Deserializer and Serializer.

The FarEnd loopback goes through the DeSer (RX side) and again through the Serializer (TX side) out on to the TX pins.

0 Romain Guilloteau 5 months ago in reply to ShreyasRao

Prodigy 110 points

Hi,

Thanks for your answers. I assume that the FarEND loopback corresponds to the SERial loopback or is it another type?

+1 ShreyasRao 5 months ago in reply to Romain Guilloteau

TI__Guru 62060 points

No, FarEnd loopback is different from Serial loopback.

While Serial loopback is from TX BIST to RX; Farend loopback involves an external connection into the RX pins and out onto the TX side.

0 Romain Guilloteau 5 months ago in reply to ShreyasRao

Prodigy 110 points

Thanks for your answer. I believe I understand now. To clarify the configuration, the SerDes loopback should be set to DISABLED mode since the loopback is realized externally for the FarEnd mode. Additionally, it appears that this configuration mode is not present in the code. Am I right?

typedef uint32_t CSL_SerdesLoopback;
#define CSL_SERDES_LOOPBACK_DISABLED (0U)
#define CSL_SERDES_LOOPBACK_LINE (1U)
#define CSL_SERDES_LOOPBACK_SER (2U)
#define CSL_SERDES_LOOPBACK_NEPAR (3U)
#define CSL_SERDES_LOOPBACK_FEPAR (4U)
#define CSL_SERDES_LOOPBACK_RECOVEREDCLOCK (5U)
#define CSL_SERDES_LOOPBACK_TXONLY (6U)
#define CSL_SERDES_LOOPBACK_PCS (7U)
#define CSL_SERDES_LOOPBACK_ISI (8U)
#define CSL_SERDES_LOOPBACK_TXONLY_LFPS (9U)

Best regards,

Romain

+1 ShreyasRao 5 months ago in reply to Romain Guilloteau

TI__Guru 62060 points

Romain,

FEPAR is FarEnd Parallel loopback mode to have it in the FarEnd mode.

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PROCESSOR-SDK-J784S4: Clarification on SerDES Loopback Configuration