For VDDS_DDR: we do not recommend using target impedance as the signoff for DDR.
Refer to the AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines which outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.

We only provide impedance targets for VDD_CORE. This information can be found under processor specific section "Example:AM62Ax" (starting on page 31) in the following document: www.ti.com/.../sprac76
As noted in the document, rails not listed are not simulated by TI due to low load transients. For more information, see the device-specific EVM layout for example implementation of these rails.
Other rails like the IOs are highly dependent on external peripherals. From the SoC perspective, if you look at the MAX current ratings for the IOs, the total current (after combining all the IOs of the same voltage) is still very low < 350mA so we don't simulate this rails/No data available.
Regarding your other questions related to PET, the supply names are not expected to match with processor (Example AM62A) pin names because the power estimates in the PET are itemized by supply groups. The power supply consolidation for these supply groups match the EVM.

AM62Lx Maximum Current Ratings

https://www.ti.com/lit/pdf/spradr4

SoC power architecture Application notes:

Application Note AM62L Power Supply Implementation

https://www.ti.com/lit/pdf/slvafw3

Power Distribution Networks: Implementation and Analysis

https://www.ti.com/lit/pdf/sprac76

Design Simulation files

https://www.ti.com/product/AM62L#design-tools-simulation

Simulation files provided includes IBIS, IBIS-AMI, BSDL, Thermal model and power-estimation tool (PET)

High Speed Board design and Signal integrity simulation

https://www.ti.com/lit/an/spracn9d/spracn9d.pdf

https://hands.com/~lkcl/ddr3/sprabi1a.pdf

https://www.ti.com/lit/an/spraar7i/spraar7i.pdf

SYSCONFIG

DDR subsystem register configuration tool

interactive and intuitive graphical tool for enabling, configuring and generating initialization code for device pin multiplexing

Technical Documents

Collaterals and app notes

https://www.ti.com/product/AM62L#tech-docs

Technical Support

AM62L Custom board design - FAQs

Previous E2E threads - Keywords AM62L

Starting a new thread

(2) TI E2E support forums

Useful links

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1478019/faq-am62l-custom-board-hardware-design---design-and-review-notes-for-reuse-of-evm-tmds62levm-schematics

(21) [FAQ] What is the difference between RMII slave signaling and RMII master signaling? - Interface forum - Interface - TI E2E support forums

SOC POH
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1492996/am620-q1-the-definition-of-power-of-hour-for-automotive-grade/5736233#5736233

Notes

Always ensure you are using the latest version of the documentation.
Check the product folder regularly for the latest version.
On Ti.com, device product folder page, there is a "Notifications" button. Registering here enables automatic notification of device document changes.
If you have any queries or need clarification, use E2E to find similar queries or ask a new question

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 1 year ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 228535 points

Hi Board designers,

Inputs regarding Package shelf life

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1520415/am625-package-shelf-life

Please refer below links

https://www.ti.com/support-quality/quality-policies-procedures/product-shelf-life.html

https://www.ti.com/support-quality/faqs/product-shelf-life-faqs.html

https://www.ti.com/packaging/docs/mslsearch.tsp?OPN=AM6254BTGFHIAMCRQ1&searchSelected=devpartno&searchkey=AM625#divline

https://www.ti.com/support-quality/reliability/reliability-home.html

https://www.ti.com/lit/an/spraby1a/spraby1a.pdf

https://www.ti.com/lit/pdf/snoa550

https://www.ti.com/lit/an/slva840/slva840.pdf

/cfs-file/__key/communityserver-discussions-components-files/791/Baking-Procedure.pdf

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 9 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 228535 points

Hi Board designers,

Inputs regarding weight and material content

https://www.ti.com/materialcontent/home

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 days ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 228535 points

Hi Board designers,

Inputs regarding maximum clamping force:

we have more updated guidance based on modelling that gives more resolution to pitch. Please see below:

• 0.65mmp/0.8mmp (like ALV)  19 g/solder ball
o 441/ALV  441 x 19g = 8379g

• 0.5mmp (like ALX)  13 g/solder ball
o 293/ALX  293 x 13g = 3809g

General Guidelines:

(+) AM2432: Maximum Allowable Value of Mechanical Pressure (Clamping Force) to the Top of Package (ALV) - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Could you tell them the maximum allowable value of pressure to the top of package ?
Do you have any document for design guide of heatsink and Thermal Interface Material ?

AM2432: Maximum Allowable Value of Mechanical Pressure (Clamping Force) to the Top of Package (ALV)

This is in our FCBGA app note (pg 52). It looks like TI’s recommendation is 0.015 lbf per BGA ball.

That same section has some details regarding heat sinks, but I’m not seeing anything too specific. Generally, the customer defines which TIM they should use as well as the design of the heat sink, so I think we can only give them pretty generic guidance.

The diagonals of some of these heat sinks can be designed with extensions to allow direct connection to the board. Back plates can reduce the bending
stress on the board. TI recommends keeping the compressive loading by a heat sink or other attachment below 0.015 lbfper BGA ball.
https://www.ti.com/lit/ug/spru811a/spru811a.pdf#page=52

Regards,

Sreenivasa

Processors

Processors forum

[FAQ] AM62L ( AM62L32 , AM62L31 ) Custom board hardware design – Collaterals to Get started