Tool/software:
Hi TI Experts,
Can you provide a List of collaterals that can be referred when starting a custom board hardware design.
Hi Board designers,
The below links are a quick reference to the collaterals that can be referred when starting a custom design.
Device Selection and features
Product Page
AM62L data sheet, product information and support | TI.com
Datasheet
AM62Lx Sitara Processors Data Sheet
https://www.ti.com/lit/pdf/sprspa1
Silicon Errata
AM62Lx Sitara Processors Silicon Errata
https://www.ti.com/lit/pdf/sprz582
Technical Reference Manual
AM62L Sitara Processors Technical Reference Manual
https://www.ti.com/lit/pdf/sprujb4
Escape Routing
AM62Lx Escape Routing for PCB Design
https://www.ti.com/lit/pdf/SPRADI2
Custom Board design
Hardware Design Considerations for AM62Lx
https://www.ti.com/lit/pdf/SPRUJC9
Schematic Review Checklist
AM62L32, AM62L31 Processor Family Schematic Design Guidelines and Schematic Review Checklist
https://www.ti.com/lit/pdf/sprado8
Hardware Design Considerations
Hardware Design Considerations for Custom Board Using AM62L32 and AM62L01 Processors
https://www.ti.com/lit/pdf/sprujc9
Evaluation EVM
TMDS62LEVM Evaluation board | TI.com
Design files package
Below are the details of the tool versions used for both E1 & E1-1 designs.
Schematic Entry - OrCAD Capture CIS 17.4
PCB Layout - Cadence Allegro 17.4 (Files will be downgraded to 17.2)
SysConfig (Pinmux) for TMDS62LEVM
EVM design files in Altium format
.ALG file : https://www.ti.com/lit/zip/sprcal6
See 3_BoardFile
Escape Routing PCB
Allegro file: Link provided in the document
CAD symbols
https://www.ti.com/product/AM62L#cad-cae-symbols
Ordering & quality
https://www.ti.com/product/AM62L#order-quality
Lead finish/Ball material
Package pad diameter and substrate pad dimension
DDR Board Design and Layout Guidelines
AM62x, AM62Lx DDR Board Design and Layout Guidelines
https://www.ti.com/lit/pdf/sprad06
Target impedance
Impedance target values for VDD_CORE on AM62L
We do not provide target impedance values for other rails on AM62x.
Note:
We do not include Buck output inductance in PDN simulations.
For VDDS_DDR: we do not recommend using target impedance as the signoff for DDR.
Refer to the AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines which outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.
AM62Lx Maximum Current Ratings
https://www.ti.com/lit/pdf/spradr4
SoC power architecture Application notes:
Application Note AM62L Power Supply Implementation
https://www.ti.com/lit/pdf/slvafw3
Power Distribution Networks: Implementation and Analysis
https://www.ti.com/lit/pdf/sprac76
Design Simulation files
https://www.ti.com/product/AM62L#design-tools-simulation
Simulation files provided includes IBIS, IBIS-AMI, BSDL, Thermal model and power-estimation tool (PET)
High Speed Board design and Signal integrity simulation
https://www.ti.com/lit/an/spracn9d/spracn9d.pdf
https://hands.com/~lkcl/ddr3/sprabi1a.pdf
https://www.ti.com/lit/an/spraar7i/spraar7i.pdf
SYSCONFIG
DDR subsystem register configuration tool
Technical Documents
Collaterals and app notes
https://www.ti.com/product/AM62L#tech-docs
Technical Support
AM62L Custom board design - FAQs
Previous E2E threads - Keywords AM62L
Starting a new thread
Useful links
Notes
Regards,
Sreenivasa
