Hi Board designers,
The below links are a quick reference to the collaterals that can be referred when starting a custom design.
Device Selection and features
Product Page
AM62L data sheet, product information and support | TI.com
Datasheet
AM62Lx Sitara Processors Data Sheet
https://www.ti.com/lit/pdf/sprspa1
Silicon Errata
AM62Lx Sitara Processors Silicon Errata
https://www.ti.com/lit/pdf/sprz582
Technical Reference Manual
AM62L Sitara Processors Technical Reference Manual
https://www.ti.com/lit/pdf/sprujb4
Escape Routing
AM62Lx Escape Routing for PCB Design
https://www.ti.com/lit/pdf/SPRADI2
Custom Board design
Hardware Design Considerations for AM62Lx
https://www.ti.com/lit/pdf/SPRUJC9
Schematic Review Checklist
AM62L32, AM62L31 Processor Family Schematic Design Guidelines and Schematic Review Checklist
https://www.ti.com/lit/pdf/sprado8
Hardware Design Considerations
Hardware Design Considerations for Custom Board Using AM62L32 and AM62L01 Processors
https://www.ti.com/lit/pdf/sprujc9
Evaluation EVM
TMDS62LEVM Evaluation board | TI.com
Design files package
https://www.ti.com/lit/zip/sprcal6
There seems to be a muxed GPMC interface implemented.
https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/TMDXICE3359_SCH.pdf
Below are the details of the tool versions used for both E1 & E1-1 designs.
Schematic Entry - OrCAD Capture CIS 17.4
PCB Layout - Cadence Allegro 17.4 (Files will be downgraded to 17.2)
SysConfig (Pinmux) for TMDS62LEVM
EVM design files in Altium format
.ALG file : https://www.ti.com/lit/zip/sprcal6
See 3_BoardFile
Escape Routing PCB
Allegro file: Link provided in the document
CAD symbols
https://www.ti.com/product/AM62L#cad-cae-symbols
Ordering & quality
https://www.ti.com/product/AM62L#order-quality
Lead finish/Ball material
Package pad diameter and substrate pad dimension
DDR Board Design and Layout Guidelines
AM62x, AM62Lx DDR Board Design and Layout Guidelines
https://www.ti.com/lit/pdf/sprad06
Target impedance
Impedance target values for VDD_CORE on AM62L
We do not provide target impedance values for other rails on AM62L
For frequencies above 50 MHz the board decoupling caps do not play a critical role. SoC and Package decaps (if any) will be dominant beyond 50 MHz
Note: We do not include Buck output inductance in PDN simulations.
For VDDS_DDR: we do not recommend using target impedance as the signoff for DDR.
Refer to the AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines which outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.
We only provide impedance targets for VDD_CORE. This information can be found under processor specific section "Example:AM62Ax" (starting on page 31) in the following document: www.ti.com/.../sprac76
As noted in the document, rails not listed are not simulated by TI due to low load transients. For more information, see the device-specific EVM layout for example implementation of these rails.
Other rails like the IOs are highly dependent on external peripherals. From the SoC perspective, if you look at the MAX current ratings for the IOs, the total current (after combining all the IOs of the same voltage) is still very low < 350mA so we don't simulate this rails/No data available.
Regarding your other questions related to PET, the supply names are not expected to match with processor (Example AM62A) pin names because the power estimates in the PET are itemized by supply groups. The power supply consolidation for these supply groups match the EVM.
AM62Lx Maximum Current Ratings
https://www.ti.com/lit/pdf/spradr4
SoC power architecture Application notes:
Application Note AM62L Power Supply Implementation
https://www.ti.com/lit/pdf/slvafw3
Power Distribution Networks: Implementation and Analysis
https://www.ti.com/lit/pdf/sprac76
Design Simulation files
https://www.ti.com/product/AM62L#design-tools-simulation
Simulation files provided includes IBIS, IBIS-AMI, BSDL, Thermal model and power-estimation tool (PET)
High Speed Board design and Signal integrity simulation
https://www.ti.com/lit/an/spracn9d/spracn9d.pdf
https://hands.com/~lkcl/ddr3/sprabi1a.pdf
https://www.ti.com/lit/an/spraar7i/spraar7i.pdf
SYSCONFIG
DDR subsystem register configuration tool
Technical Documents
Collaterals and app notes
https://www.ti.com/product/AM62L#tech-docs
Technical Support
AM62L Custom board design - FAQs
Previous E2E threads - Keywords AM62L
Starting a new thread
Useful links
Notes
Regards,
Sreenivasa
