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Original question:

DRA821U-Q1: DRA821U2-Q1: LPDDR4 Register configuration modification

DRA821U-Q1: LPDDR4 termination

Max Chen1
Intellectual 715 points
Part Number: DRA821U-Q1

Tool/software:

Hi,

we use Micron: MT53E2G32D4DE-046 AAT:C, as you can see Rank1 ODT_CA connected to VSS, which means no address lines termination?

We use this config: https://dev.ti.com/sysconfig/#/config/?args=--product%20%2Fmnt%2Ftirex-content%2FTDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.11.00.0000%2F.metadata%2Fproduct.json%20--device%20J7200_DRA821_SR1.0_alpha

seems works on our prototype boards:

I noticed that: 

Termination - SOC ODT : RZQ/5

Termination - CA ODT: RZQ/3

Termination - DQ ODT: RZQ/6

Q1:   why we have to set CA ODT not same as SOC ODT ?

I think we should set Both CA ODT and DQ ODT same as SOC ODT = RZQ/5 ==> 48 ohm.

See our schematic:

Q2: can you provide value of MR11 and MR22 registers for each memory channel (A, B)?

Q3: SOC LPDDR4 driver is capable of 40 ohm / 60 ohm with 120 ohm pull-down?

Q4: Rank0 , CLK/CS/CA ODT termination enabled ?

Q5: Rank1, CLK/CS/CA ODT termination disabled ?

thanks

Max

  • 0
    TI__Mastermind 38510 points

    Max,

    Max Chen1 said:
    we use Micron: MT53E2G32D4DE-046 AAT:C, as you can see Rank1 ODT_CA connected to VSS, which means no address lines termination?

    No, Rank 1 ODT_CA connected to VSS does NOT imply no address line termination. Please refer to section "ODT Mode Register and ODT State Table" on page 272 of the corresponding datasheet (rev G  sept. 2024), which states:

    "The CA ODT of the device is designed to enable one rank to terminate the entire command bus in a multirank system, so only one termination load will be present even if multiple devices are sharing the command signals."

    Max Chen1 said:
    Q1:   why we have to set CA ODT not same as SOC ODT ?

    SOC ODT is controlling the ODT on TDA4 for the DQ/DQS IO during READs (inputs to TDA4)

    CA ODT is controlling the ODT on the LPDDR4 for the CA/CS/CLK IO.

    Note that we provide customers the option to modify IO parameters through our register configuration tool and we do not force you to set them any particular way. 

    You may benefit from reading the following E2E thread which discusses CA ODT: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1466721/tda4vm-q1-tda4vm-lpddr4-sysconfig-and-impedance-matching-issues/ 

    Max Chen1 said:
    Q2: can you provide value of MR11 and MR22 registers for each memory channel (A, B)?

    MR11 and MR22 are entirely configurable through the register configuration tool under the section "IOControl B) DRAM IO Configuration".

    MR11 would be set by settings:

    • Termination - CA ODT
    • Termination - DQ ODT

    MR22 would be set by settings:

    • Termination - CA ODT Disable
    • Termination - CK ODT Override
    • Termination - CS ODT Override
    • Termination - SOC ODT

    Settings of channel A and B are set the same.

    Max Chen1 said:
    Q3: SOC LPDDR4 driver is capable of 40 ohm / 60 ohm with 120 ohm pull-down?

    Not sure what is being asked here. Available drive strength settings are provided as drop-down options in the register configuration tool under section "IOControl A) Processor/DDR Controller IO Configuration". 

    Max Chen1 said:

    Q4: Rank0 , CLK/CS/CA ODT termination enabled ?

    Q5: Rank1, CLK/CS/CA ODT termination disabled ?

    As mentioned above,

    • Termination settings are configurable through the register configuration tool. 
    • I recommend you read section "ODT Mode Register and ODT State Table" of the memory datasheet.

    Regards,
    Kevin