TDA4VM-Q1: Using cpsw9g in mcu20 failed

From 26afd2ff3d2674c33195e5d6e5ba20b83661a564 Mon Sep 17 00:00:00 2001
From: zhangweizhen <zhangweizhen@mit.cn>
Date: Fri, 28 Feb 2025 15:40:56 +0800
Subject: [PATCH] using cpsw9g on mcu20

Change-Id: I0e6f2df0fa8d5e8521d3a2308bce0055436e54d6
---
 .../utils/board/src/j721e/board_j721e_evm.c   |  30 +--
 .../board/src/j721e_evm/J721E_pinmux_data.c   |   2 +
 .../j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c | 152 +++++++++++-
 .../src/j721e_evm/board_ethernet_config.c     |   7 +-
 .../packages/ti/drv/enet/enet_cfg.h           |   2 +-
 .../ti/drv/enet/include/phy/tja1101.h         | 104 +++++++++
 .../ti/drv/enet/soc/j7x/j721e/enet_soc.c      |   2 +-
 .../packages/ti/drv/enet/src/phy/enetphy.c    |  22 +-
 .../packages/ti/drv/enet/src/phy/makefile     |   2 +-
 .../packages/ti/drv/enet/src/phy/tja1101.c    | 221 ++++++++++++++++++
 .../ti/drv/enet/src/phy/tja1101_priv.h        |  94 ++++++++
 .../utils/ethfw/src/app_ethfw_freertos.c      | 105 +--------
 .../vision_apps/utils/ethfw/src/concerto.mak  |   2 +-
 13 files changed, 606 insertions(+), 139 deletions(-)
 create mode 100755 psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/include/phy/tja1101.h
 create mode 100755 psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/tja1101.c
 create mode 100755 psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/tja1101_priv.h

diff --git a/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c b/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c
index 8b4c01a2e..8284cd6db 100644
--- a/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c
+++ b/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c
@@ -200,8 +200,8 @@ extern pinmuxBoardCfg_t gEthFwPinmuxData[];
 /* GPIO Driver board specific pin configuration structure */
 GPIO_PinConfig gEthFw_gpioPinCfgs[] =
 {
-    GPIO_DEVICE_CONFIG(0, 61) | GPIO_CFG_OUTPUT,
-    GPIO_DEVICE_CONFIG(0, 62) | GPIO_CFG_OUTPUT,
+    GPIO_DEVICE_CONFIG(0, 41) | GPIO_CFG_OUTPUT,
+    GPIO_DEVICE_CONFIG(0, 44) | GPIO_CFG_OUTPUT,
 };
 
 /* GPIO Driver callback functions */
@@ -244,6 +244,7 @@ static const Dp83867_Cfg gEnetGesiBoard_dp83867PhyCfg =
 /* 4 x RGMII ports in GESI expansion board */
 static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] =
 {
+#if 0
     {   /* "PRG1_RGMII1_B" */
         .macPort   = ENET_MAC_PORT_1,
         .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
@@ -286,19 +287,22 @@ static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] =
         .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
         .linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
     },
+#endif
     {   /* "PRG0_RGMII02_T" */
-        .macPort   = ENET_MAC_PORT_4,
-        .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
+        .macPort   = ENET_MAC_PORT_1,
+        .mii       = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_REDUCED },
         .phyCfg    =
         {
-            .phyAddr         = 3U,
-            .isStrapped      = BFALSE,
-            .skipExtendedCfg = BFALSE,
-            .extendedCfg     = &gEnetGesiBoard_dp83867PhyCfg,
-            .extendedCfgSize = sizeof(gEnetGesiBoard_dp83867PhyCfg),
+            .phyAddr         = 4U,
+            .isStrapped      = false,
+            .skipExtendedCfg = false,
+            //.extendedCfg     = &gEnetGesiBoard_dp83867PhyCfg,
+            //.extendedCfgSize = sizeof(gEnetGesiBoard_dp83867PhyCfg),
+            .extendedCfg     = NULL,
+            .extendedCfgSize = 0U,
         },
-        .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
-        .linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
+        //.sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
+		.linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
     },
 };
 
@@ -599,7 +603,7 @@ static void EthFwBoard_configPinmux(void)
     Board_pinmuxUpdate(gEthFwPinmuxData, BOARD_SOC_DOMAIN_MAIN);
 
     /* Configure pinmux settings for Ethernet ports and MDIO */
-    Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9gQsgmii, BOARD_SOC_DOMAIN_MAIN);
+    Board_pinmuxUpdate( gJ721E_MainPinmuxDataGesiCpsw9g, BOARD_SOC_DOMAIN_MAIN);
 
     /* REVISIT - Configure CPSW9G pins for ports on the GESI board */
     Board_pinmuxGetCfg(&pinmuxCfg);
@@ -622,7 +626,7 @@ static void EthFwBoard_detectDBs(void)
     {
         /* Assume expansion boards are present if detection not allowed */
         gEthFwBoard.gesiDetected  = BTRUE;
-        gEthFwBoard.qenetDetected = BTRUE;
+        gEthFwBoard.qenetDetected = BFALSE;
     }
 }
 
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c
index 2a71fc5f9..2389bf1cc 100755
--- a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c
@@ -460,6 +460,7 @@ static pinmuxPerCfg_t gMcu_fss0_ospi0PinCfg[] =
     {PINMUX_END}
 };
 /*
+#if 0
 static pinmuxPerCfg_t gMcu_fss0_ospi1PinCfg[] =
 {
     // MyMCU_OSPI1 -> MCU_OSPI1_CLK -> F22
@@ -504,6 +505,7 @@ static pinmuxPerCfg_t gMcu_fss0_ospi1PinCfg[] =
     },
     {PINMUX_END}
 };
+#endif
 */
 static pinmuxModuleCfg_t gMcu_fss0_ospiPinCfg[] =
 {
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
index 4c6062269..50a5d46e6 100755
--- a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
@@ -39,14 +39,15 @@ static pinmuxModuleCfg_t gCpsw9gPinCfg[] =
 
 static pinmuxPerCfg_t gGpio0PinCfg[] =
 {
-    /* MyGPIO0 -> GPIO0_96 -> T23 */
+    /* MyGPIO1 -> GPIO0_41 -> AD19 */
     {
-        PIN_RGMII5_RD0, PIN_MODE(7) | \
+        PIN_PRG1_MDIO0_MDIO, PIN_MODE(7) | \
         ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
     },
-    /* MyGPIO0 -> GPIO0_104 -> W26 */
+
+	/* MyGPIO1 -> GPIO0_44 -> AE28 */
     {
-        PIN_RGMII6_RXC, PIN_MODE(7) | \
+        PIN_PRG0_PRU0_GPO1, PIN_MODE(7) | \
         ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
     },
     {PINMUX_END}
@@ -154,6 +155,125 @@ static pinmuxPerCfg_t gRgmii3PinCfg[] =
     {PINMUX_END}
 };
 
+static pinmuxPerCfg_t gRmii1PinCfg[] =
+{
+    /* MyRMII1 -> RMII1_CRS_DV -> AF22 */
+    {
+        PIN_PRG1_PRU0_GPO2, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRMII1 -> RMII1_RXD0 -> AC23 */
+    {
+        PIN_PRG1_PRU0_GPO0, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRMII1 -> RMII1_RXD1 -> AG22 */
+    {
+        PIN_PRG1_PRU0_GPO1, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRMII1 -> RMII1_RX_ER -> AJ23 */
+    {
+        PIN_PRG1_PRU0_GPO3, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRMII1 -> RMII1_TXD0 -> AH23 */
+    {
+        PIN_PRG1_PRU0_GPO4, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyRMII1 -> RMII1_TXD1 -> AD22 */
+    {
+        PIN_PRG1_PRU0_GPO6, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyRMII1 -> RMII1_TX_EN -> AD20 */
+    {
+        PIN_PRG1_PRU0_GPO5, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+
+    {
+        PIN_PRG1_MDIO0_MDC, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+
+    {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gRmii4PinCfg[] =
+{
+    /* MyRMII1 -> RMII4_CRS_DV -> AD27 */
+    {
+        PIN_PRG0_PRU1_GPO2, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRMII1 -> RMII4_RXD0 -> AE29 */
+    {
+        PIN_PRG0_PRU1_GPO0, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRMII1 -> RMII4_RXD1 -> AD28 */
+    {
+        PIN_PRG0_PRU1_GPO1, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRMII1 -> RMII4_RX_ER -> AC25 */
+    {
+        PIN_PRG0_PRU1_GPO3, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRMII1 -> RMII4_TXD0 -> AC26 */
+    {
+        PIN_PRG0_PRU1_GPO6, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyRMII1 -> RMII4_TXD1 -> AD29 */
+    {
+        PIN_PRG0_PRU1_GPO4, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyRMII1 -> RMII4_TX_EN -> AG26 */
+    {
+        PIN_PRG0_PRU1_GPO11, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+
+
+    {
+        PIN_PRG1_MDIO0_MDC, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+
+
+    /* MyRGMII4 -> RGMII4_TD1 -> AF27 */
+    /*{
+        PIN_PRG0_PRU1_GPO12, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },*/
+    /* MyRGMII4 -> RGMII4_TD2 -> AF26 */
+    /*{
+        PIN_PRG0_PRU1_GPO13, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },*/
+    /* MyRGMII4 -> RGMII4_TD3 -> AE25 */
+    /*{
+        PIN_PRG0_PRU1_GPO14, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },*/
+    /* MyRGMII4 -> RGMII4_TXC -> AG29 */
+    /*{
+        PIN_PRG0_PRU1_GPO16, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },*/
+    /* MyRGMII4 -> RGMII4_TX_CTL -> AF29 */
+    /*{
+        PIN_PRG0_PRU1_GPO15, PIN_MODE(5) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },*/
+    {PINMUX_END}
+};
+
 static pinmuxPerCfg_t gRgmii4PinCfg[] =
 {
     /* MyRGMII4 -> RGMII4_RD0 -> AE29 */
@@ -481,12 +601,21 @@ static pinmuxPerCfg_t gRgmii8PinCfg[] =
     {PINMUX_END}
 };
 
-static pinmuxModuleCfg_t gRgmiiPinCfg[] =
+/*static pinmuxModuleCfg_t gRgmiiPinCfg[] =
 {
-    {3, 1, gRgmii3PinCfg},
-    {4, 1, gRgmii4PinCfg},
-    {1, 1, gRgmii1PinCfg},
-    {2, 1, gRgmii2PinCfg},
+    {3, TRUE, gRgmii3PinCfg},
+    {4, TRUE, gRgmii4PinCfg},
+    {1, TRUE, gRgmii1PinCfg},
+    {2, TRUE, gRgmii2PinCfg},
+    {PINMUX_END}
+};*/
+
+static pinmuxModuleCfg_t g_MtRgmiiPinCfg[] =
+{
+    {3, 0, gRgmii3PinCfg},
+    {4, 0, gRmii4PinCfg},
+    {1, 1, gRmii1PinCfg},
+    {2, 0, gRgmii2PinCfg},
     {PINMUX_END}
 };
 
@@ -573,8 +702,9 @@ pinmuxBoardCfg_t gJ721E_MainPinmuxDataGesiCpsw9g[] =
     {0, gCpsw9gPinCfg},
     {1, gGpioPinCfg},
     {2, gMdioPinCfg},
-    {3, gRgmiiPinCfg},
-    {4, gRmiiPinCfg},
+    /*{3, gRgmiiPinCfg},*/
+    {3, g_MtRgmiiPinCfg},
+    /*{4, gRmiiPinCfg},*/
     {PINMUX_END}
 };
 
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/board_ethernet_config.c b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/board_ethernet_config.c
index 5d513ea49..eedd0a767 100755
--- a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/board_ethernet_config.c
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/board/src/j721e_evm/board_ethernet_config.c
@@ -745,12 +745,9 @@ Board_STATUS Board_ethConfigCpsw9g(void)
     /* Configures the CPSW9G RGMII ports */
     for(portNum = 0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
     {
-        if ( (0U == portNum) ||
-             (2U == portNum) ||
-             (3U == portNum) ||
-             (7U == portNum) )
+        if ( 0U == portNum )
         {
-            status = Board_cpsw9gEthConfig(portNum, RGMII);
+            status = Board_cpsw9gEthConfig(portNum, RMII);
         }
         else
         {
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/enet_cfg.h b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/enet_cfg.h
index e007b849e..730e14ead 100644
--- a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/enet_cfg.h
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/enet_cfg.h
@@ -89,7 +89,7 @@ extern "C" {
 /* --------------------------------------------------------------------------*/
 
 /*! \brief CPSW Q/SGMII support (requires #ENET_CFG_CPSW_MACPORT_SGMII). */
-#define ENET_CFG_CPSW_SGMII                         (ENET_ON)
+//#define ENET_CFG_CPSW_SGMII                         (ENET_ON)
 
 /*! \brief CPSW interVLAN support support (requires #ENET_CFG_CPSW_MACPORT_INTERVLAN). */
 #define ENET_CFG_CPSW_INTERVLAN                     (ENET_ON)
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/include/phy/tja1101.h b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/include/phy/tja1101.h
new file mode 100755
index 000000000..44aa8273b
--- /dev/null
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/include/phy/tja1101.h
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * \file  tja1101.h
+ *
+ * \brief This file contains the type definitions and helper macros for the
+ *        TJA1101 Ethernet PHY.
+ */
+
+/*!
+ * \ingroup  DRV_ENETPHY
+ * \defgroup ENETPHY_TJA1101 TI TJA1101 PHY
+ *
+ * TI TJA1101 RMII Ethernet PHY.
+ *
+ * @{
+ */
+
+#ifndef TJA1101_H_
+#define TJA1101_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                                 Macros                                     */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Structures and Enums                               */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Global Variables Declarations                      */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                        Deprecated Function Declarations                    */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                       Static Function Definitions                          */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TJA1101_H_ */
+
+/* @} */
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c
index 67d934d35..771a0d1fc 100644
--- a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c
@@ -1184,7 +1184,7 @@ int32_t EnetSoc_getMacPortMii(Enet_Type enetType,
 {
     EnetMac_LayerType *enetLayer = &mii->layerType;
     EnetMac_SublayerType *enetSublayer = &mii->sublayerType;
-    uint32_t modeSel = CPSW_ENET_CTRL_MODE_RGMII;
+    uint32_t modeSel = CPSW_ENET_CTRL_MODE_RMII;
     int32_t status = ENET_EFAIL;
 
     switch (enetType)
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/enetphy.c b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/enetphy.c
index 6a6baddad..c8c2520a6 100644
--- a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/enetphy.c
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/enetphy.c
@@ -188,6 +188,7 @@ extern EnetPhy_Drv gEnetPhyDrvGeneric;
 extern EnetPhy_Drv gEnetPhyDrvDp83822;
 extern EnetPhy_Drv gEnetPhyDrvDp83867;
 extern EnetPhy_Drv gEnetPhyDrvVsc8514;
+extern EnetPhy_Drv gEnetPhyDrvTja1101;
 
 /*! \brief All the registered PHY specific drivers. */
 static EnetPhyDrv_Handle gEnetPhyDrvs[] =
@@ -195,6 +196,7 @@ static EnetPhyDrv_Handle gEnetPhyDrvs[] =
     &gEnetPhyDrvVsc8514,   /* VSC8514 */
     &gEnetPhyDrvDp83822,   /* DP83822 */
     &gEnetPhyDrvDp83867,   /* DP83867 */
+    &gEnetPhyDrvTja1101,   /*TJA1101 */
     &gEnetPhyDrvGeneric,   /* Generic PHY - must be last */
 };
 
@@ -964,9 +966,18 @@ static void EnetPhy_initState(EnetPhy_Handle hPhy)
 {
     EnetPhy_State *state = &hPhy->state;
 
-    state->speed = ENETPHY_SPEED_10MBIT;
-    state->duplexity = ENETPHY_DUPLEX_HALF;
-    state->phyLinkCaps = 0U;
+	if(hPhy->addr == 4)
+	{
+		state->speed = ENETPHY_SPEED_100MBIT;
+		state->duplexity = ENETPHY_DUPLEX_FULL;
+		state->phyLinkCaps = 0U;
+	}
+	else
+	{
+		state->speed = ENETPHY_SPEED_10MBIT;
+		state->duplexity = ENETPHY_DUPLEX_HALF;
+		state->phyLinkCaps = 0U;
+	}
 
     if (hPhy->phyCfg.isStrapped)
     {
@@ -1125,7 +1136,10 @@ static void EnetPhy_enableState(EnetPhy_Handle hPhy)
         ENETTRACE_DBG("PHY %u: req caps: %s",
                       hPhy->addr, EnetPhy_getCapsString(hPhy->reqLinkCaps));
 
-        status = EnetPhy_getLocalCaps(hPhy, &state->phyLinkCaps);
+		if(hPhy->addr == 4)
+			state->phyLinkCaps =  ENETPHY_LINK_CAP_FD100;
+		else
+        	status = EnetPhy_getLocalCaps(hPhy, &state->phyLinkCaps);
     }
 
     if (status == ENETPHY_SOK)
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/makefile b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/makefile
index f4c3b7233..f6715cfb2 100644
--- a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/makefile
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/makefile
@@ -19,7 +19,7 @@ INCLUDE_INTERNAL_INTERFACES =
 
 # Common source files and CFLAGS across all platforms and cores
 SRCS_COMMON += enetphy.c generic_phy.c
-SRCS_COMMON += dp83867.c dp83822.c vsc8514.c
+SRCS_COMMON += dp83867.c dp83822.c vsc8514.c tja1101.c
 
 PACKAGE_SRCS_COMMON = $(SRCDIR)
 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(ENET_CFLAGS)
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/tja1101.c b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/tja1101.c
new file mode 100755
index 000000000..45353f9b1
--- /dev/null
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/tja1101.c
@@ -0,0 +1,221 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * \file  tja1101.c
+ *
+ * \brief This file contains the implementation of the TJA1101 PHY.
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <stdint.h>
+#include <ti/drv/enet/include/core/enet_utils.h>
+#include <ti/drv/enet/priv/core/enet_trace_priv.h>
+#include <ti/drv/enet/include/phy/enetphy.h>
+#include <ti/drv/enet/include/phy/tja1101.h>
+#include "enetphy_priv.h"
+#include "generic_phy.h"
+#include "tja1101_priv.h"
+
+//extern void EthFwBoard_configGesi(void);
+bool static isResetDone = false;
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+#define TJA1101_OUI                           (0x6037U)
+#define TJA1101_MODEL                         (0x10U)
+#define TJA1101_REV                           (0x2U)
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+static bool Tja1101_isPhyDevSupported(EnetPhy_Handle hPhy,
+                                      const EnetPhy_Version *version);
+
+static bool Tja1101_isMacModeSupported(EnetPhy_Handle hPhy,
+                                       EnetPhy_Mii mii);
+
+static int32_t Tja1101_config(EnetPhy_Handle hPhy,
+                              const EnetPhy_Cfg *cfg,
+                              EnetPhy_Mii mii);
+
+void Tja1101_reset(EnetPhy_Handle hPhy);
+
+bool Tja1101_isResetComplete(EnetPhy_Handle hPhy);
+
+static void Tja1101_printRegs(EnetPhy_Handle hPhy);
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+EnetPhy_Drv gEnetPhyDrvTja1101 =
+{
+    .name               = "tja1101",
+    .isPhyDevSupported  = Tja1101_isPhyDevSupported,
+    .isMacModeSupported = Tja1101_isMacModeSupported,
+    .config             = Tja1101_config,
+    .reset              = Tja1101_reset,
+    .isResetComplete    = Tja1101_isResetComplete,
+    .readExtReg         = GenericPhy_readExtReg,
+    .writeExtReg        = GenericPhy_writeExtReg,
+    .printRegs          = Tja1101_printRegs,
+};
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+
+static bool Tja1101_isPhyDevSupported(EnetPhy_Handle hPhy,
+                                      const EnetPhy_Version *version)
+{
+    bool supported = false;
+
+    if ((version->oui == TJA1101_OUI) &&
+        (version->model == TJA1101_MODEL) &&
+        (version->revision == TJA1101_REV))
+    {
+        supported = true;
+    }
+
+    return supported;
+}
+
+static bool Tja1101_isMacModeSupported(EnetPhy_Handle hPhy,
+                                       EnetPhy_Mii mii)
+{
+    bool supported;
+
+    switch (mii)
+    {
+        case ENETPHY_MAC_MII_RMII:
+            supported = true;
+            break;
+
+        /* This driver doesn't support MII and RGMII interfaces,
+         * but the TJA1101 PHY does support them */
+        case ENETPHY_MAC_MII_MII:
+        case ENETPHY_MAC_MII_RGMII:
+        default:
+            supported = false;
+            break;
+    }
+
+    return supported;
+}
+
+static int32_t Tja1101_config(EnetPhy_Handle hPhy,
+                              const EnetPhy_Cfg *cfg,
+                              EnetPhy_Mii mii)
+{
+	//uint16_t i;
+    int32_t status = ENETPHY_SOK;
+	uint16_t val;
+
+#if 1
+	if(hPhy->addr == 4)
+    {
+    	/* enable the register RW */
+        EnetPhy_writeReg(hPhy, 17, 0x9804);
+		
+    	/* RMII mode enabled (50 MHz input on REF_CLK) */
+        EnetPhy_writeReg(hPhy, 18, 0xDE05);
+
+		/* 50 MHz input at REF_CLK; RMII mode only; no XTAL; no clock at CLK_IN_OUT */
+		EnetPhy_readReg(hPhy, 27, &val);
+		val &= ~(3 << 12);
+        EnetPhy_writeReg(hPhy, 27, val);
+    }
+#else
+	// not do anything
+#endif
+	/*if( hPhy->addr == 4 )
+	{
+		for(i = 0; i <= 28; i++)
+		{
+			EnetPhy_readReg(hPhy, i, &val);
+			[>ENETTRACE_DBG("PHY %u: register%u	  = 0x%04x\n", hPhy->addr, i, val);<]
+			EnetUtils_printf("PHY %u: register%u	  = 0x%04x\n", hPhy->addr, i, val);
+		}
+	}*/
+
+	return status;
+}
+
+void Tja1101_reset(EnetPhy_Handle hPhy)
+{
+	ENETTRACE_DBG("PHY %u: reset\n", hPhy->addr);
+	//EthFwBoard_configGesi();
+	EnetPhy_writeReg(hPhy, 17, 0x9804);
+	/* Reset the PHY */
+	EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_RESET, BMCR_RESET);
+	isResetDone = true;		
+}
+
+bool Tja1101_isResetComplete(EnetPhy_Handle hPhy)
+{
+    bool complete = false;
+
+	if(isResetDone)
+	{
+		ENETTRACE_DBG("PHY %u: reset is %scomplete\n", hPhy->addr, complete ? "" : "not");
+		isResetDone = false;
+		return true;
+	}
+	else
+		return complete;
+}
+
+static void Tja1101_printRegs(EnetPhy_Handle hPhy)
+{
+    uint32_t phyAddr = hPhy->addr;
+    uint16_t val = 0;
+    EnetPhy_readReg(hPhy, PHY_BMCR, &val);
+    EnetUtils_printf("PHY %u: BMCR    = 0x%04x\n", phyAddr, val);
+    EnetPhy_readReg(hPhy, PHY_BMSR, &val);
+    EnetUtils_printf("PHY %u: BMSR    = 0x%04x\n", phyAddr, val);
+    EnetPhy_readReg(hPhy, PHY_PHYIDR1, &val);
+    EnetUtils_printf("PHY %u: PHYIDR1 = 0x%04x\n", phyAddr, val);
+    EnetPhy_readReg(hPhy, PHY_PHYIDR2, &val);
+    EnetUtils_printf("PHY %u: PHYIDR2 = 0x%04x\n", phyAddr, val);
+}
diff --git a/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/tja1101_priv.h b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/tja1101_priv.h
new file mode 100755
index 000000000..ab504a589
--- /dev/null
+++ b/psdkra/pdk_jacinto_10_01_00_25/packages/ti/drv/enet/src/phy/tja1101_priv.h
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * \file  tja1101_priv.h
+ *
+ * \brief This file contains private type definitions and helper macros for the
+ *        TJA1101 Ethernet PHY.
+ */
+
+#ifndef TJA1101_PRIV_H_
+#define TJA1101_PRIV_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <stdint.h>
+#include "enetphy_priv.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                                 Macros                                     */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Structures and Enums                               */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Global Variables Declarations                      */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                        Deprecated Function Declarations                    */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                       Static Function Definitions                          */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TJA1101_PRIV_H_ */
diff --git a/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c b/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
index 063774c59..210e25868 100644
--- a/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
+++ b/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
@@ -166,9 +166,6 @@ static Enet_MacPort gEthAppPorts[] =
     /* On J721E EVM to use all 8 ports simultaneously, we use below configuration
        RGMII Ports - 1,3,4,8. QSGMII ports - 2,5,6,7 */
     ENET_MAC_PORT_1, /* RGMII */
-    ENET_MAC_PORT_3, /* RGMII */
-    ENET_MAC_PORT_4, /* RGMII */
-    ENET_MAC_PORT_8, /* RGMII */
 #if defined(ENABLE_QSGMII_PORTS)
     ENET_MAC_PORT_2, /* QSGMII main */
     ENET_MAC_PORT_5, /* QSGMII sub */
@@ -210,104 +207,8 @@ static CpswAle_SetPolicerEntryInPartitionInArgs gEthApp_customPolicers[ETHFW_UTI
 static EthFwVirtPort_VirtPortCfg gEthApp_virtPortCfg[] =
 {
     {
-        .remoteCoreId  = IPC_MPU1_0,
-        .portId        = ETHREMOTECFG_SWITCH_PORT_0,
-#if defined(ETHFW_EST_DEMO_SUPPORT) || defined(ETHFW_DEMO_SUPPORT)
-        .numTxCh       = 1U,
-        .txCh          = {
-                            [0] = ENET_RM_TX_CH_4
-                         },
-#else
-         .numTxCh      = 2U,
-         .txCh         = {
-                            [0] = ENET_RM_TX_CH_4,
-                            [1] = ENET_RM_TX_CH_7
-                         },
-#endif
-        /* Number of rx flow for this virtual port */
-        .numRxFlow     = 1U,
-        /* To create custom policers on rx flows clients need to give flow information (i.e. numCustomPolicers and customPolicersInArgs)
-         * for each allocated flow.
-         * Map the customPolicersInArgs with global custom policer's (i.e. gEthApp_customPolicers) array.
-         * For example if numRxFlow is 1 and we want to create 1 custom policer to match with 2'nd custom policer in global array do this: 
-         * .rxFlowsInfo = {  
-         *                  [0] = {
-         *                           .numCustomPolicers    = 1U,
-         *                           .customPolicersInArgs = {
-         *                                                       [0] = &gEthApp_customPolicers[2U],
-         *                                                   }
-         *                         }
-         *               }
-         * It is important to note that number of custom policers per rx flow is <= ETHREMOTECFG_POLICER_PERFLOW */
-        .numMacAddress = 1U,
-        .clientIdMask  = ETHFW_BIT(ETHREMOTECFG_CLIENTID_LINUX) | ETHFW_BIT(ETHREMOTECFG_CLIENTID_QNX),
-    },
-    {
-        .remoteCoreId  = IPC_MCU1_0,
-        .portId        = ETHREMOTECFG_SWITCH_PORT_2,
-        .numTxCh       = 1U,
-        .txCh          = {
-                            [0] = ENET_RM_TX_CH_5,
-                         },
-        .numRxFlow     = 1U,
-        .numMacAddress = 1U,
-        .clientIdMask  = ETHFW_BIT(ETHREMOTECFG_CLIENTID_AUTOSAR),
-    },
-    {
-        /* Virtual switch port for Ethfw, using ETHREMOTECFG_SWITCH_PORT_LAST */
-        .remoteCoreId  = IPC_MCU2_0,
-        .portId        = ETHREMOTECFG_SWITCH_PORT_LAST,
-#if defined(ETHFW_EST_DEMO_SUPPORT) || defined(ETHFW_DEMO_SUPPORT)
-        .numTxCh       = 3U,
-        .txCh          = {
-                            [0] = ENET_RM_TX_CH_0,
-                            [1] = ENET_RM_TX_CH_7,
-                            [2] = ENET_RM_TX_CH_6
-                         },
-#else
-        .numTxCh       = 2U,
-        .txCh          = {
-                            [0] = ENET_RM_TX_CH_0,
-                            [1] = ENET_RM_TX_CH_6
-                         },
-#endif
-        .numRxFlow     = 5U,
-        .numMacAddress = 1U,
-        .clientIdMask  = ETHFW_BIT(ETHREMOTECFG_CLIENTID_NONE),
-    },
-    {
-        /* SWITCH_PORT_1 is used for both RTOS and Autosar client */
-        .remoteCoreId  = IPC_MCU2_1,
-        .portId        = ETHREMOTECFG_SWITCH_PORT_1,
-        .numTxCh       = 1U,
-        .txCh          = {
-                            [0] = ENET_RM_TX_CH_1
-                         },
-        .numRxFlow     = 1U,
-        .numMacAddress = 1U,
-        .clientIdMask  = ETHFW_BIT(ETHREMOTECFG_CLIENTID_AUTOSAR) | ETHFW_BIT(ETHREMOTECFG_CLIENTID_RTOS),
-    },
-    {
-        .remoteCoreId  = IPC_MPU1_0,
-        .portId        = ETHREMOTECFG_MAC_PORT_1,
-        .numTxCh       = 1U,
-        .txCh          = {
-                            [0] = ENET_RM_TX_CH_3
-                         },
-        .numRxFlow     = 1U,
-        .numMacAddress = 1U,
-        .clientIdMask  = ETHFW_BIT(ETHREMOTECFG_CLIENTID_LINUX) | ETHFW_BIT(ETHREMOTECFG_CLIENTID_QNX),
-    },
-    {
-        .remoteCoreId  = IPC_MCU2_1,
-        .portId        = ETHREMOTECFG_MAC_PORT_4,
-        .numTxCh       = 1U,
-        .txCh          = {
-                            [0] = ENET_RM_TX_CH_2
-                         },
-        .numRxFlow     = 1U,
-        .numMacAddress = 1U,
-        .clientIdMask  = ETHFW_BIT(ETHREMOTECFG_CLIENTID_RTOS),
+        .remoteCoreId = IPC_MPU1_0,
+		.portId       = ETHREMOTECFG_MAC_PORT_1,
     },
 };
 
@@ -990,7 +891,7 @@ static void EthApp_netifStatusCb(struct netif *netif)
 
         appLogPrintf("Added interface '%c%c%d', IP is %s\n",
                      netif->name[0], netif->name[1], netif->num, ip4addr_ntoa(ipAddr));
-
+		appLogPrintf("ipaddr->addr=%d\n",ipAddr->addr);
         if (ipAddr->addr != 0)
         {
 #if defined(ETHFW_DEMO_SUPPORT)
diff --git a/psdkra/vision_apps/utils/ethfw/src/concerto.mak b/psdkra/vision_apps/utils/ethfw/src/concerto.mak
index 9ba7f90ad..901d80e7c 100644
--- a/psdkra/vision_apps/utils/ethfw/src/concerto.mak
+++ b/psdkra/vision_apps/utils/ethfw/src/concerto.mak
@@ -64,7 +64,7 @@ ifeq ($(TARGET_OS),$(filter $(TARGET_OS),FREERTOS SAFERTOS))
   else ifeq ($(ETHFW_INTERCORE_ETH_SUPPORT),yes)
     DEFS += ETHAPP_ENABLE_INTERCORE_ETH
   endif
-  DEFS += ENABLE_QSGMII_PORTS
+  #DEFS += ENABLE_QSGMII_PORTS
 endif
 
 # iperf server support
-- 
2.34.1

root@j721e-evm:~# /opt/vx_app_arm_remote_log.out |grep MCU2_0
[MCU2_0]     10.362329 s: CIO: Init ... Done !!!
[MCU2_0]     10.362401 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]     10.362446 s: CPU is running FreeRTOS
[MCU2_0]     10.362474 s: APP: Init ... !!!
[MCU2_0]     10.362501 s: SCICLIENT: Init ... !!!
[MCU2_0]     10.362714 s: SCICLIENT: DMSC FW version [10.1.6--v10.01.06 (Fiery Fox)]
[MCU2_0]     10.362759 s: SCICLIENT: DMSC FW revision 0xa
[MCU2_0]     10.362795 s: SCICLIENT: DMSC FW ABI revision 4.0
[MCU2_0]     10.362829 s: SCICLIENT: Init ... Done !!!
[MCU2_0]     10.362856 s: UDMA: Init ... !!!
[MCU2_0]     10.363986 s: UDMA: Init ... Done !!!
[MCU2_0]     10.364051 s: MEM: Init ... !!!
[MCU2_0]     10.364100 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e2400000 of size 15728640 bytes !!!
[MCU2_0]     10.364187 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!
[MCU2_0]     10.364247 s: MEM: Created heap (DDR_CACHE_WT_MEM, id=7, flags=0x00000000) @ e3300000 of size 1048576 bytes !!!
[MCU2_0]     10.364305 s: MEM: Init ... Done !!!
[MCU2_0]     10.364331 s: ETHFW: Init ... !!!
[MCU2_0]     10.365301 s: EthApp_initEthFw zwz change  333333!!!!
[MCU2_0]     10.365409 s: ETHFW: Warning: Using 6 random MAC address(es)
[MCU2_0]     10.365679 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]     10.374484 s: Mdio_open: MDIO manual mode enabled
[MCU2_0]     10.374552 s:
[MCU2_0]     10.375240 s: EnetHostPortDma_openRxCh: EnetHostPortDma_openRxCh ininin
[MCU2_0]     10.375304 s: : -1
[MCU2_0]     10.375341 s: EnetHostPortDma_openRxCh: EnetHostPortDma_openRxCh numRxCh is [1]
[MCU2_0]     10.375380 s: : -1
[MCU2_0]     10.375410 s: EnetHostPortDma_openRxCh: EnetUdma_openRxCh excute times is [0]
[MCU2_0]     10.375451 s: : -1
[MCU2_0]     10.376956 s: PHY 0 is alive
[MCU2_0]     10.377632 s: PHY 4 is alive
[MCU2_0]     10.382360 s: EnetPhy_bindDriver: PHY 4: OUI:006037 Model:10 Ver:02 <-> 'tja1101' : OK
[MCU2_0]     10.382419 s:
[MCU2_0]     10.382653 s: ETHFW: Shared multicasts:
[MCU2_0]     10.382727 s: ETHFW:   01:00:5e:00:00:01
[MCU2_0]     10.382771 s: ETHFW:   01:00:5e:00:00:fb
[MCU2_0]     10.382809 s: ETHFW:   01:00:5e:00:00:fc
[MCU2_0]     10.382847 s: ETHFW:   33:33:00:00:00:01
[MCU2_0]     10.382882 s: ETHFW:   33:33:ff:1d:92:c2
[MCU2_0]     10.382919 s: ETHFW:   01:80:c2:00:00:00
[MCU2_0]     10.382954 s: ETHFW:   01:80:c2:00:00:03
[MCU2_0]     10.382983 s: ETHFW: Reserved multicasts:
[MCU2_0]     10.383027 s: ETHFW:   01:80:c2:00:00:0e
[MCU2_0]     10.383067 s: ETHFW:   01:1b:19:00:00:00
[MCU2_0]     10.383127 s: ETHFW: CPSW recovery is not enabled
[MCU2_0]     10.384631 s: ETHFW: VLAN 1024 member=0x1ed virtMember=0x7 regMcastFlood=0x1ed unregMcastFlood=0x1ed untag=0x0
[MCU2_0]     10.385213 s: ETHFW: 1 VLAN entries added in ALE table
[MCU2_0]     10.385622 s:
[MCU2_0] ETHFW Version   : 0.05.00
[MCU2_0]     10.385687 s: ETHFW Build Date: Feb 28, 2025
[MCU2_0]     10.385724 s: ETHFW Build Time: 14:24:49
[MCU2_0]     10.385754 s: ETHFW Commit SHA: a7d57c17
[MCU2_0]     10.385829 s: ETHFW: Init ... DONE !!!
[MCU2_0]     10.385869 s: IPC: Init ... !!!
[MCU2_0]     10.385934 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_0]     10.385982 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     25.076644 s: IPC: HLOS is ready !!!
[MCU2_0]     25.081258 s: IPC: Init ... Done !!!
[MCU2_0]     25.081323 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_0]     25.437892 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_0]     25.438063 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     25.438444 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     25.438542 s: FVID2: Init ... !!!
[MCU2_0]     25.438622 s: FVID2: Init ... Done !!!
[MCU2_0]     25.438672 s: DSS: Init ... !!!
[MCU2_0]     25.438701 s: DSS: Display type is eDP !!!
[MCU2_0]     25.438731 s: DSS: M2M Path is enabled !!!
[MCU2_0]     25.438759 s: DSS: SoC init ... !!!
[MCU2_0]     25.438783 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]     25.438958 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.439001 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
[MCU2_0]     25.439188 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.439232 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
[MCU2_0]     25.439394 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.439435 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
[MCU2_0]     25.439656 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     25.439693 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
[MCU2_0]     25.439922 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     25.439971 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
[MCU2_0]     25.440173 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     25.440216 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
[MCU2_0]     25.441429 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     25.441469 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
[MCU2_0]     25.441995 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]     25.442034 s: DSS: SoC init ... Done !!!
[MCU2_0]     25.442063 s: DSS: Board init ... !!!
[MCU2_0]     25.442088 s: DSS: Board init ... Done !!!
[MCU2_0]     25.457562 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     25.457629 s:
[MCU2_0]     25.457684 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     25.457722 s:
[MCU2_0]     25.460625 s: DSS: Init ... Done !!!
[MCU2_0]     25.460693 s: VHWA: VPAC Init ... !!!
[MCU2_0]     25.460728 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]     25.460923 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.460961 s: VHWA: LDC Init ... !!!
[MCU2_0]     25.464045 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     25.464106 s: VHWA: MSC Init ... !!!
[MCU2_0]     25.473882 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     25.473945 s: VHWA: NF Init ... !!!
[MCU2_0]     25.475538 s: VHWA: NF Init ... Done !!!
[MCU2_0]     25.475597 s: VHWA: VISS Init ... !!!
[MCU2_0]     25.485155 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     25.485229 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     25.485282 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
[MCU2_0]     25.485328 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
[MCU2_0]     25.485366 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
[MCU2_0]     25.486646 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink on target MCU2-0
[MCU2_0]     25.486771 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source on target MCU2-0
[MCU2_0]     25.486870 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink2 on target MCU2-0
[MCU2_0]     25.486956 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source2 on target MCU2-0
[MCU2_0]     25.487043 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_intermediate on target MCU2-0
[MCU2_0]     25.487142 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_intermediate_2 on target MCU2-0
[MCU2_0]     25.487236 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_error on target MCU2-0
[MCU2_0]     25.487325 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_obj_array on target MCU2-0
[MCU2_0]     25.487415 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_sink_obj_array on target MCU2-0
[MCU2_0]     25.487499 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_intermediate on target MCU2-0
[MCU2_0]     25.487586 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_source on target MCU2-0
[MCU2_0]     25.487669 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_sink on target MCU2-0
[MCU2_0]     25.487753 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.test_target on target MCU2-0
[MCU2_0]     25.487840 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.image_intermediate on target MCU2-0
[MCU2_0]     25.487927 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.cmd_timeout_test on target MCU2-0
[MCU2_0]     25.488016 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.tiovx_overhead on target MCU2-0
[MCU2_0]     25.488242 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MCU2-0
[MCU2_0]     25.488422 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_NF
[MCU2_0]     25.488592 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_LDC1
[MCU2_0]     25.488759 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_MSC1
[MCU2_0]     25.488931 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_MSC2
[MCU2_0]     25.489194 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_VISS1
[MCU2_0]     25.489408 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE1
[MCU2_0]     25.489616 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE2
[MCU2_0]     25.489825 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE3
[MCU2_0]     25.490026 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE4
[MCU2_0]     25.490252 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE5
[MCU2_0]     25.490465 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE6
[MCU2_0]     25.490667 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE7
[MCU2_0]     25.490875 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE8
[MCU2_0]     25.491080 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DISPLAY1
[MCU2_0]     25.491310 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DISPLAY2
[MCU2_0]     25.491487 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CSITX
[MCU2_0]     25.491667 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DSS_M2M1
[MCU2_0]     25.491849 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DSS_M2M2
[MCU2_0]     25.492025 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DSS_M2M3
[MCU2_0]     25.492213 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DSS_M2M4
[MCU2_0]     25.492276 s:  VX_ZONE_INFO: [tivxInitLocal:126] Initialization Done !!!
[MCU2_0]     25.492315 s:  VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
[MCU2_0]     25.492349 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     25.507826 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     25.507889 s: CSI2RX: Init ... !!!
[MCU2_0]     25.507921 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     25.508043 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.508083 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]     25.508234 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.508269 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]     25.508413 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.508448 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]     25.508550 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.508585 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]     25.508678 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.508887 s: CSI2RX: Init ... Done !!!
[MCU2_0]     25.508927 s: CSI2TX: Init ... !!!
[MCU2_0]     25.508956 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     25.509044 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.509078 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]     25.509201 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.509240 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]     25.509352 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.509438 s: CSI2TX: Init ... Done !!!
[MCU2_0]     25.509477 s: ISS: Init ... !!!
[MCU2_0]     25.509520 s: IssSensor_Init ... Done !!!
[MCU2_0]     25.509602 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     25.509638 s: ISS: Init ... Done !!!
[MCU2_0]     25.509673 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     25.509741 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     25.509777 s: UDMA Copy: Init ... !!!
[MCU2_0]     25.511399 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     25.511469 s: APP: Init ... Done !!!
[MCU2_0]     25.511505 s: APP: Run ... !!!
[MCU2_0]     25.511531 s: IPC: Starting echo test ...
[MCU2_0]     25.511800 s: APP: Run ... Done !!!
[MCU2_0]     25.511846 s: appMAX9295Config I2C Instance = 1
[MCU2_0]     25.512058 s: @0x42 write 0x0001 for value 0x14, readback: 0x05, status = 0
[MCU2_0]     25.517286 s: @0x42 read 0x0001 -> 0x14, status = 0
[MCU2_0]     25.517474 s: @0x42 write 0x0331 for value 0x33, readback: 0x14, status = 0
[MCU2_0]     25.520293 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     25.520345 s:
[MCU2_0]     25.520390 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     25.520426 s:
[MCU2_0]     25.522283 s: @0x42 read 0x0331 -> 0x33, status = 0
[MCU2_0]     25.522462 s: @0x42 write 0x0318 for value 0x64, readback: 0x33, status = 0
[MCU2_0]     25.530778 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     25.530831 s:
[MCU2_0]     25.530871 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     25.530906 s:
[MCU2_0]     25.538302 s: @0x42 read 0x0318 -> 0x64, status = 0
[MCU2_0]     25.538378 s: max9295 init status is [0]
[MCU2_0]     25.539028 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[.] C66X_2[.] C7X_1[.]
[MCU2_0]     25.539141 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[.] C7X_1[.]
[MCU2_0]     25.539233 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[.]
[MCU2_0]     25.539322 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU2_0]     25.539545 s: unibase-1.1.5-jacinto
[MCU2_0]     25.540220 s: Starting lwIP, local interface IP is dhcp-enabled
[MCU2_0]     25.547111 s: ETHFW: Host MAC address: 70:cc:a3:04:71:98
[MCU2_0]     25.550399 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0]     25.557029 s: [LWIPIF_LWIP_IC] Interface started successfully
[MCU2_0]     25.557099 s: [LWIPIF_LWIP_IC] NETIF INIT SUCCESS
[MCU2_0]     25.568522 s: [LWIPIF_LWIP_IC] Interface started successfully
[MCU2_0]     25.568594 s: [LWIPIF_LWIP_IC] NETIF INIT SUCCESS
[MCU2_0]     25.568686 s: Added interface 'br3', IP is 0.0.0.0
[MCU2_0]     25.568740 s: ipaddr->addr=0
[MCU2_0]     26.883404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     26.883467 s:
[MCU2_0]     26.883514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     26.883550 s:
[MCU2_0]     32.283408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     32.283474 s:
[MCU2_0]     32.283520 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     32.283560 s:
[MCU2_0]     37.683404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     37.683463 s:
[MCU2_0]     37.683510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     37.683547 s:
[MCU2_0]     43.083407 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     43.083473 s:
[MCU2_0]     43.083521 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     43.083557 s:
[MCU2_0]     48.483410 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     48.483472 s:
[MCU2_0]     48.483520 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     48.483558 s:
[MCU2_0]     53.883406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     53.883471 s:
[MCU2_0]     53.883515 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     53.883552 s:
[MCU2_0]     59.283409 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     59.283468 s:
[MCU2_0]     59.283516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     59.283555 s:
[MCU2_0]     64.683406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     64.683467 s:
[MCU2_0]     64.683514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     64.683552 s:
[MCU2_0]     70.083403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     70.083466 s:
[MCU2_0]     70.083509 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     70.083545 s:
[MCU2_0]     75.483405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     75.483465 s:
[MCU2_0]     75.483510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     75.483547 s:







[MCU2_0]     80.883408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     80.883470 s:
[MCU2_0]     80.883517 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     80.883554 s:
[MCU2_0]     86.283401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     86.283461 s:
[MCU2_0]     86.283510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     86.283549 s:
[MCU2_0]     91.683408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     91.683471 s:
[MCU2_0]     91.683518 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     91.683558 s:
[MCU2_0]     97.083402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]     97.083468 s:
[MCU2_0]     97.083516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]     97.083554 s:
[MCU2_0]    102.483404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    102.483468 s:
[MCU2_0]    102.483514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    102.483550 s:
[MCU2_0]    107.883400 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    107.883460 s:
[MCU2_0]    107.883505 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    107.883543 s:
[MCU2_0]    113.283406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    113.283468 s:
[MCU2_0]    113.283514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    113.283550 s:
[MCU2_0]    118.683405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    118.683467 s:
[MCU2_0]    118.683510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    118.683546 s:
[MCU2_0]    124.083407 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    124.083472 s:
[MCU2_0]    124.083520 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    124.083559 s:
[MCU2_0]    129.483408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    129.483476 s:
[MCU2_0]    129.483530 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    129.483569 s:
[MCU2_0]    134.883402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    134.883465 s:
[MCU2_0]    134.883515 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    134.883555 s:
[MCU2_0]    140.283399 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    140.283465 s:
[MCU2_0]    140.283519 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    140.283557 s:
[MCU2_0]    145.683403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    145.683465 s:
[MCU2_0]    145.683511 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    145.683549 s:
[MCU2_0]    151.083401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    151.083464 s:
[MCU2_0]    151.083511 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    151.083547 s:
[MCU2_0]    156.483401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    156.483462 s:
[MCU2_0]    156.483508 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    156.483547 s:
[MCU2_0]    161.883405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    161.883464 s:
[MCU2_0]    161.883510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    161.883548 s:
[MCU2_0]    167.283402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    167.283465 s:
[MCU2_0]    167.283510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    167.283549 s:
[MCU2_0]    172.683400 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    172.683463 s:
[MCU2_0]    172.683513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    172.683549 s:
[MCU2_0]    178.083399 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    178.083465 s:
[MCU2_0]    178.083513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    178.083551 s:
[MCU2_0]    183.483401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    183.483468 s:
[MCU2_0]    183.483516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    183.483556 s:
[MCU2_0]    188.883410 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    188.883475 s:
[MCU2_0]    188.883521 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    188.883558 s:
[MCU2_0]    194.283401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    194.283462 s:
[MCU2_0]    194.283507 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    194.283543 s:
[MCU2_0]    199.683404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    199.683466 s:
[MCU2_0]    199.683516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    199.683553 s:
[MCU2_0]    205.083409 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    205.083472 s:
[MCU2_0]    205.083523 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    205.083564 s:
[MCU2_0]    210.483402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    210.483470 s:
[MCU2_0]    210.483517 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    210.483556 s:
[MCU2_0]    215.883408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    215.883472 s:
[MCU2_0]    215.883519 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    215.883555 s:
[MCU2_0]    221.283407 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    221.283468 s:
[MCU2_0]    221.283512 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    221.283551 s:
[MCU2_0]    226.683396 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    226.683457 s:
[MCU2_0]    226.683504 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    226.683540 s:
[MCU2_0]    232.083403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    232.083469 s:
[MCU2_0]    232.083516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    232.083553 s:
[MCU2_0]    237.483406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    237.483470 s:
[MCU2_0]    237.483513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    237.483552 s:
[MCU2_0]    242.883403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    242.883469 s:
[MCU2_0]    242.883516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    242.883554 s:
[MCU2_0]    248.283404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    248.283467 s:
[MCU2_0]    248.283509 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    248.283547 s:
[MCU2_0]    253.683400 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    253.683463 s:
[MCU2_0]    253.683509 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    253.683546 s:
[MCU2_0]    259.083400 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    259.083463 s:
[MCU2_0]    259.083509 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    259.083546 s:
[MCU2_0]    264.483402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    264.483466 s:
[MCU2_0]    264.483515 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    264.483554 s:
[MCU2_0]    269.883398 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    269.883460 s:
[MCU2_0]    269.883503 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    269.883539 s:
[MCU2_0]    275.283401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    275.283460 s:
[MCU2_0]    275.283507 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    275.283545 s:
[MCU2_0]    280.683401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    280.683463 s:
[MCU2_0]    280.683508 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    280.683545 s:
[MCU2_0]    286.083401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    286.083469 s:
[MCU2_0]    286.083514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    286.083552 s:
[MCU2_0]    291.483408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    291.483472 s:
[MCU2_0]    291.483518 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    291.483554 s:
[MCU2_0]    296.883402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    296.883466 s:
[MCU2_0]    296.883512 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    296.883548 s:
[MCU2_0]    302.283402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    302.283465 s:
[MCU2_0]    302.283512 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    302.283547 s:
[MCU2_0]    307.683404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    307.683468 s:
[MCU2_0]    307.683513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    307.683551 s:
[MCU2_0]    313.083401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    313.083464 s:
[MCU2_0]    313.083505 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    313.083541 s:
[MCU2_0]    318.483398 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    318.483457 s:
[MCU2_0]    318.483501 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    318.483537 s:
[MCU2_0]    323.883401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    323.883464 s:
[MCU2_0]    323.883513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    323.883549 s:
[MCU2_0]    329.283409 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    329.283474 s:
[MCU2_0]    329.283523 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    329.283560 s:
[MCU2_0]    334.683412 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    334.683474 s:
[MCU2_0]    334.683514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    334.683547 s:
[MCU2_0]    340.083401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    340.083469 s:
[MCU2_0]    340.083514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    340.083550 s:
[MCU2_0]    345.483398 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    345.483462 s:
[MCU2_0]    345.483506 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    345.483546 s:
[MCU2_0]    350.883401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    350.883463 s:
[MCU2_0]    350.883504 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    350.883539 s:
[MCU2_0]    356.283409 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    356.283475 s:
[MCU2_0]    356.283521 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    356.283559 s:
[MCU2_0]    361.683408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    361.683469 s:
[MCU2_0]    361.683513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    361.683550 s:
[MCU2_0]    367.083404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    367.083466 s:
[MCU2_0]    367.083511 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    367.083549 s:
[MCU2_0]    372.483405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    372.483467 s:
[MCU2_0]    372.483514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    372.483550 s:
[MCU2_0]    377.883405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    377.883467 s:
[MCU2_0]    377.883514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    377.883554 s:
[MCU2_0]    383.283402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    383.283465 s:
[MCU2_0]    383.283514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    383.283550 s:
[MCU2_0]    388.683408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    388.683473 s:
[MCU2_0]    388.683519 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    388.683556 s:
[MCU2_0]    394.083401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    394.083466 s:
[MCU2_0]    394.083516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    394.083555 s:
[MCU2_0]    399.483406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    399.483467 s:
[MCU2_0]    399.483512 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    399.483547 s:
[MCU2_0]    404.883398 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    404.883464 s:
[MCU2_0]    404.883512 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    404.883547 s:
[MCU2_0]    410.283402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    410.283465 s:
[MCU2_0]    410.283510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    410.283545 s:
[MCU2_0]    415.683400 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    415.683465 s:
[MCU2_0]    415.683513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    415.683550 s:
[MCU2_0]    421.083403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    421.083468 s:
[MCU2_0]    421.083516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    421.083555 s:
[MCU2_0]    426.483396 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    426.483455 s:
[MCU2_0]    426.483500 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    426.483541 s:
[MCU2_0]    431.883402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    431.883465 s:
[MCU2_0]    431.883505 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    431.883543 s:
[MCU2_0]    437.283402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    437.283460 s:
[MCU2_0]    437.283505 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    437.283542 s:
[MCU2_0]    442.683408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    442.683474 s:
[MCU2_0]    442.683518 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    442.683554 s:
[MCU2_0]    448.083407 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    448.083468 s:
[MCU2_0]    448.083510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    448.083543 s:
[MCU2_0]    453.483409 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    453.483473 s:
[MCU2_0]    453.483519 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    453.483559 s:
[MCU2_0]    458.883404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    458.883466 s:
[MCU2_0]    458.883511 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    458.883547 s:
[MCU2_0]    464.283403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    464.283467 s:
[MCU2_0]    464.283516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    464.283552 s:
[MCU2_0]    469.683413 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    469.683478 s:
[MCU2_0]    469.683525 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    469.683562 s:
[MCU2_0]    475.083403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    475.083465 s:
[MCU2_0]    475.083512 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    475.083551 s:
[MCU2_0]    480.483400 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    480.483462 s:
[MCU2_0]    480.483508 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    480.483546 s:
[MCU2_0]    485.883406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    485.883466 s:
[MCU2_0]    485.883511 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    485.883548 s:
[MCU2_0]    491.283402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    491.283465 s:
[MCU2_0]    491.283513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    491.283550 s:
[MCU2_0]    496.683401 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    496.683465 s:
[MCU2_0]    496.683513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    496.683553 s:
[MCU2_0]    502.083400 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    502.083463 s:
[MCU2_0]    502.083509 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    502.083545 s:
[MCU2_0]    507.483408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    507.483469 s:
[MCU2_0]    507.483514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    507.483552 s:
[MCU2_0]    512.883405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    512.883467 s:
[MCU2_0]    512.883513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    512.883550 s:
[MCU2_0]    518.283406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    518.283468 s:
[MCU2_0]    518.283517 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    518.283554 s:
[MCU2_0]    523.683407 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    523.683466 s:
[MCU2_0]    523.683511 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    523.683549 s:
[MCU2_0]    529.083409 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    529.083471 s:
[MCU2_0]    529.083520 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    529.083560 s:
[MCU2_0]    534.483404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    534.483469 s:
[MCU2_0]    534.483519 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    534.483553 s:
[MCU2_0]    539.883406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    539.883469 s:
[MCU2_0]    539.883515 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    539.883552 s:
[MCU2_0]    545.283402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    545.283463 s:
[MCU2_0]    545.283503 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    545.283540 s:
[MCU2_0]    550.683410 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    550.683472 s:
[MCU2_0]    550.683517 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    550.683553 s:
[MCU2_0]    556.083406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    556.083467 s:
[MCU2_0]    556.083515 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    556.083550 s:
[MCU2_0]    561.483405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    561.483469 s:
[MCU2_0]    561.483516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    561.483558 s:
[MCU2_0]    566.883406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    566.883471 s:
[MCU2_0]    566.883523 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    566.883561 s:
[MCU2_0]    572.283403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    572.283465 s:
[MCU2_0]    572.283511 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    572.283545 s:
[MCU2_0]    577.683408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    577.683472 s:
[MCU2_0]    577.683517 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    577.683551 s:
[MCU2_0]    583.083405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    583.083471 s:
[MCU2_0]    583.083521 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    583.083563 s:
[MCU2_0]    588.483408 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    588.483471 s:
[MCU2_0]    588.483514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    588.483550 s:
[MCU2_0]    593.883405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    593.883467 s:
[MCU2_0]    593.883514 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    593.883551 s:
[MCU2_0]    599.283409 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    599.283474 s:
[MCU2_0]    599.283526 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    599.283563 s:
[MCU2_0]    604.683407 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    604.683469 s:
[MCU2_0]    604.683517 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    604.683555 s:
[MCU2_0]    610.083410 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    610.083474 s:
[MCU2_0]    610.083521 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    610.083562 s:
[MCU2_0]    615.483404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    615.483466 s:
[MCU2_0]    615.483512 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    615.483548 s:
[MCU2_0]    620.883402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    620.883461 s:
[MCU2_0]    620.883506 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    620.883545 s:
[MCU2_0]    626.283404 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    626.283467 s:
[MCU2_0]    626.283515 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    626.283555 s:
[MCU2_0]    631.683400 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    631.683464 s:
[MCU2_0]    631.683509 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    631.683545 s:
[MCU2_0]    637.083414 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    637.083477 s:
[MCU2_0]    637.083524 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    637.083561 s:
[MCU2_0]    642.483402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    642.483466 s:
[MCU2_0]    642.483511 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    642.483547 s:
[MCU2_0]    647.883407 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    647.883472 s:
[MCU2_0]    647.883513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    647.883550 s:
[MCU2_0]    653.283395 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    653.283456 s:
[MCU2_0]    653.283504 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    653.283544 s:
[MCU2_0]    658.683400 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    658.683466 s:
[MCU2_0]    658.683513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    658.683551 s:
[MCU2_0]    664.083406 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    664.083468 s:
[MCU2_0]    664.083515 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    664.083552 s:
[MCU2_0]    669.483402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    669.483461 s:
[MCU2_0]    669.483504 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    669.483541 s:
[MCU2_0]    674.883402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    674.883464 s:
[MCU2_0]    674.883510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    674.883545 s:
[MCU2_0]    680.283403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    680.283468 s:
[MCU2_0]    680.283516 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    680.283552 s:
[MCU2_0]    685.683399 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    685.683457 s:
[MCU2_0]    685.683502 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    685.683542 s:
[MCU2_0]    691.083399 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    691.083464 s:
[MCU2_0]    691.083510 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    691.083551 s:
[MCU2_0]    696.483405 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    696.483468 s:
[MCU2_0]    696.483519 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    696.483556 s:
[MCU2_0]    701.883402 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    701.883466 s:
[MCU2_0]    701.883513 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    701.883551 s:
[MCU2_0]    707.283407 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    707.283470 s:
[MCU2_0]    707.283518 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    707.283556 s:
[MCU2_0]    712.683411 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    712.683477 s:
[MCU2_0]    712.683525 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    712.683561 s:
[MCU2_0]    718.083411 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    718.083476 s:
[MCU2_0]    718.083522 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    718.083561 s:
[MCU2_0]    723.483395 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    723.483463 s:
[MCU2_0]    723.483515 s: EnetPhy_enableState: PHY 4: new link caps: FD100
[MCU2_0]    723.483553 s:
[MCU2_0]    728.883403 s: EnetPhy_enableState: PHY 4: falling back to manual mode
[MCU2_0]    728.883465 s:
[MCU2_0]    728.883512 s: EnetPhy_enableState: PHY 4: new link caps: FD100

root@j721e-evm:~# /opt/vx_app_arm_remote_log.out |grep MCU2_0
[MCU2_0]     10.276505 s: CIO: Init ... Done !!!
[MCU2_0]     10.276579 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]     10.276615 s: CPU is running FreeRTOS
[MCU2_0]     10.276638 s: APP: Init ... !!!
[MCU2_0]     10.276659 s: SCICLIENT: Init ... !!!
[MCU2_0]     10.276863 s: SCICLIENT: DMSC FW version [10.1.6--v10.01.06 (Fiery Fox)]
[MCU2_0]     10.276909 s: SCICLIENT: DMSC FW revision 0xa
[MCU2_0]     10.276936 s: SCICLIENT: DMSC FW ABI revision 4.0
[MCU2_0]     10.276963 s: SCICLIENT: Init ... Done !!!
[MCU2_0]     10.276986 s: UDMA: Init ... !!!
[MCU2_0]     10.278078 s: UDMA: Init ... Done !!!
[MCU2_0]     10.278138 s: MEM: Init ... !!!
[MCU2_0]     10.278177 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ f1200000 of size 2097152 bytes !!!
[MCU2_0]     10.278237 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!
[MCU2_0]     10.278285 s: MEM: Created heap (DDR_CACHE_WT_MEM, id=7, flags=0x00000000) @ f1400000 of size 1048576 bytes !!!
[MCU2_0]     10.278345 s: MEM: Init ... Done !!!
[MCU2_0]     10.278367 s: ETHFW: Init ... !!!
[MCU2_0]     10.279377 s: ETHFW: Warning: Using 6 random MAC address(es)
[MCU2_0]     10.279640 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]     10.288450 s: Mdio_open: MDIO manual mode enabled
[MCU2_0]     10.288517 s:
[MCU2_0]     10.290657 s: PHY 0 is alive
[MCU2_0]     10.291339 s: PHY 4 is alive
[MCU2_0]     10.296112 s: EnetPhy_bindDriver: PHY 4: OUI:006037 Model:10 Ver:02 <-> 'tja1101' : OK
[MCU2_0]     10.296168 s:
[MCU2_0]     10.296407 s: ETHFW: Shared multicasts:
[MCU2_0]     10.296475 s: ETHFW:   01:00:5e:00:00:01
[MCU2_0]     10.296511 s: ETHFW:   01:00:5e:00:00:fb
[MCU2_0]     10.296544 s: ETHFW:   01:00:5e:00:00:fc
[MCU2_0]     10.296575 s: ETHFW:   33:33:00:00:00:01
[MCU2_0]     10.296606 s: ETHFW:   33:33:ff:1d:92:c2
[MCU2_0]     10.296636 s: ETHFW:   01:80:c2:00:00:00
[MCU2_0]     10.296665 s: ETHFW:   01:80:c2:00:00:03
[MCU2_0]     10.296690 s: ETHFW: Reserved multicasts:
[MCU2_0]     10.296722 s: ETHFW:   01:80:c2:00:00:0e
[MCU2_0]     10.296750 s: ETHFW:   01:1b:19:00:00:00
[MCU2_0]     10.296796 s: ETHFW: CPSW recovery is not enabled
[MCU2_0]     10.298307 s: ETHFW: VLAN 1024 member=0x1ed virtMember=0x7 regMcastFlood=0x1ed unregMcastFlood=0x1ed untag=0x0
[MCU2_0]     10.298880 s: ETHFW: 1 VLAN entries added in ALE table
[MCU2_0]     10.299115 s:
[MCU2_0] ETHFW Version   : 0.05.00
[MCU2_0]     10.299176 s: ETHFW Build Date: Mar  4, 2025
[MCU2_0]     10.299206 s: ETHFW Build Time: 10:24:25
[MCU2_0]     10.299231 s: ETHFW Commit SHA: 303d812f
[MCU2_0]     10.299308 s: ETHFW: Init ... DONE !!!
[MCU2_0]     10.299339 s: IPC: Init ... !!!
[MCU2_0]     10.299395 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_0]     10.299435 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     25.686398 s: IPC: HLOS is ready !!!
[MCU2_0]     25.690861 s: IPC: Init ... Done !!!
[MCU2_0]     25.690925 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_0]     25.908384 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_0]     25.908526 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     25.908878 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     25.908950 s: FVID2: Init ... !!!
[MCU2_0]     25.909049 s: FVID2: Init ... Done !!!
[MCU2_0]     25.909094 s: DSS: Init ... !!!
[MCU2_0]     25.909120 s: DSS: Display type is eDP !!!
[MCU2_0]     25.909143 s: DSS: M2M Path is enabled !!!
[MCU2_0]     25.909166 s: DSS: SoC init ... !!!
[MCU2_0]     25.909186 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]     25.909374 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.909416 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
[MCU2_0]     25.909596 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.909628 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
[MCU2_0]     25.909782 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.909814 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
[MCU2_0]     25.910046 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     25.910077 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
[MCU2_0]     25.910273 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     25.910307 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
[MCU2_0]     25.910463 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     25.910511 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
[MCU2_0]     25.911718 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     25.911750 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
[MCU2_0]     25.912295 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]     25.912328 s: DSS: SoC init ... Done !!!
[MCU2_0]     25.912353 s: DSS: Board init ... !!!
[MCU2_0]     25.912376 s: DSS: Board init ... Done !!!
[MCU2_0]     25.930812 s: DSS: Init ... Done !!!
[MCU2_0]     25.930882 s: VHWA: VPAC Init ... !!!
[MCU2_0]     25.930911 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]     25.931091 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.931126 s: VHWA: LDC Init ... !!!
[MCU2_0]     25.934119 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     25.934181 s: VHWA: MSC Init ... !!!
[MCU2_0]     25.943898 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     25.943960 s: VHWA: NF Init ... !!!
[MCU2_0]     25.945474 s: VHWA: NF Init ... Done !!!
[MCU2_0]     25.945531 s: VHWA: VISS Init ... !!!
[MCU2_0]     25.954886 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     25.954953 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     25.955002 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
[MCU2_0]     25.955044 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
[MCU2_0]     25.955076 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
[MCU2_0]     25.956358 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink on target MCU2-0
[MCU2_0]     25.956470 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source on target MCU2-0
[MCU2_0]     25.956547 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_sink2 on target MCU2-0
[MCU2_0]     25.956617 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_source2 on target MCU2-0
[MCU2_0]     25.956688 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.scalar_intermediate on target MCU2-0
[MCU2_0]     25.956759 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_intermediate_2 on target MCU2-0
[MCU2_0]     25.956830 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_error on target MCU2-0
[MCU2_0]     25.956902 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_source_obj_array on target MCU2-0
[MCU2_0]     25.956974 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.scalar_sink_obj_array on target MCU2-0
[MCU2_0]     25.957046 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_intermediate on target MCU2-0
[MCU2_0]     25.957119 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_source on target MCU2-0
[MCU2_0]     25.957189 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.pyramid_sink on target MCU2-0
[MCU2_0]     25.957258 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.test_target on target MCU2-0
[MCU2_0]     25.957345 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.capture.image_intermediate on target MCU2-0
[MCU2_0]     25.957423 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.cmd_timeout_test on target MCU2-0
[MCU2_0]     25.957495 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:162] registered kernel com.ti.test_kernels.tiovx_overhead on target MCU2-0
[MCU2_0]     25.957699 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MCU2-0
[MCU2_0]     25.957864 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_NF
[MCU2_0]     25.958022 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_LDC1
[MCU2_0]     25.958168 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_MSC1
[MCU2_0]     25.958325 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_MSC2
[MCU2_0]     25.958564 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target VPAC_VISS1
[MCU2_0]     25.958757 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE1
[MCU2_0]     25.958945 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE2
[MCU2_0]     25.959140 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE3
[MCU2_0]     25.959341 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE4
[MCU2_0]     25.959542 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE5
[MCU2_0]     25.959744 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE6
[MCU2_0]     25.959944 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE7
[MCU2_0]     25.960129 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CAPTURE8
[MCU2_0]     25.960343 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DISPLAY1
[MCU2_0]     25.960544 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DISPLAY2
[MCU2_0]     25.960718 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target CSITX
[MCU2_0]     25.960882 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DSS_M2M1
[MCU2_0]     25.961045 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DSS_M2M2
[MCU2_0]     25.961204 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DSS_M2M3
[MCU2_0]     25.961383 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target DSS_M2M4
[MCU2_0]     25.961433 s:  VX_ZONE_INFO: [tivxInitLocal:126] Initialization Done !!!
[MCU2_0]     25.961471 s:  VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
[MCU2_0]     25.961497 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     25.977181 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     25.977239 s: CSI2RX: Init ... !!!
[MCU2_0]     25.977266 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     25.977386 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.977424 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]     25.977564 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.977594 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]     25.977711 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.977739 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]     25.977832 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.977859 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]     25.977944 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.978142 s: CSI2RX: Init ... Done !!!
[MCU2_0]     25.978177 s: CSI2TX: Init ... !!!
[MCU2_0]     25.978197 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     25.978282 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.978328 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]     25.978432 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.978460 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]     25.978562 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     25.978638 s: CSI2TX: Init ... Done !!!
[MCU2_0]     25.978669 s: ISS: Init ... !!!
[MCU2_0]     25.978706 s: IssSensor_Init ... Done !!!
[MCU2_0]     25.978778 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     25.978807 s: ISS: Init ... Done !!!
[MCU2_0]     25.978830 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     25.978883 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     25.978911 s: UDMA Copy: Init ... !!!
[MCU2_0]     25.980520 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     25.980578 s: APP: Init ... Done !!!
[MCU2_0]     25.980607 s: APP: Run ... !!!
[MCU2_0]     25.980629 s: IPC: Starting echo test ...
[MCU2_0]     25.980976 s: APP: Run ... Done !!!
[MCU2_0]     25.981015 s: appMAX9295Config I2C Instance = 1
[MCU2_0]     25.981224 s: @0x42 write 0x0001 for value 0x14, readback: 0x05, status = 0
[MCU2_0]     25.985458 s: @0x42 read 0x0001 -> 0x14, status = 0
[MCU2_0]     25.985641 s: @0x42 write 0x0331 for value 0x33, readback: 0x14, status = 0
[MCU2_0]     25.990454 s: @0x42 read 0x0331 -> 0x33, status = 0
[MCU2_0]     25.990627 s: @0x42 write 0x0318 for value 0x64, readback: 0x33, status = 0
[MCU2_0]     26.006459 s: @0x42 read 0x0318 -> 0x64, status = 0
[MCU2_0]     26.006531 s: max9295 init status is [0]
[MCU2_0]     26.008870 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[.] C7X_1[.]
[MCU2_0]     26.008969 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[.] C7X_1[.]
[MCU2_0]     26.009047 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[.]
[MCU2_0]     26.009118 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU2_0]     26.009909 s: Starting lwIP, local interface IP is dhcp-enabled
[MCU2_0]     26.016734 s: ETHFW: Host MAC address: 70:35:e5:ca:1a:9b
[MCU2_0]     26.019932 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0]     26.026636 s: [LWIPIF_LWIP_IC] Interface started successfully
[MCU2_0]     26.026708 s: [LWIPIF_LWIP_IC] NETIF INIT SUCCESS
[MCU2_0]     26.033364 s: [LWIPIF_LWIP_IC] Interface started successfully
[MCU2_0]     26.033437 s: [LWIPIF_LWIP_IC] NETIF INIT SUCCESS
[MCU2_0]     26.033530 s: Added interface 'br3', IP is 0.0.0.0

^C
root@j721e-evm:~# ^C
root@j721e-evm:~# ifconfig
lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 18  bytes 2180 (2.1 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 18  bytes 2180 (2.1 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

root@j721e-evm:~# ^

/* NOTE: 2 virtual ports should not have same tx channel allocated to them */
static EthFwVirtPort_VirtPortCfg gEthApp_virtPortCfg[] =
{
    {
        .remoteCoreId  = IPC_MPU1_0,
        .portId        = ETHREMOTECFG_SWITCH_PORT_0,
#if defined(ETHFW_EST_DEMO_SUPPORT) || defined(ETHFW_DEMO_SUPPORT)
        .numTxCh       = 1U,
        .txCh          = {
                            [0] = ENET_RM_TX_CH_4
                         },
#else
         .numTxCh      = 2U,
         .txCh         = {
                            [0] = ENET_RM_TX_CH_4,
                            [1] = ENET_RM_TX_CH_7
                         },
#endif
        /* Number of rx flow for this virtual port */
        .numRxFlow     = 1U,
        /* To create custom policers on rx flows clients need to give flow information (i.e. numCustomPolicers and customPolicersInArgs)
         * for each allocated flow.
         * Map the customPolicersInArgs with global custom policer's (i.e. gEthApp_customPolicers) array.
         * For example if numRxFlow is 1 and we want to create 1 custom policer to match with 2'nd custom policer in global array do this: 
         * .rxFlowsInfo = {  
         *                  [0] = {
         *                           .numCustomPolicers    = 1U,
         *                           .customPolicersInArgs = {
         *                                                       [0] = &gEthApp_customPolicers[2U],
         *                                                   }
         *                         }
         *               }
         * It is important to note that number of custom policers per rx flow is <= ETHREMOTECFG_POLICER_PERFLOW */
        .numMacAddress = 1U,
        .clientIdMask  = ETHFW_BIT(ETHREMOTECFG_CLIENTID_LINUX) | ETHFW_BIT(ETHREMOTECFG_CLIENTID_QNX),
    },

	{
        /* Virtual switch port for Ethfw, using ETHREMOTECFG_SWITCH_PORT_LAST */
        .remoteCoreId  = IPC_MCU2_0,
        .portId        = ETHREMOTECFG_SWITCH_PORT_LAST,
#if defined(ETHFW_EST_DEMO_SUPPORT) || defined(ETHFW_DEMO_SUPPORT)
        .numTxCh       = 3U,
        .txCh          = {
                            [0] = ENET_RM_TX_CH_0,
                            [1] = ENET_RM_TX_CH_7,
                            [2] = ENET_RM_TX_CH_6
                         },
#else
        .numTxCh       = 2U,
        .txCh          = {
                            [0] = ENET_RM_TX_CH_0,
                            [1] = ENET_RM_TX_CH_6
                         },
#endif
        .numRxFlow     = 5U,
        .numMacAddress = 1U,
        .clientIdMask  = ETHFW_BIT(ETHREMOTECFG_CLIENTID_NONE),
    },
    
};