TDA4VM-Q1: Ask the CPSW9G Native Linux Driver

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Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 6.6.32 (master@xzs) (aarch64-oe-linux-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240620) #4 SMP PREEMPT Tue Mar  4 17:15:35 CST 2025
[    0.000000] KASLR disabled due to lack of seed
[    0.000000] Machine model: Texas Instruments J721e EVM
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x00000008e0000000, size 512 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000008e0000000..0x00000008ffffffff (524288 KiB) map reusable linux,cma
[    0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a0000000..0x00000000a00fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a0000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a0100000..0x00000000a0ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a0100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a1000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a1000000..0x00000000a10fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a1000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a1100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a1100000..0x00000000a1ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a1100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a2000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a2000000..0x00000000a20fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a2000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a2100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a2100000..0x00000000a3ffffff (31744 KiB) nomap non-reusable vision-apps-r5f-memory@a2100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a4000000..0x00000000a40fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a4000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a4100000..0x00000000a5ffffff (31744 KiB) nomap non-reusable vision-apps-r5f-memory@a4100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a6000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a6000000..0x00000000a60fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a6000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a6100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a6100000..0x00000000a6ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a6100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a7000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a7000000..0x00000000a70fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a7000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a7100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a7100000..0x00000000a7ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a7100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c66-dma-memory@a8000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a8000000..0x00000000a80fffff (1024 KiB) nomap non-reusable vision-apps-c66-dma-memory@a8000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c66-memory@a8100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a8100000..0x00000000a8ffffff (15360 KiB) nomap non-reusable vision-apps-c66-memory@a8100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a9000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c66-dma-memory@a9000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a9000000..0x00000000a90fffff (1024 KiB) nomap non-reusable vision-apps-c66-dma-memory@a9000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a9100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c66-memory@a9100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a9100000..0x00000000a9ffffff (15360 KiB) nomap non-reusable vision-apps-c66-memory@a9100000
[    0.000000] OF: reserved mem: 0x00000000aa000000..0x00000000abffffff (32768 KiB) nomap non-reusable vision-apps-rtos-ipc-memory-region
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 96 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@ac000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000ac000000..0x00000000b1ffffff (98304 KiB) nomap non-reusable vision-apps-dma-memory@ac000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71-dma-memory@b2000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000b2000000..0x00000000b20fffff (1024 KiB) nomap non-reusable vision-apps-c71-dma-memory@b2000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b2100000, size 95 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71-memory@b2100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000b2100000..0x00000000b7ffffff (97280 KiB) nomap non-reusable vision-apps-c71-memory@b2100000
[    0.000000] OF: reserved mem: initialized node vision_apps_shared-memories, compatible id dma-heap-carveout
[    0.000000] OF: reserved mem: 0x00000000b8000000..0x00000000d7ffffff (524288 KiB) map non-reusable vision_apps_shared-memories
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000d8000000, size 192 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-lo@d8000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000d8000000..0x00000000e3ffffff (196608 KiB) nomap non-reusable vision-apps-core-heap-memory-lo@d8000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000e4000000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-virtual-eth-queues@e4000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000e4000000..0x00000000e47fffff (8192 KiB) nomap non-reusable vision-apps-r5f-virtual-eth-queues@e4000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000e4800000, size 24 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-virtual-eth-buffers@e4800000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000e4800000..0x00000000e5ffffff (24576 KiB) nomap non-reusable vision-apps-r5f-virtual-eth-buffers@e4800000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000880000000, size 624 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-hi@880000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000880000000..0x00000008a6ffffff (638976 KiB) nomap non-reusable vision-apps-core-heap-memory-hi@880000000
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000008ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x00000000b7ffffff]
[    0.000000]   node   0: [mem 0x00000000b8000000-0x00000000d7ffffff]
[    0.000000]   node   0: [mem 0x00000000d8000000-0x00000000e5ffffff]
[    0.000000]   node   0: [mem 0x00000000e6000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x00000008a6ffffff]
[    0.000000]   node   0: [mem 0x00000008a7000000-0x00000008ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.4
[    0.000000] percpu: Embedded 20 pages/cpu s42920 r8192 d30808 u81920
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: Spectre-v3a
[    0.000000] CPU features: detected: Spectre-BHB
[    0.000000] CPU features: detected: ARM erratum 1742098
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] alternatives: applying boot alternatives
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 root=PARTUUID=e9ba7f88-02 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1032192
[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[    0.000000] software IO TLB: area num 2.
[    0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
[    0.000000] Memory: 1694668K/4194304K available (12032K kernel code, 1250K rwdata, 4044K rodata, 2432K init, 502K bss, 1975348K reserved, 524288K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000]  Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 960 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] Root IRQ handler: gic_handle_irq
[    0.000000] GICv3: GICv3 features: 16 PPIs
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @8a7800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x00000008a7040000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008a7050000
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.008440] Console: colour dummy device 80x25
[    0.013016] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.023687] pid_max: default: 32768 minimum: 301
[    0.028445] LSM: initializing lsm=capability,integrity
[    0.033764] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.041341] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.050374] RCU Tasks: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
[    0.057638] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
[    0.065508] rcu: Hierarchical SRCU implementation.
[    0.070405] rcu:     Max phase no-delay instances is 1000.
[    0.075958] Platform MSI: msi-controller@1820000 domain created
[    0.082297] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.091722] EFI services will not be available.
[    0.096495] smp: Bringing up secondary CPUs ...
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
[    0.109782] Detected PIPT I-cache on CPU1
[    0.109832] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.109844] GICv3: CPU1: using allocated LPI pending table @0x00000008a7060000
[    0.109880] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.109952] smp: Brought up 1 node, 2 CPUs
[    0.139298] SMP: Total of 2 processors activated.
[    0.144102] CPU features: detected: 32-bit EL0 Support
[    0.149357] CPU features: detected: CRC32 instructions
[    0.154644] CPU: All CPU(s) started at EL2
[    0.158826] alternatives: applying system-wide alternatives
[    0.165645] devtmpfs: initialized
[    0.176202] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.186191] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
[    0.203207] pinctrl core: initialized pinctrl subsystem
[    0.208975] DMI not present or invalid.
[    0.213292] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.219922] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[    0.227235] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.235244] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.243377] audit: initializing netlink subsys (disabled)
[    0.249029] audit: type=2000 audit(0.160:1): state=initialized audit_enabled=0 res=1
[    0.249275] thermal_sys: Registered thermal governor 'step_wise'
[    0.256946] thermal_sys: Registered thermal governor 'power_allocator'
[    0.263170] cpuidle: using governor menu
[    0.273945] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.280908] ASID allocator initialised with 65536 entries
[    0.296500] platform a40000.pinctrl: Fixed dependency cycle(s) with /bus@100000/pinctrl@a40000/mcu-cpsw-cpts
[    0.307705] Modules: 27664 pages in range for non-PLT usage
[    0.307710] Modules: 519184 pages in range for PLT usage
[    0.313949] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[    0.326316] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[    0.332718] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[    0.339653] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[    0.346054] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    0.352987] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[    0.359388] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[    0.366322] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[    0.373588] k3-chipinfo 43000014.chipid: Family:J721E rev:SR1.1 JTAGID[0x1bb6402f] Detected
[    0.382666] iommu: Default domain type: Translated
[    0.387591] iommu: DMA domain TLB invalidation policy: strict mode
[    0.394061] SCSI subsystem initialized
[    0.398083] usbcore: registered new interface driver usbfs
[    0.403706] usbcore: registered new interface driver hub
[    0.409147] usbcore: registered new device driver usb
[    0.414577] pps_core: LinuxPPS API ver. 1 registered
[    0.419649] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.428987] PTP clock support registered
[    0.433097] EDAC MC: Ver: 3.0.0
[    0.436565] scmi_core: SCMI protocol bus registered
[    0.441699] FPGA manager framework
[    0.445214] Advanced Linux Sound Architecture Driver Initialized.
[    0.451963] vgaarb: loaded
[    0.454921] clocksource: Switched to clocksource arch_sys_counter
[    0.461295] VFS: Disk quotas dquot_6.6.0
[    0.465326] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.475647] Carveout Heap: Exported 512 MiB at 0x00000000b8000000
[    0.481973] NET: Registered PF_INET protocol family
[    0.487166] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.496271] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
[    0.505026] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.512948] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.521156] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
[    0.530107] TCP: Hash tables configured (established 32768 bind 32768)
[    0.536949] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    0.543870] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    0.551358] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    0.557663] RPC: Registered named UNIX socket transport module.
[    0.563720] RPC: Registered udp transport module.
[    0.568523] RPC: Registered tcp transport module.
[    0.573327] RPC: Registered tcp-with-tls transport module.
[    0.578930] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.585516] NET: Registered PF_XDP protocol family
[    0.590429] PCI: CLS 0 bytes, default 64
[    0.595251] Initialise system trusted keyrings
[    0.599939] workingset: timestamp_bits=46 max_order=20 bucket_order=0
[    0.606731] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.612856] NFS: Registering the id_resolver key type
[    0.618034] Key type id_resolver registered
[    0.622306] Key type id_legacy registered
[    0.626407] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.633256] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.654483] Key type asymmetric registered
[    0.658669] Asymmetric key parser 'x509' registered
[    0.663678] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 244)
[    0.671243] io scheduler mq-deadline registered
[    0.675871] io scheduler kyber registered
[    0.679988] io scheduler bfq registered
[    0.686165] pinctrl-single 4301c000.pinctrl: 94 pins, size 376
[    0.692478] pinctrl-single 11c000.pinctrl: 173 pins, size 692
[    0.698623] pinctrl-single 104200.pinctrl: 20 pins, size 80
[    0.704389] pinctrl-single 104280.pinctrl: 8 pins, size 32
[    0.710388] pinctrl-single a40000.pinctrl: 512 pins, size 2048
[    0.719978] Serial: 8250/16550 driver, 12 ports, IRQ sharing enabled
[    0.729112] arm-smmu-v3 36600000.iommu: ias 48-bit, oas 48-bit (features 0x00001faf)
[    0.737401] arm-smmu-v3 36600000.iommu: allocated 65536 entries for cmdq
[    0.744592] arm-smmu-v3 36600000.iommu: allocated 32768 entries for evtq
[    0.752898] arm-smmu-v3 36600000.iommu: msi_domain absent - falling back to wired irqs
[    0.764146] loop: module loaded
[    0.768012] megasas: 07.725.01.00-rc1
[    0.773695] tun: Universal TUN/TAP device driver, 1.6
[    0.779504] VFIO - User Level meta-driver version: 0.3
[    0.785373] usbcore: registered new interface driver usb-storage
[    0.791844] i2c_dev: i2c /dev entries driver
[    0.796232] pps_ldisc: PPS line discipline registered
[    0.802086] sdhci: Secure Digital Host Controller Interface driver
[    0.808410] sdhci: Copyright(c) Pierre Ossman
[    0.812969] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.819140] ledtrig-cpu: registered to indicate activity on CPUs
[    0.825441] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.832442] usbcore: registered new interface driver usbhid
[    0.838136] usbhid: USB HID core driver
[    0.842878] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[    0.851499] optee: probing for conduit method.
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
[    0.856059] optee: revision 4.2 (12d7c4ee)
[    0.872515] optee: dynamic shared memory is enabled
[    0.882164] random: crng init done
[    0.885700] optee: initialized driver
[    0.891080] NET: Registered PF_PACKET protocol family
[    0.896296] Key type dns_resolver registered
[    0.904189] registered taskstats version 1
[    0.908484] Loading compiled-in X.509 certificates
[    0.922010] ti-sci 44083000.system-controller: ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[    1.030406] omap_i2c 42120000.i2c: bus 0 rev0.12 at 400 kHz
[    1.036415] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 137 domain created
[    1.044971] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 131 domain created
[    1.054334] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 213 domain created
[    1.062975] ti-sci-inta 33d00000.interrupt-controller: Interrupt Aggregator domain 209 created
[    1.079318] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[    1.089204] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    1.095964] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.105674] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    1.115835] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.122595] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.130697] printk: console [ttyS2] disabled
[    1.135235] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 202, base_baud = 3000000) is a 8250
[    1.144120] printk: console [ttyS2] enabled
[    1.144120] printk: console [ttyS2] enabled
[    1.152661] printk: bootconsole [ns16550a0] disabled
[    1.152661] printk: bootconsole [ns16550a0] disabled
[    1.175681] 2850000.serial: ttyS7 at MMIO 0x2850000 (irq = 203, base_baud = 3000000) is a 8250
[    1.187745] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[    1.230926] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.241588] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, PhyId : 0x002b09b0 , PhyAddr : 0x00
[    1.250494] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, 31_F007 : 0x0040
[    1.257741] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, 1_C04A : 0x0000
[    1.264901] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, 1_0000 : 0x8040
[    1.272061] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, 1_0007 : 0x0009
[    1.279221] mv88e2111 46000f00.mdio:00: PHY failed to boot firmware, status=000d
[    1.286640] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver mv88e2111
[    1.294828] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    1.307723] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.314931] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.321234] pps pps0: new PPS source ptp0
[    1.325386] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010a, freq:500000000, add_val:1 pps:1
[    1.335689] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    1.378923] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.386480] davinci_mdio c000f00.mdio: no live phy, scanning all
[    1.966541] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    1.979245] am65-cpsw-nuss c000000.ethernet: /bus@100000/ethernet@c000000/ethernet-ports/port@3 error retrieving port phy: -19
[    1.991913] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    2.001209] mmc1: CQHCI version 5.10
[    2.001357] mmc0: CQHCI version 5.10
[    2.008410] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fc7100
[    2.015415] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fc7100
[    2.022279] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fc7100
[    2.029126] omap-mailbox 31f83000.mailbox: omap mailbox rev 0x66fc7100
[    2.035964] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fc7100
[    2.042520] pinctrl-single 4301c000.pinctrl: Invalid number of rows: 0
[    2.045537] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    2.049035] pinctrl-single 4301c000.pinctrl: no pins entries for wkup-gpio-default-pins
[    2.049092] pinctrl-single 11c000.pinctrl: pin PIN105 already requested by 44083000.system-controller:clock-controller; cannot claim for 600000.gpio
[    2.056623] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    2.064493] pinctrl-single 11c000.pinctrl: pin-105 (600000.gpio) status -22
[    2.064497] pinctrl-single 11c000.pinctrl: could not request pin 105 (PIN105) from group main-gpio0-default-pins  on device pinctrl-single
[    2.064502] davinci_gpio 600000.gpio: Error applying setting, reverse things back
[    2.115652] ------------[ cut here ]------------
[    2.120271] WARNING: CPU: 1 PID: 11 at drivers/reset/core.c:766 __reset_control_get_internal+0x68/0x194
[    2.129655] Modules linked in:
[    2.132702] CPU: 1 PID: 11 Comm: kworker/u4:0 Not tainted 6.6.32 #4
[    2.138952] Hardware name: Texas Instruments J721e EVM (DT)
[    2.144507] Workqueue: events_unbound deferred_probe_work_func
[    2.146099] mmc1: new high speed SDXC card at address aaaa
[    2.150335] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    2.150340] pc : __reset_control_get_internal+0x68/0x194
[    2.156414] mmcblk1: mmc1:aaaa SL64G 59.5 GiB
[    2.162743] lr : __of_reset_control_get+0x188/0x1c0
[    2.162747] sp : ffff800081493980
[    2.162749] x29: ffff800081493980 x28: 0000000000000000 x27: 0000000000000001
[    2.162755] x26: ffff000828b18af8 x25: 0000000000000001 x24: 0000000000000001
[    2.173306]  mmcblk1: p1 p2
[    2.177249] x23: 0000000000000000 x22: ffff0008273b2a88 x21: 0000000000000001
[    2.177255] x20: ffff0008273b2aa8 x19: ffff000828b01f40 x18: 0000000000000000
[    2.177260] x17: ffff000828104800 x16: ffff000828104600 x15: 0000000000000002
[    2.218903] x14: ffffffffffffffff x13: 0000000000000000 x12: 0000000000000019
[    2.226022] x11: 0101010101010101 x10: ffff8400830cc88f x9 : 0000000000000028
[    2.233140] x8 : 0101010101010101 x7 : 00000000736c6c65 x6 : 000000000080a3f0
[    2.240259] x5 : ffff8000814939d8 x4 : 0000000000000000 x3 : 0000000000000001
[    2.247376] x2 : 0000000000000001 x1 : 0000000000000001 x0 : 0000000000000000
[    2.254494] Call trace:
[    2.256930]  __reset_control_get_internal+0x68/0x194
[    2.261881]  __of_reset_control_get+0x188/0x1c0
[    2.266396]  of_reset_control_array_get+0xac/0x19c
[    2.271172]  cdns_sierra_phy_probe+0xb40/0x112c
[    2.275695]  platform_probe+0x68/0xc4
[    2.279347]  really_probe+0x148/0x2b0
[    2.282995]  __driver_probe_device+0x78/0x12c
[    2.287336]  driver_probe_device+0xd8/0x15c
[    2.291505]  __device_attach_driver+0xb8/0x134
[    2.295933]  bus_for_each_drv+0x88/0xe8
[    2.299756]  __device_attach+0xa0/0x190
[    2.303578]  device_initial_probe+0x14/0x20
[    2.307746]  bus_probe_device+0xac/0xb0
[    2.311569]  deferred_probe_work_func+0x88/0xc0
[    2.316086]  process_one_work+0x138/0x248
[    2.320089]  worker_thread+0x320/0x438
[    2.323825]  kthread+0x110/0x114
[    2.327040]  ret_from_fork+0x10/0x20
[    2.330604] ---[ end trace 0000000000000000 ]---
[    2.335286] cdns-sierra-phy 5010000.serdes: failed to get reset phy@0
[    2.335339] mmc0: Command Queue Engine enabled
[    2.346170] mmc0: new HS200 MMC card at address 0001
[    2.351134] cdns-sierra-phy: probe of 5010000.serdes failed with error -16
[    2.351543] mmcblk0: mmc0:0001 AAM20F 59.3 GiB
[    2.364482] mmcblk0boot0: mmc0:0001 AAM20F 31.5 MiB
[    2.369392] j721e-pcie 2920000.pcie: host bridge /bus@100000/pcie@2920000 ranges:
[    2.370189] mmcblk0boot1: mmc0:0001 AAM20F 31.5 MiB
[    2.376916] j721e-pcie 2920000.pcie:       IO 0x4400001000..0x4400010fff -> 0x0000001000
[    2.382458] mmcblk0rpmb: mmc0:0001 AAM20F 4.00 MiB, chardev (239:0)
[    2.390242] j721e-pcie 2920000.pcie:      MEM 0x4400011000..0x4407ffffff -> 0x0000011000
[    2.404309] j721e-pcie 2920000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    2.513172] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[    2.520560] phy phy-5020000.serdes.10: phy poweron failed --> -110
[    2.526729] j721e-pcie 2920000.pcie: error -ETIMEDOUT: Failed to init phy
[    2.533646] j721e-pcie: probe of 2920000.pcie failed with error -110
[    2.541106] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
[    2.552479] ti-udma 31150000.dma-controller: Channels: 122 (tchan: 61, rchan: 61, gp-rflow: 16)
[    2.567867] spi-nor spi6.0: s28hs512t (65536 Kbytes)
[    2.572974] 8 fixed-partitions partitions found on MTD device 47040000.spi.0
[    2.580014] Creating 8 MTD partitions on "47040000.spi.0":
[    2.585487] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    2.591599] 0x000000080000-0x000000280000 : "ospi.tispl"
[    2.597368] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    2.603204] 0x000000680000-0x0000006a0000 : "ospi.env"
[    2.608336] mtd: partition "ospi.env" doesn't end on an erase/write block -- force read-only
[    2.617257] 0x0000006a0000-0x0000006c0000 : "ospi.env.backup"
[    2.622999] mtd: partition "ospi.env.backup" doesn't start on an erase/write block boundary -- force read-only
[    2.633449] 0x0000006c0000-0x0000007c0000 : "ospi.sysfw"
[    2.639247] 0x000000800000-0x000003fc0000 : "ospi.rootfs"
[    2.645104] 0x000003fe0000-0x000004000000 : "ospi.phypattern"
[    2.650843] mtd: partition "ospi.phypattern" doesn't start on an erase/write block boundary -- force read-only
[    2.662085] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[    2.706923] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.717618] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, PhyId : 0x002b09b0 , PhyAddr : 0x00
[    2.726526] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, 31_F007 : 0x0040
[    2.733775] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, 1_C04A : 0x0000
[    2.740936] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, 1_0000 : 0x8040
[    2.748096] mv88e2111 46000f00.mdio:00: [xzs] mv3310_probe, 1_0007 : 0x0009
[    2.755256] mv88e2111 46000f00.mdio:00: PHY failed to boot firmware, status=000d
[    2.762686] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver mv88e2111
[    2.770871] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    2.783770] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    2.790978] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    2.797293] pps pps0: new PPS source ptp1
[    2.801435] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010a, freq:500000000, add_val:1 pps:1
[    2.819233] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    2.830453] pps pps1: new PPS source pps.-1
[    2.834666] pps pps1: Registered IRQ 232 as PPS source
[    2.845147] clk: Disabling unused clocks
[    2.870245] ALSA device list:
[    2.873213]   No soundcards found.
[    3.430445] EXT4-fs (mmcblk1p2): recovery complete
[    3.436345] EXT4-fs (mmcblk1p2): mounted filesystem 3a6947ba-91a3-4915-9b08-f9977d7f422b r/w with ordered data mode. Quota mode: none.
[    3.448454] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    3.458837] devtmpfs: mounted
[    3.463409] Freeing unused kernel memory: 2432K
[    3.468022] Run /sbin/init as init process
[    3.978033] systemd[1]: System time before build time, advancing clock.
[    4.062890] NET: Registered PF_INET6 protocol family
[    4.068506] Segment Routing with IPv6
[    4.072196] In-situ OAM (IOAM) with IPv6
[    4.127787] systemd[1]: systemd 255.4^ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -TPM2 -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
[    4.159601] systemd[1]: Detected architecture arm64.

Welcome to Arago 2023.10!

[    4.184584] systemd[1]: Hostname set to <j721e-evm>.
[    4.457498] systemd[1]: /usr/lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
[    4.531126] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
[    4.594220] systemd[1]: Queued start job for default target Graphical Interface.
[    4.630114] systemd[1]: Created slice Slice /system/getty.
[  OK  ] Created slice Slice /system/getty.
[    4.652316] systemd[1]: Created slice Slice /system/modprobe.
[  OK  ] Created slice Slice /system/modprobe.
[    4.676162] systemd[1]: Created slice Slice /system/serial-getty.
[  OK  ] Created slice Slice /system/serial-getty.
[    4.699886] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[    4.723173] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password Requests to Console Directory Watch.
[    4.747080] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Forward Password Requests to Wall Directory Watch.
[    4.771018] systemd[1]: Expecting device /dev/ttyS2...
         Expecting device /dev/ttyS2...
[    4.791036] systemd[1]: Reached target Path Units.
[  OK  ] Reached target Path Units.
[    4.810984] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[    4.830973] systemd[1]: Reached target Slice Units.
[  OK  ] Reached target Slice Units.
[    4.850982] systemd[1]: Reached target Swaps.
[  OK  ] Reached target Swaps.
[    4.895586] systemd[1]: Listening on RPCbind Server Activation Socket.
[  OK  ] Listening on RPCbind Server Activation Socket.
[    4.919122] systemd[1]: Reached target RPC Port Mapper.
[  OK  ] Reached target RPC Port Mapper.
[    4.944798] systemd[1]: Listening on Process Core Dump Socket.
[  OK  ] Listening on Process Core Dump Socket.
[    4.967236] systemd[1]: Listening on initctl Compatibility Named Pipe.
[  OK  ] Listening on initctl Compatibility Named Pipe.
[    4.991713] systemd[1]: Listening on Journal Audit Socket.
[  OK  ] Listening on Journal Audit Socket.
[    5.015368] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[    5.039377] systemd[1]: Listening on Journal Socket.
[  OK  ] Listening on Journal Socket.
[    5.055467] systemd[1]: Listening on Network Service Netlink Socket.
[  OK  ] Listening on Network Service Netlink Socket.
[    5.082343] systemd[1]: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    5.103311] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    5.123336] systemd[1]: Listening on User Database Manager Socket.
[  OK  ] Listening on User Database Manager Socket.
[    5.175218] systemd[1]: Mounting Huge Pages File System...
         Mounting Huge Pages File System...
[    5.193531] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    5.219654] systemd[1]: Mounting Kernel Debug File System...
         Mounting Kernel Debug File System...
[    5.243417] systemd[1]: Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
[    5.283452] systemd[1]: Mounting Temporary Directory /tmp...
         Mounting Temporary Directory /tmp...
[    5.305580] systemd[1]: Starting Create List of Static Device Nodes...
         Starting Create List of Static Device Nodes...
[    5.343888] systemd[1]: Starting Load Kernel Module configfs...
         Starting Load Kernel Module configfs...
[    5.371791] systemd[1]: Starting Load Kernel Module drm...
         Starting Load Kernel Module drm...
[    5.403828] systemd[1]: Starting Load Kernel Module fuse...
         Starting Load Kernel Module fuse...
[    5.427921] systemd[1]: Starting Start psplash boot splash screen...
         Starting Start psplash boot splash screen...
[    5.484598] systemd[1]: Starting RPC Bind...
         Starting RPC Bind...
[    5.491599] fuse: init (API version 7.39)
[    5.499358] systemd[1]: File System Check on Root Device was skipped because of an unmet condition check (ConditionPathIsReadWrite=!/).
[    5.516959] systemd[1]: Starting Journal Service...
         Starting Journal Service...
[    5.560031] systemd[1]: Starting Load Kernel Modules...
         Starting Load Kernel Modules...
[    5.604623] systemd[1]: Starting Generate network units from Kernel command line...
[    5.606555] systemd-journald[113]: Collecting audit messages is enabled.
         Starting Generate network units from Kernel command line...
[    5.647768] systemd[1]: Starting Remount Root and Kernel File Systems...
         Starting Remount Root and Kernel File Systems...
[    5.669317] cryptodev: loading out-of-tree module taints kernel.
[    5.685299] cryptodev: driver 1.13 loaded.
[    5.695534] systemd[1]: Starting Coldplug All udev Devices...
         Starting Coldplug All udev Devices...
[    5.715269] systemd[1]: Started RPC Bind.
[  OK  ] Started RPC Bind.
[    5.732782] systemd[1]: Started Journal Service.
[  OK  ] Started Journal Service.
[    5.742260] EXT4-fs (mmcblk1p2): re-mounted 3a6947ba-91a3-4915-9b08-f9977d7f422b r/w. Quota mode: none.
[  OK  ] Mounted Huge Pages File System.
[  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Mounted Temporary Directory /tmp.
[  OK  ] Finished Create List of Static Device Nodes.
[  OK  ] Finished Load Kernel Module configfs.
[  OK  ] Finished Load Kernel Module drm.
[  OK  ] Finished Load Kernel Module fuse.
[FAILED] Failed to start Start psplash boot splash screen.
See 'systemctl status psplash-start.service' for details.
[DEPEND] Dependency failed for Start psplas…temd progress communication helper.
[  OK  ] Finished Load Kernel Modules.
[  OK  ] Finished Generate network units from Kernel command line.
[  OK  ] Finished Remount Root and Kernel File Systems.
         Mounting FUSE Control File System...
         Mounting Kernel Configuration File System...
         Starting Flush Journal to Persistent Storage...
         Starting Apply Kernel Variables...
[    6.204741] systemd-journald[113]: Received client request to flush runtime journal.
         Starting Create Static Device Nodes in /dev gracefully...
[  OK  ] Finished Coldplug All udev Devices.
[  OK  ] Mounted FUSE Control File System.
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Finished Flush Journal to Persistent Storage.
[  OK  ] Finished Apply Kernel Variables.
[  OK  ] Finished Create Static Device Nodes in /dev gracefully.
         Starting Create Static Device Nodes in /dev...
[  OK  ] Finished Create Static Device Nodes in /dev.
[  OK  ] Reached target Preparation for Local File Systems.
         Mounting /var/volatile...
[    6.464618] audit: type=1334 audit(1709054766.484:2): prog-id=6 op=LOAD
[    6.471676] audit: type=1334 audit(1709054766.492:3): prog-id=7 op=LOAD
         Starting Rule-based Manager for Device Events and Files...
[  OK  ] Mounted /var/volatile.
         Starting Load/Save OS Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Finished Load/Save OS Random Seed.
[  OK  ] Finished Create Volatile Files and Directories.
[    6.678341] audit: type=1334 audit(1709054766.696:4): prog-id=8 op=LOAD
         Starting Network Name Resolution...
[    6.725783] audit: type=1334 audit(1709054766.744:5): prog-id=9 op=LOAD
         Starting Network Time Synchronization...
         Starting Record System Boot/Shutdown in UTMP...
[  OK  ] Started Rule-based Manager for Device Events and Files.
[    6.864149] audit: type=1334 audit(1709054766.880:6): prog-id=10 op=LOAD
[    6.879061] audit: type=1334 audit(1709054766.880:7): prog-id=11 op=LOAD
[    6.890517] audit: type=1334 audit(1709054766.880:8): prog-id=12 op=LOAD
         Starting User Database Manager...
[  OK  ] Finished Record System Boot/Shutdown in UTMP.
[  OK  ] Found device /dev/ttyS2.
[  OK  ] Started User Database Manager.
[  OK  ] Started Network Time Synchronization.
[  OK  ] Reached target System Time Set.
[  OK  ] Started Network Name Resolution.
[  OK  ] Reached target Host and Network Name Lookups.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily rotation of log files.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target Timer Units.
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[  OK  ] Listening on D-Bus System Message Bus Socket.
         Starting Docker Socket for the API...
[  OK  ] Listening on dropbear.socket.
[  OK  ] Listening on PC/SC Smart Card Daemon Activation Socket.
         Starting Weston socket...
[    7.651070] audit: type=1334 audit(1709057496.197:9): prog-id=13 op=LOAD
         Starting D-Bus System Message Bus...
         Starting Reboot and dump vmcore via kexec...
[  OK  ] Listening on Docker Socket for the API.
[  OK  ] Listening on Weston socket.
[  OK  ] Finished Reboot and dump vmcore via kexec.
[  OK  ] Reached target Socket Units.
[  OK  ] Started D-Bus System Message Bus.
[  OK  ] Reached target Basic System.
[  OK  ] Started Job spooling tools.
         Starting Avahi mDNS/DNS-SD Stack...
[    8.037807] dbus-broker-lau[341]: memfd_create() called without MFD_EXEC or MFD_NOEXEC_SEAL set
[  OK  ] Started Periodic Command Scheduler.
         Starting Print notice about GPLv3 packages...
[    8.088777] k3-dsp-rproc 4d80800000.dsp: assigned reserved memory node vision-apps-c66-dma-memory@a9000000
         Starting IPv6 Packet Filtering Framework...
[    8.131309] k3-dsp-rproc 4d80800000.dsp: configured DSP for IPC-only mode
         Starting IPv4 Packet Filtering Framework..[    8.147171] remoteproc remoteproc0: 4d80800000.dsp is available
.
[    8.161976] remoteproc remoteproc0: attaching to 4d80800000.dsp
[    8.169355] k3-dsp-rproc 4d80800000.dsp: DSP initialized in IPC-only mode
[    8.169388] rproc-virtio rproc-virtio.0.auto: assigned reserved memory node vision-apps-c66-dma-memory@a9000000
[    8.171266] mc: Linux media interface: v0.10
[    8.181095] virtio_rpmsg_bus virtio0: rpmsg host is online
[    8.181150] rproc-virtio rproc-virtio.0.auto: registered virtio0 (type 7)
[    8.181157] remoteproc remoteproc0: remote processor 4d80800000.dsp is now attached
[    8.182448] k3-dsp-rproc 4d81800000.dsp: assigned reserved memory node vision-apps-c66-dma-memory@a8000000
[    8.183754] k3-dsp-rproc 4d81800000.dsp: configured DSP for IPC-only mode
[    8.240790] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0xd
[    8.248833] videodev: Linux video capture interface: v2.00
[    8.253262] remoteproc remoteproc1: 4d81800000.dsp is available
[    8.261385] remoteproc remoteproc1: attaching to 4d81800000.dsp
[  OK  ] Started irqbalance daemon.
[    8.275070] k3-dsp-rproc 4d81800000.dsp: DSP initialized in IPC-only mode
         Starting Telephony service...
[    8.283979] rproc-virtio rproc-virtio.1.auto: assigned reserved memory node vision-apps-c66-dma-memory@a8000000
[    8.299712] virtio_rpmsg_bus virtio1: rpmsg host is online
[    8.305393] virtio_rpmsg_bus virtio1: creating channel rpmsg_chrdev addr 0xd
[    8.314096] rproc-virtio rproc-virtio.1.auto: registered virtio1 (type 7)
[    8.320954] remoteproc remoteproc1: remote processor 4d81800000.dsp is now attached
         Starting Update pmic registers for…le safety feature on power rails...
         Starting Expand the rootfs partiti…to full size of the boot device....
[  OK  ] Started strongSwan IPsec IKEv1/IKEv2 daemon using ipsec.conf.
[    8.351621] audit: type=1334 audit(1709057496.897:10): prog-id=14 op=LOAD
[    8.372539] audit: type=1334 audit(1709057496.913:11): prog-id=15 op=LOAD
[    8.375944] k3-dsp-rproc 64800000.dsp: assigned reserved memory node vision-apps-c71-dma-memory@b2000000
         Starting User Login Management...
         Starting Telnet Server...
[    8.444451] k3-dsp-rproc 64800000.dsp: configured DSP for IPC-only mode
[  OK  ] Finished IPv4 Packet Filtering Framework.
[  OK  ] Finished IPv6 Packet Filtering Fram[    8.464898] remoteproc remoteproc2: 64800000.dsp is available
ework.
[  OK  ] Reached target Preparation for Network.
[    8.506257] omap_rng 4e10000.rng: Random Number Generator ver. 241b34c
[    8.530909] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
[    8.538534] remoteproc remoteproc2: attaching to 64800000.dsp
         Starting Network Configuration...
[  OK  ] Finished Update pmic registers for…able safety feature on power rails.
[  OK  ] Started Avahi mDNS/DNS-SD Stack.
[  OK  ] Finished Telnet Server.
[    8.614524] remoteproc remoteproc2: unsupported resource 65538
[    8.625680] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vcc-supply regulator, assuming enabled
[    8.636835] k3-dsp-rproc 64800000.dsp: DSP initialized in IPC-only mode
[    8.647041] rproc-virtio rproc-virtio.4.auto: assigned reserved memory node vision-apps-c71-dma-memory@b2000000
[    8.660645] virtio_rpmsg_bus virtio2: rpmsg host is online
[    8.662649] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0xd
[    8.667621] rproc-virtio rproc-virtio.4.auto: registered virtio2 (type 7)
[    8.691071] remoteproc remoteproc2: remote processor 64800000.dsp is now attached
[    8.744815] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq-supply regulator, assuming enabled
[    8.759350] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq2-supply regulator, assuming enabled
[  OK  ] Started Telephony service.
[    8.799555] scsi host0: ufshcd
[    8.849155] scsi 0:0:0:49488: Well-known LUN    SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    8.871705] scsi 0:0:0:49476: Well-known LUN    SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    8.891447] scsi 0:0:0:49456: Well-known LUN    SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    8.912110] scsi 0:0:0:0: Direct-Access     SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    8.924274] sd 0:0:0:0: [sda] 61743104 4096-byte logical blocks: (253 GB/236 GiB)
[    8.924432] scsi 0:0:0:1: Direct-Access     SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    8.940031] sd 0:0:0:0: [sda] Write Protect is off
[    8.947600] scsi 0:0:0:2: Direct-Access     SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    8.955889] sd 0:0:0:1: [sdb] 8192 4096-byte logical blocks: (33.6 MB/32.0 MiB)
[    8.964228] sd 0:0:0:2: [sdc] 8192 4096-byte logical blocks: (33.6 MB/32.0 MiB)
[    8.971699] sd 0:0:0:1: [sdb] Write Protect is off
[    8.976489] sd 0:0:0:2: [sdc] Write Protect is off
[    8.976591] sd 0:0:0:2: [sdc] Write cache: enabled, read cache: enabled, supports DPO and FUA
[    8.981281] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, supports DPO and FUA
[    8.981291] sd 0:0:0:0: [sda] Preferred minimum I/O size 524288 bytes
[    9.010572] sd 0:0:0:2: [sdc] Preferred minimum I/O size 524288 bytes
[    9.018585] sd 0:0:0:1: [sdb] Write cache: enabled, read cache: enabled, supports DPO and FUA
[    9.030880] sd 0:0:0:2: [sdc] Optimal transfer size 524288 bytes
[    9.043048] sd 0:0:0:1: [sdb] Preferred minimum I/O size 524288 bytes
[    9.049589] sd 0:0:0:0: [sda] Optimal transfer size 524288 bytes
[    9.061626] sd 0:0:0:2: [sdc] Attached SCSI disk
[    9.066643] sd 0:0:0:1: [sdb] Optimal transfer size 524288 bytes
[    9.079170] sd 0:0:0:0: [sda] Attached SCSI disk
[    9.086733] img_enc 4200000.video-encoder: vxe_enc_probe: using heap 1 for internal alloc
[    9.095768] sd 0:0:0:1: [sdb] Attached SCSI disk
[    9.113295] img_dec 4300000.video-decoder: decoder registered as /dev/video0

[    9.127549] img_enc 4200000.video-encoder: encoder registered as /dev/video1
[    9.159602] platform 41000000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
[    9.247892] platform 41000000.r5f: configured R5F for IPC-only mode
[    9.276782] platform 41000000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a0000000
[    9.337033] remoteproc remoteproc3: 41000000.r5f is available
[    9.379399] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    9.383971] remoteproc remoteproc3: attaching to 41000000.r5f
[    9.411117] Bluetooth: Core ver 2.22
[    9.419086] NET: Registered PF_BLUETOOTH protocol family
[    9.430159] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    9.430617] Bluetooth: HCI device and connection manager initialized
[    9.436232] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
[    9.449928] remoteproc remoteproc3: rsc table is truncated
[    9.453098] Bluetooth: HCI socket layer initialized
[    9.456648] remoteproc remoteproc3: Failed to process resources: -22
[  OK  ] Finished Expand the rootfs partitio[    9.469112] Bluetooth: L2CAP socket layer initialized
n to full size of the boot device..
[    9.470130] k3_r5_rproc bus@100000:bus@28380000:r5fss@41000000: rproc_add failed, ret = -22
[    9.490820] Bluetooth: SCO socket layer initialized
[    9.500706] remoteproc remoteproc3: releasing 41000000.r5f
[    9.525897] k3_r5_rproc bus@100000:bus@28380000:r5fss@41000000: k3_r5_cluster_rproc_init failed, ret = -22
[    9.539784] k3_r5_rproc: probe of bus@100000:bus@28380000:r5fss@41000000 failed with error -22
[    9.557048] platform 5c00000.r5f: configured R5F for IPC-only mode
[    9.563837] platform 5c00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a2000000
[    9.575987] remoteproc remoteproc3: 5c00000.r5f is available
[    9.581801] remoteproc remoteproc3: attaching to 5c00000.r5f
[    9.588302] platform 5c00000.r5f: R5F core initialized in IPC-only mode
[    9.595224] rproc-virtio rproc-virtio.5.auto: assigned reserved memory node vision-apps-r5f-dma-memory@a2000000
[    9.606236] virtio_rpmsg_bus virtio3: rpmsg host is online
[    9.611841] virtio_rpmsg_bus virtio3: creating channel rpmsg_chrdev addr 0xd
[    9.612638] rproc-virtio rproc-virtio.5.auto: registered virtio3 (type 7)
[    9.626020] remoteproc remoteproc3: remote processor 5c00000.r5f is now attached
[    9.635271] platform 5d00000.r5f: configured R5F for IPC-only mode
[    9.642656] platform 5d00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a4000000
[    9.655466] remoteproc remoteproc4: 5d00000.r5f is available
         Starting Virtual Console Setup...
[    9.739996] remoteproc remoteproc4: attaching to 5d00000.r5f
[    9.747525] platform 5d00000.r5f: R5F core initialized in IPC-only mode
[    9.754581] rproc-virtio rproc-virtio.6.auto: assigned reserved memory node vision-apps-r5f-dma-memory@a4000000
[    9.769031] virtio_rpmsg_bus virtio4: rpmsg host is online
[    9.774595] virtio_rpmsg_bus virtio3: creating channel rpmsg_chrdev addr 0x15
[    9.774854] virtio_rpmsg_bus virtio4: creating channel rpmsg_chrdev addr 0xd
[    9.789036] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0x15
[    9.791589] rproc-virtio rproc-virtio.6.auto: registered virtio4 (type 7)
[    9.796340] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0x15
[    9.803100] remoteproc remoteproc4: remote processor 5d00000.r5f is now attached
[    9.810172] virtio_rpmsg_bus virtio1: creating channel rpmsg_chrdev addr 0x15
[    9.825149] virtio_rpmsg_bus virtio1: creating channel ti.ipc4.ping-pong addr 0xe
[    9.833203] virtio_rpmsg_bus virtio0: creating channel ti.ipc4.ping-pong addr 0xe
[    9.843644] virtio_rpmsg_bus virtio2: creating channel ti.ipc4.ping-pong addr 0xe
[    9.851338] virtio_rpmsg_bus virtio4: creating channel rpmsg_chrdev addr 0x15
[    9.859809] virtio_rpmsg_bus virtio4: creating channel ti.ipc4.ping-pong addr 0xe
[    9.867677] remoteproc remoteproc6: b034000.pru is available
[    9.868813] platform 5e00000.r5f: configured R5F for remoteproc mode
[    9.880631] remoteproc remoteproc7: b004000.rtu is available
[    9.886435] platform 5e00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a6000000
[    9.902538] remoteproc remoteproc5: 5e00000.r5f is available

[    9.910461] remoteproc remoteproc8: b00a000.txpru is available
[  OK  ] Reached target Network.
         Starting Enable and configure wl18xx bluetooth stack...
         Starting containerd container runtime...
[  OK  ] Started Netperf Benchmark Server    9.954852] remoteproc remoteproc5: loading /lib/firmware/j7-main-r5f1_0-fw failed with error -22
m.
[    9.961386] remoteproc remoteproc9: b038000.pru is available
[    9.965722] remoteproc remoteproc5: Direct firmware load for j7-main-r5f1_0-fw failed with error -22
[    9.983338] remoteproc remoteproc5: powering up 5e00000.r5f
[    9.983448] remoteproc remoteproc5: loading /lib/firmware/j7-main-r5f1_0-fw failed with error -22
[    9.983452] remoteproc remoteproc5: Direct firmware load for j7-main-r5f1_0-fw failed with error -22
[    9.983457] remoteproc remoteproc5: request_firmware failed: -22
[    9.983476] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [Generic Clause 45 PHY] (irq=POLL)
[    9.983485] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rgmii-rxid link mode
[    9.997568] remoteproc remoteproc10: b006000.rtu is available
[    9.998114] remoteproc remoteproc11: b00c000.txpru is available
[    9.999032] remoteproc remoteproc12: b134000.pru is available
[    9.999662] remoteproc remoteproc13: b104000.rtu is available
[   10.000195] remoteproc remoteproc14: b10a000.txpru is available
[   10.000766] remoteproc remoteproc15: b138000.pru is available
[   10.001202] remoteproc remoteproc16: b106000.rtu is available
[   10.001740] remoteproc remoteproc17: b10c000.txpru is available
         Starting Simple Network Management Protocol (SNMP) Daemon....
         Starting Permit User Sessions...
[  OK  ] Finished Enable and configure wl18xx bluetooth stack.
[  OK  ] Finished Permit User Sessions.
[  OK  ] Listening on Load/Save RF Kill Switch Status /dev/rfkill Watch.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
         Starting Weston, a Wayland compositor, as a system service...
[FAILED] Failed to start Synchronize System and HW clocks.
See 'systemctl status sync-clocks.service' for details.
[   10.650973] virtio_rpmsg_bus virtio3: creating channel ti.ipc4.ping-pong addr 0xe
[  OK  ] Finished Virtual Console Setup.
[  OK  ] Created slice User Slice of UID 1000.
         Starting User Runtime Directory /run/user/1000...
[  OK  ] Finished User Runtime Directory /run/user/1000.
         Starting User Manager for UID 1000...
[   11.734466] kauditd_printk_skb: 2 callbacks suppressed
[   11.734474] audit: type=1006 audit(1709057500.281:14): pid=560 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=1 res=1
[   11.752302] audit: type=1300 audit(1709057500.281:14): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffdcaec838 a2=4 a3=1 items=0 ppid=1 pid=560 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=1 comm="(systemd)" exe="/usr/lib/systemd/systemd-executor" key=(null)
[   11.779197] audit: type=1327 audit(1709057500.281:14): proctitle="(systemd)"
[   11.918971] k3_r5_rproc bus@100000:r5fss@5e00000: Timed out waiting for 5e00000.r5f core to power up!
[  OK  ] Started User Manager for UID 1000.
[  OK  ] Started Session c1 of User weston   12.445790] audit: type=1006 audit(1709057500.993:15): pid=510 uid=0 old-auid=4294967295 auid=1000 tty=tty7 old-ses=4294967295 ses=2 res=1
0m.
[   12.461466] audit: type=1300 audit(1709057500.993:15): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffda095228 a2=4 a3=1 items=0 ppid=1 pid=510 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=tty7 ses=2 comm="(weston)" exe="/usr/lib/systemd/systemd-executor" key=(null)
[   12.488605] audit: type=1327 audit(1709057500.993:15): proctitle="(weston)"
[  OK  ] Created slice Slice /system/systemd-fsck.
         Expecting device /dev/mmcblk1p1...
[  OK  ] Found device /dev/mmcblk1p1.
         Starting File System Check on /dev/mmcblk1p1...
[FAILED] Failed to start Weston, a Wayland compositor, as a system service.
See 'systemctl status weston.service' for details.
[  OK  ] Finished File System Check on /dev/mmcblk1p1.
         Mounting /run/media/boot-mmcblk1p1...
[  OK  ] Mounted /run/media/boot-mmcblk1p1.
[  OK  ] Started Simple Network Management Protocol (SNMP) Daemon..
[  OK  ] Started containerd container runtime.

 _____                    _____           _         _
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|
              |___|                    |___|

Arago Project j721e-evm ttyS2

Arago 2023.10 j721e-evm ttyS2

j721e-evm login: ***************************************************************
***************************************************************
NOTICE: This file system contains the following GPL-3.0 packages:
        adwaita-icon-theme-symbolic
        autoconf
        bash-dev
        bash
        bc
        binutils
        cifs-utils
        coreutils-stdbuf
        coreutils
        cpio
        cpp-symlinks
        cpp
        dosfstools
        elfutils
        findutils
        g++-symlinks
        g++
        gawk
        gcc-symlinks
        gcc
        gdb
        gdbserver
        gettext
        glmark2
        gnu-config
        grub-common
        grub-editenv
        grub-efi
        gzip
        hidapi
        kbd-dev
        kbd-keymaps-pine
        less
        libasm1
        libatomic-dev
        libatomic1
        libbfd
        libdebuginfod1
        libdw1
        libelf1
        libgcc-s-dev
        libgcc1
        libgdbm-compat4
        libgdbm-dev
        libgdbm6
        libgettextlib
        libgettextsrc
        libgmp10
        libidn2-0
        libmpc3
        libmpfr6
        libopcodes
        libqt5charts-examples
        libqt5charts-plugins
        libqt5charts-qmlplugins
        libqt5charts5
        libqt5serialport-examples
        libqt5serialport-plugins
        libqt5serialport-qmlplugins
        libqt5serialport5
        libqt5svg-examples
        libqt5svg-plugins
        libqt5svg-qmlplugins
        libqt5svg5
        libqt5virtualkeyboard-plugins
        libqt5virtualkeyboard-qmlplugins
        libqt5virtualkeyboard5
        libreadline-dev
        libreadline8
        libstdc++-dev
        libstdc++6
        libunistring5
        m4
        make
        nettle
        parted
        piglit
        qt3d-plugins
        qt3d-qmlplugins
        qt3d
        qtbase-examples
        qtbase-plugins
        qtbase-qmlplugins
        qtbase
        qtconnectivity-plugins
        qtconnectivity-qmlplugins
        qtconnectivity
        qtdeclarative-plugins
        qtdeclarative-qmlplugins
        qtdeclarative-tools
        qtdeclarative
        qtgraphicaleffects-qmlplugins
        qtlocation-examples
        qtlocation-plugins
        qtlocation-qmlplugins
        qtlocation
        qtmultimedia-examples
        qtmultimedia-plugins
        qtmultimedia-qmlplugins
        qtmultimedia
        qtquics-qmlplugins.control
        qtquics2-plugins.control
        qtquics2-qmlplugins.control
        qtquics2.control
        qtscript-examples
        qtscript-plugins
        qtscript-qmlplugins
        qtscript
        qtwayland-examples
        qtwayland-plugins
        qtwayland-qmlplugins
        qtwayland
        tar
        which

If you do not wish to distribute GPL-3.0 components please remove
the above packages prior to distribution.  This can be done using
the opkg remove command.  i.e.:
    opkg remove <package>
Where <package> is the name printed in the list above

NOTE: If the package is a dependency of another package you
      will be notified of the dependent packages.  You should
      use the --force-removal-of-dependent-packages option to
      also remove the dependent packages as well
***************************************************************
***************************************************************

j721e-evm login: root
[   21.130373] audit: type=1006 audit(1709057509.677:16): pid=975 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=3 res=1
[   21.142879] audit: type=1300 audit(1709057509.677:16): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=ffffd285cd48 a2=1 a3=1 items=0 ppid=1 pid=975 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/usr/lib/systemd/systemd-executor" key=(null)
[   21.169677] audit: type=1327 audit(1709057509.677:16): proctitle="(systemd)"
[   21.176812] audit: type=1334 audit(1709057509.697:17): prog-id=18 op=LOAD
[   21.183741] audit: type=1300 audit(1709057509.697:17): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffd1bbf658 a2=90 a3=0 items=0 ppid=1 pid=975 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)
[   21.209507] audit: type=1327 audit(1709057509.697:17): proctitle="(systemd)"
[   21.216591] audit: type=1334 audit(1709057509.717:18): prog-id=18 op=UNLOAD
[   21.223591] audit: type=1300 audit(1709057509.717:18): arch=c00000b7 syscall=57 success=yes exit=0 a0=8 a1=1 a2=0 a3=ffffb0f74c60 items=0 ppid=1 pid=975 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)
[   21.250421] audit: type=1327 audit(1709057509.717:18): proctitle="(systemd)"
[   21.257513] audit: type=1334 audit(1709057509.717:19): prog-id=19 op=LOAD
root@j721e-evm:~# [   22.127244] platform gpio-regulator-tps659411: deferred probe pending

root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~# ifconfig
eth0: flags=4099<UP,BROADCAST,MULTICAST>  mtu 1500
        ether ec:bf:d0:bb:1e:47  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 28  bytes 2890 (2.8 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 28  bytes 2890 (2.8 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

root@j721e-evm:~#
root@j721e-evm:~#

Hi,

Can you update CPSW Port node as below.

&cpsw0_port3 {
	phy-mode = "sgmii";
	phys = <&cpsw0_phy_gmii_sel 3>, <&serdes1_sgmii_link>;
	mac-address = [00 00 00 00 00 00];
	phy-names = "mac", "serdes";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

Cannot see eth1 after adding these two lines.
phys = <&cpsw0_phy_gmii_sel 3>, <&serdes1_sgmii_link>;
phy-names = "mac", "serdes";

root@j721e-evm:~# dmesg | grep c000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 96 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@ac000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000ac000000..0x00000000b1ffffff (98304 KiB) nomap non-reusable vision-apps-dma-memory@ac000000
[    1.104179] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    1.114331] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.121089] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.963262] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    3.211794] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    3.338189] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110
root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep c000f00
[    1.331075] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    1.374583] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.382141] davinci_mdio c000f00.mdio: no live phy, scanning all
[    2.578015] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    2.622587] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.630151] davinci_mdio c000f00.mdio: no live phy, scanning all
root@j721e-evm:~#

After adding these two lines, Can see eth1, but cannot ping SOC1. Can ping SOC1 through ETHFW.
phys = <&cpsw0_phy_gmii_sel 3>, <&serdes1_sgmii_link>;
phy-names = "portmode", "serdes-phy";

root@j721e-evm:~# dmesg | grep c000f00
[    1.343006] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    1.386514] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.394072] davinci_mdio c000f00.mdio: no live phy, scanning all
[    2.605903] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    2.650520] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.658079] davinci_mdio c000f00.mdio: no live phy, scanning all
root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep c000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 96 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@ac000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000ac000000..0x00000000b1ffffff (98304 KiB) nomap non-reusable vision-apps-dma-memory@ac000000
[    1.105463] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    1.115640] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.122401] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.974647] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    1.987453] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[    1.993723] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
[    2.000843] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    2.007239] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    3.238263] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    3.251074] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[    3.257350] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
[    3.264471] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    3.270863] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    3.290023] am65-cpsw-nuss c000000.ethernet: set new flow-id-base 140
[   10.197988] am65-cpsw-nuss c000000.ethernet eth1: configuring for fixed/sgmii link mode
[   10.214801] am65-cpsw-nuss c000000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off
root@j721e-evm:~#
root@j721e-evm:~# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet6 fe80::eebf:d0ff:febb:1e47  prefixlen 64  scopeid 0x20<link>
        ether ec:bf:d0:bb:1e:47  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 37  bytes 7836 (7.6 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 192.168.1.2  netmask 255.255.255.0  broadcast 192.168.1.255
        inet6 fe80::e4b9:89ff:fe61:1f9b  prefixlen 64  scopeid 0x20<link>
        ether e6:b9:89:61:1f:9b  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 54  bytes 9774 (9.5 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 22  bytes 2628 (2.5 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 22  bytes 2628 (2.5 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

root@j721e-evm:~#
root@j721e-evm:~# ifconfig eth1 192.168.1.2
root@j721e-evm:~# ping 192.168.1.100
PING 192.168.1.100 (192.168.1.100) 56(84) bytes of data.
From 192.168.1.2 icmp_seq=1 Destination Host Unreachable
From 192.168.1.2 icmp_seq=5 Destination Host Unreachable
From 192.168.1.2 icmp_seq=6 Destination Host Unreachable
^C
--- 192.168.1.100 ping statistics ---
8 packets transmitted, 0 received, +3 errors, 100% packet loss, time 7162ms
pipe 4
root@j721e-evm:~#

Hi,

zs xu said:

After adding these two lines, Can see eth1, but cannot ping SOC1. Can ping SOC1 through ETHFW.

What do you mean, in case of ETHFW you are able to use Port-3 from SerDes1 and ping link partner.

In case of Linux you can't ? If so, confirm ETHFW is not enabled in your case.

Here, I can see Tx statistics of eth1 but not Rx, can you check on link partner side whether any packets received from CPSW or not?
Also, confirm is PHY configuration same in Linux and RTOS ETHFW?

Best Regards,
Sudheer

In file vision_apps_build_flags.mak, set BUILD_ENABLE_ETHFW?=no

And there is no output related to ETHFW in the log of mcu2_0.

I want to show that my SOC1 is working properly.

Symptom When eth1 is pinged, the SOC1 tcpdump fails to capture any packets.

Port-3 and SOC1 connect mac to mac directly through SGMII.

This configuration enables SOC1 to be pinged through ETHFW

    {
        .macPort   = ENET_MAC_PORT_3,
        .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_SERIAL },
        .phyCfg    =
        {
            .phyAddr         = ENETPHY_INVALID_PHYADDR,
            .isStrapped      = BFALSE,
            .skipExtendedCfg = BFALSE,
            .extendedCfg     = NULL,
            .extendedCfgSize = 0,
        },
        .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK,
        .linkCfg   = { ENET_SPEED_1GBIT, ENET_DUPLEX_FULL },
    },

Hi,

Can you please check by integrating below changes.



Best Regards,
Sudheer

My SDK does not have the code in the red box, I added these code, still can not ping.

root@j721e-evm:~# ifconfig eth1 192.168.1.2
root@j721e-evm:~# ping 192.168.1.100
PING 192.168.1.100 (192.168.1.100) 56(84) bytes of data.
From 192.168.1.2 icmp_seq=1 Destination Host Unreachable
From 192.168.1.2 icmp_seq=2 Destination Host Unreachable
From 192.168.1.2 icmp_seq=3 Destination Host Unreachable
^C
--- 192.168.1.100 ping statistics ---
5 packets transmitted, 0 received, +3 errors, 100% packet loss, time 4086ms
pipe 3
root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~# ifconfig
eth0: flags=4099<UP,BROADCAST,MULTICAST>  mtu 1500
        ether ec:bf:d0:bb:1e:47  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 192.168.1.2  netmask 255.255.255.0  broadcast 192.168.1.255
        inet6 fe80::7c3b:b8ff:fe29:b2f5  prefixlen 64  scopeid 0x20<link>
        ether 7e:3b:b8:29:b2:f5  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 36  bytes 5672 (5.5 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 23  bytes 2740 (2.6 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 23  bytes 2740 (2.6 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep c000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 96 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@ac000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000ac000000..0x00000000b1ffffff (98304 KiB) nomap non-reusable vision-apps-dma-memory@ac000000
[    1.104257] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    1.114412] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.121170] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.964553] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    1.977375] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[    1.983649] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
[    1.990768] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    1.997172] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    3.242441] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    3.255279] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[    3.261570] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
[    3.268690] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    3.275048] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    3.294043] am65-cpsw-nuss c000000.ethernet: set new flow-id-base 140
[   10.329672] am65-cpsw-nuss c000000.ethernet eth1: configuring for fixed/sgmii link mode
[   10.341952] am65-cpsw-nuss c000000.ethernet: config mac interface.
[   10.352119] am65-cpsw-nuss c000000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off
root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep c000f00
[    1.330820] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    1.374429] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.381990] davinci_mdio c000f00.mdio: no live phy, scanning all
[    2.609862] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    2.654436] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.661997] davinci_mdio c000f00.mdio: no live phy, scanning all
root@j721e-evm:~#

Hi,

zs xu said:

phy-names = "portmode", "serdes-phy";

If still not able to ping means SerDes issue only can you check by configuring phy-names as below.
phy-names = "mac", "serdes";

Above "serdes" should be used for serdes configuration.

If eth1 interface not comes up, please share the boot log (from above share boot log I could see driver probe failed).

Can you check whether serdes configs enabled or not?

Best Regards,
Sudheer

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 6.6.32 (master@xzs) (aarch64-oe-linux-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240620) #18 SMP PREEMPT Thu Mar  6 15:25:07 CST 2025
[    0.000000] KASLR disabled due to lack of seed
[    0.000000] Machine model: Texas Instruments J721e EVM
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x00000008e0000000, size 512 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000008e0000000..0x00000008ffffffff (524288 KiB) map reusable linux,cma
[    0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a0000000..0x00000000a00fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a0000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a0100000..0x00000000a0ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a0100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a1000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a1000000..0x00000000a10fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a1000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a1100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a1100000..0x00000000a1ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a1100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a2000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a2000000..0x00000000a20fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a2000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a2100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a2100000..0x00000000a3ffffff (31744 KiB) nomap non-reusable vision-apps-r5f-memory@a2100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a4000000..0x00000000a40fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a4000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a4100000..0x00000000a5ffffff (31744 KiB) nomap non-reusable vision-apps-r5f-memory@a4100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a6000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a6000000..0x00000000a60fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a6000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a6100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a6100000..0x00000000a6ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a6100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a7000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a7000000..0x00000000a70fffff (1024 KiB) nomap non-reusable vision-apps-r5f-dma-memory@a7000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a7100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a7100000..0x00000000a7ffffff (15360 KiB) nomap non-reusable vision-apps-r5f-memory@a7100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c66-dma-memory@a8000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a8000000..0x00000000a80fffff (1024 KiB) nomap non-reusable vision-apps-c66-dma-memory@a8000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c66-memory@a8100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a8100000..0x00000000a8ffffff (15360 KiB) nomap non-reusable vision-apps-c66-memory@a8100000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a9000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c66-dma-memory@a9000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a9000000..0x00000000a90fffff (1024 KiB) nomap non-reusable vision-apps-c66-dma-memory@a9000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a9100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c66-memory@a9100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000a9100000..0x00000000a9ffffff (15360 KiB) nomap non-reusable vision-apps-c66-memory@a9100000
[    0.000000] OF: reserved mem: 0x00000000aa000000..0x00000000abffffff (32768 KiB) nomap non-reusable vision-apps-rtos-ipc-memory-region
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 96 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@ac000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000ac000000..0x00000000b1ffffff (98304 KiB) nomap non-reusable vision-apps-dma-memory@ac000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71-dma-memory@b2000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000b2000000..0x00000000b20fffff (1024 KiB) nomap non-reusable vision-apps-c71-dma-memory@b2000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b2100000, size 95 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-c71-memory@b2100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000b2100000..0x00000000b7ffffff (97280 KiB) nomap non-reusable vision-apps-c71-memory@b2100000
[    0.000000] OF: reserved mem: initialized node vision_apps_shared-memories, compatible id dma-heap-carveout
[    0.000000] OF: reserved mem: 0x00000000b8000000..0x00000000d7ffffff (524288 KiB) map non-reusable vision_apps_shared-memories
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000d8000000, size 192 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-lo@d8000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000d8000000..0x00000000e3ffffff (196608 KiB) nomap non-reusable vision-apps-core-heap-memory-lo@d8000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000e4000000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-virtual-eth-queues@e4000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000e4000000..0x00000000e47fffff (8192 KiB) nomap non-reusable vision-apps-r5f-virtual-eth-queues@e4000000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000e4800000, size 24 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-r5f-virtual-eth-buffers@e4800000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000e4800000..0x00000000e5ffffff (24576 KiB) nomap non-reusable vision-apps-r5f-virtual-eth-buffers@e4800000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000880000000, size 624 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-hi@880000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000880000000..0x00000008a6ffffff (638976 KiB) nomap non-reusable vision-apps-core-heap-memory-hi@880000000
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000008ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x00000000b7ffffff]
[    0.000000]   node   0: [mem 0x00000000b8000000-0x00000000d7ffffff]
[    0.000000]   node   0: [mem 0x00000000d8000000-0x00000000e5ffffff]
[    0.000000]   node   0: [mem 0x00000000e6000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x00000008a6ffffff]
[    0.000000]   node   0: [mem 0x00000008a7000000-0x00000008ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.4
[    0.000000] percpu: Embedded 20 pages/cpu s42920 r8192 d30808 u81920
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: Spectre-v3a
[    0.000000] CPU features: detected: Spectre-BHB
[    0.000000] CPU features: detected: ARM erratum 1742098
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] alternatives: applying boot alternatives
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 root=PARTUUID=e9ba7f88-02 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1032192
[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[    0.000000] software IO TLB: area num 2.
[    0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
[    0.000000] Memory: 1694672K/4194304K available (12032K kernel code, 1250K rwdata, 4044K rodata, 2432K init, 502K bss, 1975344K reserved, 524288K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000]  Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 960 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] Root IRQ handler: gic_handle_irq
[    0.000000] GICv3: GICv3 features: 16 PPIs
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @8a7800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x00000008a7040000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008a7050000
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.008437] Console: colour dummy device 80x25
[    0.013009] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.023680] pid_max: default: 32768 minimum: 301
[    0.028439] LSM: initializing lsm=capability,integrity
[    0.033758] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.041335] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.050358] RCU Tasks: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
[    0.057624] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
[    0.065490] rcu: Hierarchical SRCU implementation.
[    0.070387] rcu:     Max phase no-delay instances is 1000.
[    0.075959] Platform MSI: msi-controller@1820000 domain created
[    0.082308] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.091745] EFI services will not be available.
[    0.096519] smp: Bringing up secondary CPUs ...
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
[    0.109800] Detected PIPT I-cache on CPU1
[    0.109848] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.109861] GICv3: CPU1: using allocated LPI pending table @0x00000008a7060000
[    0.109897] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.109966] smp: Brought up 1 node, 2 CPUs
[    0.139310] SMP: Total of 2 processors activated.
[    0.144115] CPU features: detected: 32-bit EL0 Support
[    0.149369] CPU features: detected: CRC32 instructions
[    0.154650] CPU: All CPU(s) started at EL2
[    0.158832] alternatives: applying system-wide alternatives
[    0.165658] devtmpfs: initialized
[    0.176101] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.186089] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
[    0.202978] pinctrl core: initialized pinctrl subsystem
[    0.208753] DMI not present or invalid.
[    0.213080] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.219710] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[    0.227029] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.235040] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.243173] audit: initializing netlink subsys (disabled)
[    0.248825] audit: type=2000 audit(0.160:1): state=initialized audit_enabled=0 res=1
[    0.249059] thermal_sys: Registered thermal governor 'step_wise'
[    0.256745] thermal_sys: Registered thermal governor 'power_allocator'
[    0.262963] cpuidle: using governor menu
[    0.273727] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.280690] ASID allocator initialised with 65536 entries
[    0.296148] platform a40000.pinctrl: Fixed dependency cycle(s) with /bus@100000/pinctrl@a40000/mcu-cpsw-cpts
[    0.307336] Modules: 27664 pages in range for non-PLT usage
[    0.307341] Modules: 519184 pages in range for PLT usage
[    0.313586] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[    0.325950] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[    0.332352] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[    0.339286] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[    0.345687] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    0.352621] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[    0.359021] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[    0.365955] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[    0.373200] k3-chipinfo 43000014.chipid: Family:J721E rev:SR1.1 JTAGID[0x1bb6402f] Detected
[    0.382283] iommu: Default domain type: Translated
[    0.387203] iommu: DMA domain TLB invalidation policy: strict mode
[    0.393662] SCSI subsystem initialized
[    0.397674] usbcore: registered new interface driver usbfs
[    0.403298] usbcore: registered new interface driver hub
[    0.408739] usbcore: registered new device driver usb
[    0.414155] pps_core: LinuxPPS API ver. 1 registered
[    0.419227] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.428565] PTP clock support registered
[    0.432667] EDAC MC: Ver: 3.0.0
[    0.436125] scmi_core: SCMI protocol bus registered
[    0.441257] FPGA manager framework
[    0.444775] Advanced Linux Sound Architecture Driver Initialized.
[    0.451513] vgaarb: loaded
[    0.454482] clocksource: Switched to clocksource arch_sys_counter
[    0.460860] VFS: Disk quotas dquot_6.6.0
[    0.464890] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.475189] Carveout Heap: Exported 512 MiB at 0x00000000b8000000
[    0.481514] NET: Registered PF_INET protocol family
[    0.486700] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.495817] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
[    0.504566] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.512488] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.520692] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
[    0.529643] TCP: Hash tables configured (established 32768 bind 32768)
[    0.536508] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    0.543438] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    0.550897] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    0.557211] RPC: Registered named UNIX socket transport module.
[    0.563273] RPC: Registered udp transport module.
[    0.568078] RPC: Registered tcp transport module.
[    0.572881] RPC: Registered tcp-with-tls transport module.
[    0.578485] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.585070] NET: Registered PF_XDP protocol family
[    0.589980] PCI: CLS 0 bytes, default 64
[    0.594801] Initialise system trusted keyrings
[    0.599478] workingset: timestamp_bits=46 max_order=20 bucket_order=0
[    0.606258] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.612394] NFS: Registering the id_resolver key type
[    0.617572] Key type id_resolver registered
[    0.621843] Key type id_legacy registered
[    0.625945] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.632793] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.654002] Key type asymmetric registered
[    0.658185] Asymmetric key parser 'x509' registered
[    0.663196] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 244)
[    0.670763] io scheduler mq-deadline registered
[    0.675390] io scheduler kyber registered
[    0.679505] io scheduler bfq registered
[    0.685680] pinctrl-single 4301c000.pinctrl: 94 pins, size 376
[    0.691997] pinctrl-single 11c000.pinctrl: 173 pins, size 692
[    0.698140] pinctrl-single 104200.pinctrl: 20 pins, size 80
[    0.703906] pinctrl-single 104280.pinctrl: 8 pins, size 32
[    0.709900] pinctrl-single a40000.pinctrl: 512 pins, size 2048
[    0.719466] Serial: 8250/16550 driver, 12 ports, IRQ sharing enabled
[    0.728593] arm-smmu-v3 36600000.iommu: ias 48-bit, oas 48-bit (features 0x00001faf)
[    0.736900] arm-smmu-v3 36600000.iommu: allocated 65536 entries for cmdq
[    0.744092] arm-smmu-v3 36600000.iommu: allocated 32768 entries for evtq
[    0.752429] arm-smmu-v3 36600000.iommu: msi_domain absent - falling back to wired irqs
[    0.763634] loop: module loaded
[    0.767485] megasas: 07.725.01.00-rc1
[    0.773180] tun: Universal TUN/TAP device driver, 1.6
[    0.778991] VFIO - User Level meta-driver version: 0.3
[    0.784865] usbcore: registered new interface driver usb-storage
[    0.791353] i2c_dev: i2c /dev entries driver
[    0.795735] pps_ldisc: PPS line discipline registered
[    0.801586] sdhci: Secure Digital Host Controller Interface driver
[    0.807907] sdhci: Copyright(c) Pierre Ossman
[    0.812469] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.818636] ledtrig-cpu: registered to indicate activity on CPUs
[    0.824940] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.831932] usbcore: registered new interface driver usbhid
[    0.837627] usbhid: USB HID core driver
[    0.842369] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[    0.850992] optee: probing for conduit method.
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
[    0.855553] optee: revision 4.2 (12d7c4ee)
[    0.872002] optee: dynamic shared memory is enabled
[    0.881642] random: crng init done
[    0.885177] optee: initialized driver
[    0.890455] NET: Registered PF_PACKET protocol family
[    0.895685] Key type dns_resolver registered
[    0.903510] registered taskstats version 1
[    0.907798] Loading compiled-in X.509 certificates
[    0.921094] ti-sci 44083000.system-controller: ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[    1.028045] omap_i2c 42120000.i2c: bus 0 rev0.12 at 400 kHz
[    1.034041] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 137 domain created
[    1.042595] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 131 domain created
[    1.051956] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 213 domain created
[    1.060599] ti-sci-inta 33d00000.interrupt-controller: Interrupt Aggregator domain 209 created
[    1.076655] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[    1.086546] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    1.093313] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.103071] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    1.113234] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.119993] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.128106] printk: console [ttyS2] disabled
[    1.132634] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 202, base_baud = 3000000) is a 8250
[    1.141538] printk: console [ttyS2] enabled
[    1.141538] printk: console [ttyS2] enabled
[    1.149990] printk: bootconsole [ns16550a0] disabled
[    1.149990] printk: bootconsole [ns16550a0] disabled
[    1.163207] 2850000.serial: ttyS7 at MMIO 0x2850000 (irq = 203, base_baud = 3000000) is a 8250
[    1.175202] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[    1.218485] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.231317] mv88q2220 46000f00.mdio:02: [xzs] mv88q2220_probe, PhyId : 0x002b0b20 , PhyAddr : 0x02
[    1.240727] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver unknown
[    1.248715] davinci_mdio 46000f00.mdio: phy[2]: device 46000f00.mdio:02, driver mv88q2220
[    1.256894] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    1.269785] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.276993] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.283280] pps pps0: new PPS source ptp0
[    1.287440] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010a, freq:500000000, add_val:1 pps:1
[    1.297825] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    1.342487] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.350045] davinci_mdio c000f00.mdio: no live phy, scanning all
[    1.930369] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    1.944379] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    1.953614] mmc1: CQHCI version 5.10
[    1.953738] mmc0: CQHCI version 5.10
[    1.960801] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fc7100
[    1.967818] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fc7100
[    1.974694] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fc7100
[    1.981534] omap-mailbox 31f83000.mailbox: omap mailbox rev 0x66fc7100
[    1.988398] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fc7100
[    1.994955] pinctrl-single 4301c000.pinctrl: Invalid number of rows: 0
[    1.999028] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    2.001475] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    2.008996] pinctrl-single 4301c000.pinctrl: no pins entries for wkup-gpio-default-pins
[    2.024566] pinctrl-single 11c000.pinctrl: pin PIN105 already requested by 44083000.system-controller:clock-controller; cannot claim for 600000.gpio
[    2.037983] pinctrl-single 11c000.pinctrl: pin-105 (600000.gpio) status -22
[    2.044952] pinctrl-single 11c000.pinctrl: could not request pin 105 (PIN105) from group main-gpio0-default-pins  on device pinctrl-single
[    2.057372] davinci_gpio 600000.gpio: Error applying setting, reverse things back
[    2.073863] j721e-pcie 2920000.pcie: host bridge /bus@100000/pcie@2920000 ranges:
[    2.081401] j721e-pcie 2920000.pcie:       IO 0x4400001000..0x4400010fff -> 0x0000001000
[    2.089626] j721e-pcie 2920000.pcie:      MEM 0x4400011000..0x4407ffffff -> 0x0000011000
[    2.097723] j721e-pcie 2920000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    2.117925] mmc1: new high speed SDXC card at address aaaa
[    2.123907] mmcblk1: mmc1:aaaa SL64G 59.5 GiB
[    2.133613]  mmcblk1: p1 p2
[    2.140565] mmc0: Command Queue Engine enabled
[    2.145012] mmc0: new HS200 MMC card at address 0001
[    2.150360] mmcblk0: mmc0:0001 AAM20F 59.3 GiB
[    2.156454] mmcblk0boot0: mmc0:0001 AAM20F 31.5 MiB
[    2.162140] mmcblk0boot1: mmc0:0001 AAM20F 31.5 MiB
[    2.167751] mmcblk0rpmb: mmc0:0001 AAM20F 4.00 MiB, chardev (239:0)
[    2.206536] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[    2.213927] phy phy-5020000.serdes.11: phy poweron failed --> -110
[    2.220101] j721e-pcie 2920000.pcie: error -ETIMEDOUT: Failed to init phy
[    2.226891] j721e-pcie: probe of 2920000.pcie failed with error -110
[    2.234538] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
[    2.245875] ti-udma 31150000.dma-controller: Channels: 122 (tchan: 61, rchan: 61, gp-rflow: 16)
[    2.261099] spi-nor spi6.0: s28hs512t (65536 Kbytes)
[    2.266179] 8 fixed-partitions partitions found on MTD device 47040000.spi.0
[    2.273247] Creating 8 MTD partitions on "47040000.spi.0":
[    2.278721] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    2.284853] 0x000000080000-0x000000280000 : "ospi.tispl"
[    2.290629] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    2.296459] 0x000000680000-0x0000006a0000 : "ospi.env"
[    2.301593] mtd: partition "ospi.env" doesn't end on an erase/write block -- force read-only
[    2.310520] 0x0000006a0000-0x0000006c0000 : "ospi.env.backup"
[    2.316256] mtd: partition "ospi.env.backup" doesn't start on an erase/write block boundary -- force read-only
[    2.326716] 0x0000006c0000-0x0000007c0000 : "ospi.sysfw"
[    2.332524] 0x000000800000-0x000003fc0000 : "ospi.rootfs"
[    2.338387] 0x000003fe0000-0x000004000000 : "ospi.phypattern"
[    2.344126] mtd: partition "ospi.phypattern" doesn't start on an erase/write block boundary -- force read-only
[    2.355370] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[    2.398484] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.411351] mv88q2220 46000f00.mdio:02: [xzs] mv88q2220_probe, PhyId : 0x002b0b20 , PhyAddr : 0x02
[    2.420761] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver unknown
[    2.428749] davinci_mdio 46000f00.mdio: phy[2]: device 46000f00.mdio:02, driver mv88q2220
[    2.436928] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    2.449828] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    2.457037] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    2.463351] pps pps0: new PPS source ptp1
[    2.467485] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010a, freq:500000000, add_val:1 pps:1
[    2.485345] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    2.496759] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    2.542484] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.550040] davinci_mdio c000f00.mdio: no live phy, scanning all
[    3.130266] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    3.243881] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
[    3.250659] phy phy-5010000.serdes.10: phy poweron failed --> -110
[    3.257100] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110
[    3.264537] pps pps1: new PPS source pps.-1
[    3.268743] pps pps1: Registered IRQ 232 as PPS source
[    3.279140] clk: Disabling unused clocks
[    3.303945] ALSA device list:
[    3.306912]   No soundcards found.
[    3.695094] EXT4-fs (mmcblk1p2): recovery complete
[    3.700869] EXT4-fs (mmcblk1p2): mounted filesystem 3a6947ba-91a3-4915-9b08-f9977d7f422b r/w with ordered data mode. Quota mode: none.
[    3.712977] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    3.723648] devtmpfs: mounted
[    3.728194] Freeing unused kernel memory: 2432K
[    3.732828] Run /sbin/init as init process
[    4.243249] systemd[1]: System time before build time, advancing clock.
[    4.325857] NET: Registered PF_INET6 protocol family
[    4.331458] Segment Routing with IPv6
[    4.335154] In-situ OAM (IOAM) with IPv6
[    4.390929] systemd[1]: systemd 255.4^ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -TPM2 -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
[    4.422735] systemd[1]: Detected architecture arm64.

Welcome to Arago 2023.10!

[    4.448166] systemd[1]: Hostname set to <j721e-evm>.
[    4.733679] systemd[1]: /usr/lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
[    4.806895] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
[    4.869804] systemd[1]: Queued start job for default target Graphical Interface.
[    4.913610] systemd[1]: Created slice Slice /system/getty.
[  OK  ] Created slice Slice /system/getty.
[    4.935820] systemd[1]: Created slice Slice /system/modprobe.
[  OK  ] Created slice Slice /system/modprobe.
[    4.959736] systemd[1]: Created slice Slice /system/serial-getty.
[  OK  ] Created slice Slice /system/serial-getty.
[    4.983499] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[    5.006762] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password Requests to Console Directory Watch.
[    5.030651] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Forward Password Requests to Wall Directory Watch.
[    5.054577] systemd[1]: Expecting device /dev/ttyS2...
         Expecting device /dev/ttyS2...
[    5.070644] systemd[1]: Reached target Path Units.
[  OK  ] Reached target Path Units.
[    5.090896] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[    5.110915] systemd[1]: Reached target Slice Units.
[  OK  ] Reached target Slice Units.
[    5.130753] systemd[1]: Reached target Swaps.
[  OK  ] Reached target Swaps.
[    5.174872] systemd[1]: Listening on RPCbind Server Activation Socket.
[  OK  ] Listening on RPCbind Server Activation Socket.
[    5.198680] systemd[1]: Reached target RPC Port Mapper.
[  OK  ] Reached target RPC Port Mapper.
[    5.224351] systemd[1]: Listening on Process Core Dump Socket.
[  OK  ] Listening on Process Core Dump Socket.
[    5.246793] systemd[1]: Listening on initctl Compatibility Named Pipe.
[  OK  ] Listening on initctl Compatibility Named Pipe.
[    5.271230] systemd[1]: Listening on Journal Audit Socket.
[  OK  ] Listening on Journal Audit Socket.
[    5.294923] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[    5.318912] systemd[1]: Listening on Journal Socket.
[  OK  ] Listening on Journal Socket.
[    5.334996] systemd[1]: Listening on Network Service Netlink Socket.
[  OK  ] Listening on Network Service Netlink Socket.
[    5.361904] systemd[1]: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    5.382859] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    5.402871] systemd[1]: Listening on User Database Manager Socket.
[  OK  ] Listening on User Database Manager Socket.
[    5.454788] systemd[1]: Mounting Huge Pages File System...
         Mounting Huge Pages File System...
[    5.481050] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    5.507065] systemd[1]: Mounting Kernel Debug File System...
         Mounting Kernel Debug File System...
[    5.526918] systemd[1]: Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
[    5.545506] systemd[1]: Mounting Temporary Directory /tmp...
         Mounting Temporary Directory /tmp...
[    5.591095] systemd[1]: Starting Create List of Static Device Nodes...
         Starting Create List of Static Device Nodes...
[    5.639263] systemd[1]: Starting Load Kernel Module configfs...
         Starting Load Kernel Module configfs...
[    5.687368] systemd[1]: Starting Load Kernel Module drm...
         Starting Load Kernel Module drm...
[    5.707289] systemd[1]: Starting Load Kernel Module fuse...
         Starting Load Kernel Module fuse...
[    5.731625] systemd[1]: Starting Start psplash boot splash screen...
         Starting Start psplash boot splash screen...
[    5.761699] fuse: init (API version 7.39)
[    5.807108] systemd[1]: Starting RPC Bind...
         Starting RPC Bind...
[    5.826841] systemd[1]: File System Check on Root Device was skipped because of an unmet condition check (ConditionPathIsReadWrite=!/).
[    5.843425] systemd[1]: Starting Journal Service...
         Starting Journal Service...
[    5.895141] systemd[1]: Starting Load Kernel Modules...
         Starting Load Kernel Modules...
[    5.939609] systemd-journald[117]: Collecting audit messages is enabled.
[    5.948097] systemd[1]: Starting Generate network units from Kernel command line...
         Starting Generate network units from Kernel command line...
[    5.987174] systemd[1]: Starting Remount Root and Kernel File Systems...
[    5.994353] cryptodev: loading out-of-tree module taints kernel.
         Starting Remount Root and Kernel File Systems systemd[1]: Starting Coldplug All udev Devices...
[0m...
[    6.014842] cryptodev: driver 1.13 loaded.
         Starting Coldplug All udev Devices...
[    6.044809] systemd[1]: Started RPC Bind.
[  OK  ] Started RPC Bind.
[    6.059330] systemd[1]: Started Journal Service.
[  OK  ] Started Journal Service.
[  OK  ] Mounted Huge Pages File System.[    6.086697] EXT4-fs (mmcblk1p2): re-mounted 3a6947ba-91a3-4915-9b08-f9977d7f422b r/w. Quota mode: none.

[  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Mounted Temporary Directory /tmp.
[  OK  ] Finished Create List of Static Device Nodes.
[  OK  ] Finished Load Kernel Module configfs.
[  OK  ] Finished Load Kernel Module drm.
[  OK  ] Finished Load Kernel Module fuse.
[FAILED] Failed to start Start psplash boot splash screen.
See 'systemctl status psplash-start.service' for details.
[DEPEND] Dependency failed for Start psplas…temd progress communication helper.
[  OK  ] Finished Load Kernel Modules.
[  OK  ] Finished Generate network units from Kernel command line.
[  OK  ] Finished Remount Root and Kernel File Systems.
         Mounting FUSE Control File System...
         Mounting Kernel Configuration File System...
         Starting Flush Journal to Persistent Storage...
         Starting Apply Kernel Variables...
         Starting Create Static Device Nodes in /dev gr[    6.503201] systemd-journald[117]: Received client request to flush runtime journal.
acefully...
[  OK  ] Finished Coldplug All udev Devices.
[  OK  ] Mounted FUSE Control File System.
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Finished Flush Journal to Persistent Storage.
[  OK  ] Finished Apply Kernel Variables.
[  OK  ] Finished Create Static Device Nodes in /dev gracefully.
         Starting Create Static Device Nodes in /dev...
[  OK  ] Finished Create Static Device Nodes in /dev.
[  OK  ] Reached target Preparation for Local File Systems.
         Mounting /var/volatile...
[    6.744148] audit: type=1334 audit(1709054766.496:2): prog-id=6 op=LOAD
[    6.751208] audit: type=1334 audit(1709054766.504:3): prog-id=7 op=LOAD
         Starting Rule-based Manager for Device Events and Files...
[  OK  ] Mounted /var/volatile.
         Starting Load/Save OS Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Finished Load/Save OS Random Seed.
[  OK  ] Finished Create Volatile Files and Directories.
[    6.941906] audit: type=1334 audit(1709054766.692:4): prog-id=8 op=LOAD
         Starting Network Name Resolution...
[    6.980748] audit: type=1334 audit(1709054766.732:5): prog-id=9 op=LOAD
         Starting Network Time Synchronization...
         Starting Record System Boot/Shutdown in UTMP...
[  OK  ] Started Rule-based Manager for Device Events and Files.
[    7.061301] audit: type=1334 audit(1709054766.812:6): prog-id=10 op=LOAD
[    7.070997] audit: type=1334 audit(1709054766.824:7): prog-id=11 op=LOAD
[    7.078625] audit: type=1334 audit(1709054766.828:8): prog-id=12 op=LOAD
         Starting User Database Manager...
[  OK  ] Finished Record System Boot/Shutdown in UTMP.
[  OK  ] Found device /dev/ttyS2.
[  OK  ] Started User Database Manager.
[  OK  ] Started Network Time Synchronization.
[  OK  ] Reached target System Time Set.
[  OK  ] Started Network Name Resolution.
[  OK  ] Reached target Host and Network Name Lookups.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily rotation of log files.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target Timer Units.
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[  OK  ] Listening on D-Bus System Message Bus Socket.
         Starting Docker Socket for the API...
[  OK  ] Listening on dropbear.socket.
[  OK  ] Listening on PC/SC Smart Card Daemon Activation Socket.
         Starting Weston socket...
[    7.906203] audit: type=1334 audit(1709076230.805:9): prog-id=13 op=LOAD
         Starting D-Bus System Message Bus...
         Starting Reboot and dump vmcore via kexec...
[  OK  ] Listening on Docker Socket for the API.
[  OK  ] Listening on Weston socket.
[  OK  ] Started D-Bus System Message Bus.
[  OK  ] Finished Reboot and dump vmcore via kexec.
[    8.117252] dbus-broker-lau[337]: memfd_create() called without MFD_EXEC or MFD_NOEXEC_SEAL set
[  OK  ] Reached target Socket Units.
[  OK  ] Reached target Basic System.
[  OK  ] Started Job spooling tools.
         Starting Avahi mDNS/DNS-SD Stack...
[  OK  ] Started Periodic Command Scheduler.
         Starting Print notice about GPLv3 packages...
         Starting IPv6 Packet Filtering Framework...
         Starting IPv4 Packet Filtering Framework...
[  OK  ] Started irqbalance daemon.
         Starting Telephony service...
         Starting Update pmic registers for…le safety feature on power rails...
         Starting Expand the rootfs partiti…to full size of the boot device....
[  OK  ] Started strongSwan IPsec IKEv1/IKEv2 daemon using ipsec.conf.
[    8.475827] audit: type=1334 audit(1709076231.377:10): prog-id=14 op=LOAD
[    8.489754] audit: type=1334 audit(1709076231.389:11): prog-id=15 op=LOAD
         Starting User Login Management...
         Starting Telnet Server...
[  OK  ] Finished IPv6 Packet Filtering Framework.
[  OK  ] Finished IPv4 Packet Filtering Framework.
[  OK  ] Reached target Preparation for Network.
         Starting Network Configuration...
[  OK  ] Started Avahi mDNS/DNS-SD Stack.
[  OK  ] Finished Telnet Server.
[  OK  ] Finished Update pmic registers for…able safety feature on power rails.
[    8.781607] k3-dsp-rproc 4d80800000.dsp: assigned reserved memory node vision-apps-c66-dma-memory@a9000000
[    8.798859] k3-dsp-rproc 4d80800000.dsp: configured DSP for IPC-only mode
[    8.811281] remoteproc remoteproc0: 4d80800000.dsp is available
[    8.822455] remoteproc remoteproc0: attaching to 4d80800000.dsp
[  OK  ] Started Telephony service.
[    8.845489] k3-dsp-rproc 4d80800000.dsp: DSP initialized in IPC-only mode
[    8.870214] rproc-virtio rproc-virtio.0.auto: assigned reserved memory node vision-apps-c66-dma-memory@a9000000
[    8.891913] virtio_rpmsg_bus virtio0: rpmsg host is online
[    8.895692] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0xd
[    8.905371] mc: Linux media interface: v0.10
[    8.917901] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
[    8.925748] rproc-virtio rproc-virtio.0.auto: registered virtio0 (type 7)
[    8.930415] omap_rng 4e10000.rng: Random Number Generator ver. 241b34c
[    8.935364] remoteproc remoteproc0: remote processor 4d80800000.dsp is now attached
[    8.949492] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vcc-supply regulator, assuming enabled
[    8.949501] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq-supply regulator, assuming enabled
[    8.949504] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq2-supply regulator, assuming enabled
[    8.982873] k3-dsp-rproc 4d81800000.dsp: assigned reserved memory node vision-apps-c66-dma-memory@a8000000
[    9.000518] scsi host0: ufshcd
[    9.015390] k3-dsp-rproc 4d81800000.dsp: configured DSP for IPC-only mode
[    9.029669] videodev: Linux video capture interface: v2.00
[    9.037102] remoteproc remoteproc1: 4d81800000.dsp is available
[    9.049867] remoteproc remoteproc1: attaching to 4d81800000.dsp
[    9.059529] k3-dsp-rproc 4d81800000.dsp: DSP initialized in IPC-only mode
[    9.066593] rproc-virtio rproc-virtio.3.auto: assigned reserved memory node vision-apps-c66-dma-memory@a8000000
[    9.078222] virtio_rpmsg_bus virtio1: rpmsg host is online
[    9.082285] virtio_rpmsg_bus virtio1: creating channel rpmsg_chrdev addr 0xd
[    9.094306] scsi 0:0:0:49488: Well-known LUN    SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    9.103456] rproc-virtio rproc-virtio.3.auto: registered virtio1 (type 7)
[    9.112686] scsi 0:0:0:49476: Well-known LUN    SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    9.123393] remoteproc remoteproc1: remote processor 4d81800000.dsp is now attached
[    9.132725] scsi 0:0:0:49456: Well-known LUN    SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    9.133239] k3-dsp-rproc 64800000.dsp: assigned reserved memory node vision-apps-c71-dma-memory@b2000000
[    9.152626] scsi 0:0:0:0: Direct-Access     SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    9.160681] k3-dsp-rproc 64800000.dsp: configured DSP for IPC-only mode
[    9.168844] sd 0:0:0:0: [sda] 61743104 4096-byte logical blocks: (253 GB/236 GiB)
[    9.171907] remoteproc remoteproc2: 64800000.dsp is available
[    9.182349] sd 0:0:0:0: [sda] Write Protect is off
[    9.182545] remoteproc remoteproc2: attaching to 64800000.dsp
[    9.193023] scsi 0:0:0:1: Direct-Access     SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    9.193486] remoteproc remoteproc2: unsupported resource 65538
[    9.207051] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, supports DPO and FUA
[    9.218143] sd 0:0:0:1: [sdb] 8192 4096-byte logical blocks: (33.6 MB/32.0 MiB)
[    9.225707] scsi 0:0:0:2: Direct-Access     SAMSUNG  KLUEGAJ1ZD-B0CQ  5900 PQ: 0 ANSI: 6
[    9.241815] sd 0:0:0:0: [sda] Preferred minimum I/O size 524288 bytes
[    9.243187] k3-dsp-rproc 64800000.dsp: DSP initialized in IPC-only mode

[    9.255303] sd 0:0:0:1: [sdb] Write Protect is off
[    9.257143] rproc-virtio rproc-virtio.4.auto: assigned reserved memory node vision-apps-c71-dma-memory@b2000000
[    9.262563] sd 0:0:0:0: [sda] Optimal transfer size 524288 bytes
[    9.270909] virtio_rpmsg_bus virtio2: rpmsg host is online
[    9.281883] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0xd
[    9.289892] rproc-virtio rproc-virtio.4.auto: registered virtio2 (type 7)
[    9.297478] remoteproc remoteproc2: remote processor 64800000.dsp is now attached
[    9.304911] sd 0:0:0:1: [sdb] Write cache: enabled, read cache: enabled, supports DPO and FUA
[    9.314452] sd 0:0:0:0: [sda] Attached SCSI disk
[    9.318557] sd 0:0:0:1: [sdb] Preferred minimum I/O size 524288 bytes
[    9.326584] sd 0:0:0:2: [sdc] 8192 4096-byte logical blocks: (33.6 MB/32.0 MiB)
[    9.336300] sd 0:0:0:2: [sdc] Write Protect is off
[    9.341844] sd 0:0:0:1: [sdb] Optimal transfer size 524288 bytes
[    9.352880] sd 0:0:0:2: [sdc] Write cache: enabled, read cache: enabled, supports DPO and FUA
[    9.363586] sd 0:0:0:2: [sdc] Preferred minimum I/O size 524288 bytes
[    9.370700] sd 0:0:0:1: [sdb] Attached SCSI disk
[    9.371818] sd 0:0:0:2: [sdc] Optimal transfer size 524288 bytes
[    9.386003] sd 0:0:0:2: [sdc] Attached SCSI disk
[    9.388571] platform 41000000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
[    9.447975] platform 41000000.r5f: configured R5F for IPC-only mode
[    9.469205] platform 41000000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a0000000
[    9.489031] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    9.499346] remoteproc remoteproc3: 41000000.r5f is available
[    9.534882] remoteproc remoteproc3: attaching to 41000000.r5f
[    9.546550] remoteproc remoteproc3: rsc table is truncated
[    9.556720] remoteproc remoteproc3: Failed to process resources: -22
[    9.564475] k3_r5_rproc bus@100000:bus@28380000:r5fss@41000000: rproc_add failed, ret = -22
[    9.574421] remoteproc remoteproc3: releasing 41000000.r5f
[    9.580218] k3_r5_rproc bus@100000:bus@28380000:r5fss@41000000: k3_r5_cluster_rproc_init failed, ret = -22
[    9.589982] k3_r5_rproc: probe of bus@100000:bus@28380000:r5fss@41000000 failed with error -22
[    9.602870] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    9.603257] platform 5c00000.r5f: configured R5F for IPC-only mode
[    9.608670] Bluetooth: Core ver 2.22
[    9.617866] platform 5c00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a2000000
[    9.618870] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
[    9.636037] NET: Registered PF_BLUETOOTH protocol family
[    9.640565] remoteproc remoteproc3: 5c00000.r5f is available
[    9.644756] Bluetooth: HCI device and connection manager initialized
[    9.661781] Bluetooth: HCI socket layer initialized
[    9.671877] Bluetooth: L2CAP socket layer initialized
[    9.680934] Bluetooth: SCO socket layer initialized
[    9.703324] remoteproc remoteproc3: attaching to 5c00000.r5f
[    9.711255] platform 5c00000.r5f: R5F core initialized in IPC-only mode
[    9.722221] rproc-virtio rproc-virtio.5.auto: assigned reserved memory node vision-apps-r5f-dma-memory@a2000000
[    9.733392] virtio_rpmsg_bus virtio3: rpmsg host is online
[    9.738949] virtio_rpmsg_bus virtio3: creating channel rpmsg_chrdev addr 0xd
[    9.747950] rproc-virtio rproc-virtio.5.auto: registered virtio3 (type 7)
[    9.755122] remoteproc remoteproc3: remote processor 5c00000.r5f is now attached
[    9.764321] platform 5d00000.r5f: configured R5F for IPC-only mode
[    9.771813] platform 5d00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a4000000
[    9.784230] remoteproc remoteproc4: 5d00000.r5f is available
[    9.790244] remoteproc remoteproc4: attaching to 5d00000.r5f
[    9.797886] platform 5d00000.r5f: R5F core initialized in IPC-only mode
[    9.805342] rproc-virtio rproc-virtio.6.auto: assigned reserved memory node vision-apps-r5f-dma-memory@a4000000
[    9.820131] virtio_rpmsg_bus virtio4: rpmsg host is online
[    9.824587] virtio_rpmsg_bus virtio4: creating channel rpmsg_chrdev addr 0xd
[    9.832899] virtio_rpmsg_bus virtio4: creating channel rpmsg_chrdev addr 0x15
[    9.839076] rproc-virtio rproc-virtio.6.auto: registered virtio4 (type 7)
[    9.840145] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0x15
[    9.851629] remoteproc remoteproc4: remote processor 5d00000.r5f is now attached
[    9.854128] virtio_rpmsg_bus virtio2: creating channel ti.ipc4.ping-pong addr 0xe
[    9.868939] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0x15
[    9.876148] virtio_rpmsg_bus virtio0: creating channel ti.ipc4.ping-pong addr 0xe
[    9.883779] virtio_rpmsg_bus virtio1: creating channel rpmsg_chrdev addr 0x15
[    9.890912] platform 5e00000.r5f: configured R5F for remoteproc mode
[    9.897340] virtio_rpmsg_bus virtio1: creating channel ti.ipc4.ping-pong addr 0xe
[    9.904884] virtio_rpmsg_bus virtio3: creating channel rpmsg_chrdev addr 0x15
[    9.912129] virtio_rpmsg_bus virtio4: creating channel ti.ipc4.ping-pong addr 0xe
[    9.912622] platform 5e00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a6000000
[    9.929697] remoteproc remoteproc5: 5e00000.r5f is available
[  OK  ] Finished Expand the rootfs partition to full size of the boot device..
[   10.005102] remoteproc remoteproc5: loading /lib/firmware/j7-main-r5f1_0-fw failed with error -22
[   10.011219] img_enc 4200000.video-encoder: vxe_enc_probe: using heap 1 for internal alloc
[   10.015507] remoteproc remoteproc5: Direct firmware load for j7-main-r5f1_0-fw failed with error -22
[   10.032574] remoteproc remoteproc5: powering up 5e00000.r5f
[   10.039045] remoteproc remoteproc5: loading /lib/firmware/j7-main-r5f1_0-fw failed with error -22
[   10.048555] remoteproc remoteproc5: Direct firmware load for j7-main-r5f1_0-fw failed with error -22
[   10.057416] img_dec 4300000.video-decoder: decoder registered as /dev/video0
[   10.058439] remoteproc remoteproc5: request_firmware failed: -22
[   10.077589] img_enc 4200000.video-encoder: encoder registered as /dev/video1
[  OK  ] Started Network Configuration.
[  OK  ] Reached target Network.
[   10.175471] remoteproc remoteproc6: b034000.pru is available
         Starting Enable and configure wl18xx bluetooth[   10.187486] remoteproc remoteproc7: b004000.rtu is available
 stack...
[   10.198159] remoteproc remoteproc8: b00a000.txpru is available

[  OK  ] Started Netperf Benchmark Server   10.212954] remoteproc remoteproc9: b038000.pru is available
m.
[   10.222278] remoteproc remoteproc10: b006000.rtu is available
[   10.233855] remoteproc remoteproc11: b00c000.txpru is available
[   10.234333] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [Generic Clause 45 PHY] (irq=POLL)
[   10.252002] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rgmii-rxid link mode
         Starting Simple Network Management Protocol (S[   10.264698] am65-cpsw-nuss 46000000.ethernet: config mac interface.
NMP) Daemon....
         Starting Permit User Sessions...
[   10.279705] remoteproc remoteproc12: b134000.pru is available
[   10.289939] remoteproc remoteproc13: b104000.rtu is available
[   10.297212] remoteproc remoteproc14: b10a000.txpru is available
[   10.303775] remoteproc remoteproc15: b138000.pru is available
[   10.309981] remoteproc remoteproc16: b106000.rtu is available
[   10.311092] remoteproc remoteproc17: b10c000.txpru is available
         Starting Virtual Console Setup...
[  OK  ] Finished Enable and configure wl18xx bluetooth stack.
[  OK  ] Finished Permit User Sessions.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
         Starting Weston, a Wayland compositor, as a system service...
[  OK  ] Listening on Load/Save RF Kill Switch Status /dev/rfkill Watch.
[FAILED] Failed to start Synchronize System and HW clocks.
See 'systemctl status sync-clocks.service' for details.
[   10.723435] virtio_rpmsg_bus virtio3: creating channel ti.ipc4.ping-pong addr 0xe
[   11.311193] am65-cpsw-nuss 46000000.ethernet eth0: Link is Up - Unknown/Unknown - flow control off
[  OK  ] Finished Virtual Console Setup.
[  OK  ] Created slice User Slice of UID 1000.
         Starting User Runtime Directory /run/user/1000...
[  OK  ] Finished User Runtime Directory /run/user/1000.
         Starting User Manager for UID 1000...
[   11.950515] k3_r5_rproc bus@100000:r5fss@5e00000: Timed out waiting for 5e00000.r5f core to power up!
[  OK  ] Started User Manager for UID 1000.
[  OK  ] Started Session c1 of User weston   12.429670] kauditd_printk_skb: 5 callbacks suppressed
0m.
[   12.429677] audit: type=1006 audit(1709076235.329:15): pid=512 uid=0 old-auid=4294967295 auid=1000 tty=tty7 old-ses=4294967295 ses=2 res=1
[   12.450790] audit: type=1300 audit(1709076235.329:15): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=fffff1b46a98 a2=4 a3=1 items=0 ppid=1 pid=512 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=tty7 ses=2 comm="(weston)" exe="/usr/lib/systemd/systemd-executor" key=(null)
[   12.477391] audit: type=1327 audit(1709076235.329:15): proctitle="(weston)"
[  OK  ] Created slice Slice /system/systemd-fsck.
         Expecting device /dev/mmcblk1p1...
[  OK  ] Found device /dev/mmcblk1p1.
         Starting File System Check on /dev/mmcblk1p1...
[FAILED] Failed to start Weston, a Wayland compositor, as a system service.
See 'systemctl status weston.service' for details.
[  OK  ] Finished File System Check on /dev/mmcblk1p1.
         Mounting /run/media/boot-mmcblk1p1...
[  OK  ] Mounted /run/media/boot-mmcblk1p1.
[  OK  ] Started Simple Network Management Protocol (SNMP) Daemon..
[  OK  ] Started containerd container runtime.

 _____                    _____           _         _
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|
              |___|                    |___|

Arago Project j721e-evm ttyS2

Arago 2023.10 j721e-evm ttyS2

j721e-evm login: ***************************************************************
***************************************************************
NOTICE: This file system contains the following GPL-3.0 packages:
        adwaita-icon-theme-symbolic
        autoconf
        bash-dev
        bash
        bc
        binutils
        cifs-utils
        coreutils-stdbuf
        coreutils
        cpio
        cpp-symlinks
        cpp
        dosfstools
        elfutils
        findutils
        g++-symlinks
        g++
        gawk
        gcc-symlinks
        gcc
        gdb
        gdbserver
        gettext
        glmark2
        gnu-config
        grub-common
        grub-editenv
        grub-efi
        gzip
        hidapi
        kbd-dev
        kbd-keymaps-pine
        less
        libasm1
        libatomic-dev
        libatomic1
        libbfd
        libdebuginfod1
        libdw1
        libelf1
        libgcc-s-dev
        libgcc1
        libgdbm-compat4
        libgdbm-dev
        libgdbm6
        libgettextlib
        libgettextsrc
        libgmp10
        libidn2-0
        libmpc3
        libmpfr6
        libopcodes
        libqt5charts-examples
        libqt5charts-plugins
        libqt5charts-qmlplugins
        libqt5charts5
        libqt5serialport-examples
        libqt5serialport-plugins
        libqt5serialport-qmlplugins
        libqt5serialport5
        libqt5svg-examples
        libqt5svg-plugins
        libqt5svg-qmlplugins
        libqt5svg5
        libqt5virtualkeyboard-plugins
        libqt5virtualkeyboard-qmlplugins
        libqt5virtualkeyboard5
        libreadline-dev
        libreadline8
        libstdc++-dev
        libstdc++6
        libunistring5
        m4
        make
        nettle
        parted
        piglit
        qt3d-plugins
        qt3d-qmlplugins
        qt3d
        qtbase-examples
        qtbase-plugins
        qtbase-qmlplugins
        qtbase
        qtconnectivity-plugins
        qtconnectivity-qmlplugins
        qtconnectivity
        qtdeclarative-plugins
        qtdeclarative-qmlplugins
        qtdeclarative-tools
        qtdeclarative
        qtgraphicaleffects-qmlplugins
        qtlocation-examples
        qtlocation-plugins
        qtlocation-qmlplugins
        qtlocation
        qtmultimedia-examples
        qtmultimedia-plugins
        qtmultimedia-qmlplugins
        qtmultimedia
        qtquics-qmlplugins.control
        qtquics2-plugins.control
        qtquics2-qmlplugins.control
        qtquics2.control
        qtscript-examples
        qtscript-plugins
        qtscript-qmlplugins
        qtscript
        qtwayland-examples
        qtwayland-plugins
        qtwayland-qmlplugins
        qtwayland
        tar
        which

If you do not wish to distribute GPL-3.0 components please remove
the above packages prior to distribution.  This can be done using
the opkg remove command.  i.e.:
    opkg remove <package>
Where <package> is the name printed in the list above

NOTE: If the package is a dependency of another package you
      will be notified of the dependent packages.  You should
      use the --force-removal-of-dependent-packages option to
      also remove the dependent packages as well
***************************************************************
***************************************************************
[   22.126811] platform gpio-regulator-tps659411: deferred probe pending

j721e-evm login: root
[   97.833712] audit: type=1006 audit(1709076320.733:16): pid=984 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=3 res=1
[   97.850806] audit: type=1300 audit(1709076320.733:16): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=fffffb292478 a2=1 a3=1 items=0 ppid=1 pid=984 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/usr/lib/systemd/systemd-executor" key=(null)
[   97.877369] audit: type=1327 audit(1709076320.733:16): proctitle="(systemd)"
[   97.886302] audit: type=1334 audit(1709076320.749:17): prog-id=18 op=LOAD
[   97.893328] audit: type=1300 audit(1709076320.749:17): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffefb8f058 a2=90 a3=0 items=0 ppid=1 pid=984 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)

[   97.919170] audit: type=1327 audit(1709076320.749:17): proctitle="(systemd)"
[   97.926409] audit: type=1334 audit(1709076320.749:18): prog-id=18 op=UNLOAD
[   97.933436] audit: type=1300 audit(1709076320.749:18): arch=c00000b7 syscall=57 success=yes exit=0 a0=8 a1=1 a2=0 a3=ffff8c0e8c60 items=0 ppid=1 pid=984 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)
[   97.959046] audit: type=1327 audit(1709076320.749:18): proctitle="(systemd)"
[   97.966101] audit: type=1334 audit(1709076320.749:19): prog-id=19 op=LOAD
root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet6 fe80::eebf:d0ff:febb:1e47  prefixlen 64  scopeid 0x20<link>
        ether ec:bf:d0:bb:1e:47  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 24  bytes 4266 (4.1 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 66  bytes 5732 (5.5 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 66  bytes 5732 (5.5 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

root@j721e-evm:~#

The following configuration still fails to see eth1, and an error log is displayed: probe of c000000.ethernet failed with error-110.

phy-names = "mac", "serdes";

I confirm that the "disable" under the serdes_wiz1 node has been deleted. Are there any registers that can confirm the enable status of serdes1?

root@j721e-evm:~# devmem2 0x05010414
/dev/mem opened.
Memory mapped at address 0xffffb8e74000.
Read at address 0x05010414 (0xffffb8e74414): 0x80000000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x0501048c
/dev/mem opened.
Memory mapped at address 0xffffbc856000.
Read at address 0x0501048C (0xffffbc85648c): 0x00000002
root@j721e-evm:~#

Hi,

In Serdes1 node you need to use wiz1 node for reset, but you are using wiz0.
Can you please check with below change.

- resets = <&serdes_wiz0 1>;
+ resets = <&serdes_wiz1 1>;

Best Regards,
Sudheer

I fixed this yesterday, and it was always correct in the previous test

&serdes1 {
	assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz1_pll1_refclk>;

	serdes1_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz1 1>;
	};
};

Hi,

Can you check by updating the SerDes node as below.

&serdes1 {

	serdes1_qsgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz1 1>;
		assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
		assigned-clock-parents = <&wiz1_pll1_refclk>;
	};
};

The above modification still does not find eth1, and an error log is displayed: probe of c000000.ethernet failed with error-110.

board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/configs/defconfig

CONFIG_PHY_AM654_SERDES=y
CONFIG_PHY_J721E_WIZ=y

CONFIG_PHY_J721E_WIZ is enable.

Hi,

zs xu said:

board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/configs/defconfig

Can you provide the defconfig info of yours.

Also, share the dtb file.

Best Regards,
Sudheer

CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_AUDIT=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
CONFIG_PREEMPT=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NUMA_BALANCING=y
CONFIG_MEMCG=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_USER_NS=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_PROFILING=y
CONFIG_KEXEC=y
CONFIG_KEXEC_FILE=y
CONFIG_CRASH_DUMP=y
CONFIG_ARCH_ACTIONS=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_ALPINE=y
CONFIG_ARCH_APPLE=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM2835=y
CONFIG_ARCH_BCM_IPROC=y
CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
CONFIG_ARCH_LG1K=y
CONFIG_ARCH_HISI=y
CONFIG_ARCH_KEEMBAY=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_NXP=y
CONFIG_ARCH_LAYERSCAPE=y
CONFIG_ARCH_MXC=y
CONFIG_ARCH_S32=y
CONFIG_ARCH_MA35=y
CONFIG_ARCH_NPCM=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_REALTEK=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_INTEL_SOCFPGA=y
CONFIG_ARCH_STM32=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_TESLA_FSD=y
CONFIG_ARCH_SPRD=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_THUNDER2=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_VISCONTI=y
CONFIG_ARCH_XGENE=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_ARM64_VA_BITS_48=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_SMT=y
CONFIG_NUMA=y
CONFIG_XEN=y
CONFIG_COMPAT=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_HIBERNATION=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPUFREQ_DT=y
CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_IMX_CPUFREQ_DT=m
CONFIG_ARM_MEDIATEK_CPUFREQ=y
CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
CONFIG_ARM_QCOM_CPUFREQ_HW=y
CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
CONFIG_ARM_SCMI_CPUFREQ=y
CONFIG_ARM_TEGRA186_CPUFREQ=y
CONFIG_QORIQ_CPUFREQ=y
CONFIG_ACPI=y
CONFIG_ACPI_HOTPLUG_MEMORY=y
CONFIG_ACPI_HMAT=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_PCIEAER=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MEMORY_HOTPLUG=y
CONFIG_MEMORY_HOTREMOVE=y
CONFIG_KSM=y
CONFIG_MEMORY_FAILURE=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_XDP_SOCKETS=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IPV6=m
CONFIG_NETFILTER=y
CONFIG_BRIDGE_NETFILTER=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_IP_VS=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_NET_DSA=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_GATE=m
CONFIG_HSR=m
CONFIG_QRTR_SMD=m
CONFIG_QRTR_TUN=m
CONFIG_CAN=m
CONFIG_BT=m
CONFIG_BT_HIDP=m
# CONFIG_BT_LE is not set
CONFIG_BT_LEDS=y
# CONFIG_BT_DEBUGFS is not set
CONFIG_BT_HCIBTUSB=m
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_QCOMSMD=m
CONFIG_BT_NXPUART=m
CONFIG_CFG80211=m
CONFIG_MAC80211=m
CONFIG_RFKILL=m
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_NFC=m
CONFIG_NFC_NCI=m
CONFIG_NFC_S3FWRN5_I2C=m
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PASID=y
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_ACPI=y
CONFIG_PCI_AARDVARK=y
CONFIG_PCIE_ALTERA=y
CONFIG_PCIE_ALTERA_MSI=y
CONFIG_PCIE_BRCMSTB=m
CONFIG_PCI_HOST_THUNDER_PEM=y
CONFIG_PCI_HOST_THUNDER_ECAM=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCIE_MEDIATEK_GEN3=m
CONFIG_PCI_TEGRA=y
CONFIG_PCIE_RCAR_HOST=y
CONFIG_PCIE_RCAR_EP=y
CONFIG_PCIE_ROCKCHIP_HOST=m
CONFIG_PCI_XGENE=y
CONFIG_PCI_J721E_HOST=y
CONFIG_PCI_J721E_EP=y
CONFIG_PCI_IMX6_HOST=y
CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_HISI=y
CONFIG_PCIE_KIRIN=y
CONFIG_PCIE_HISI_STB=y
CONFIG_PCIE_ARMADA_8K=y
CONFIG_PCIE_TEGRA194_HOST=m
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW_PLAT_EP=y
CONFIG_PCIE_QCOM=y
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
CONFIG_PCI_KEYSTONE_HOST=y
CONFIG_PCI_KEYSTONE_EP=y
CONFIG_PCIE_VISCONTI_HOST=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
CONFIG_PCI_EPF_TEST=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_HISILICON_LPC=y
CONFIG_TEGRA_ACONNECT=m
CONFIG_MHI_BUS_PCI_GENERIC=m
CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_INTEL_STRATIX10_SERVICE=y
CONFIG_INTEL_STRATIX10_RSU=m
CONFIG_EFI_CAPSULE_LOADER=y
CONFIG_IMX_SCU=y
CONFIG_IMX_SCU_PD=y
CONFIG_GNSS=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_NAND_BRCMNAND=m
CONFIG_MTD_NAND_FSL_IFC=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_HYPERBUS=m
CONFIG_HBMC_AM654=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=m
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_NVME=m
CONFIG_QCOM_COINCELL=m
CONFIG_QCOM_FASTRPC=m
CONFIG_SRAM=y
CONFIG_SRAM_DMA_HEAP=y
CONFIG_PCI_ENDPOINT_TEST=m
CONFIG_EEPROM_AT24=m
CONFIG_EEPROM_AT25=m
CONFIG_UACCE=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_HISI_SAS=y
CONFIG_SCSI_HISI_SAS_PCI=y
CONFIG_MEGARAID_SAS=y
CONFIG_SCSI_MPT3SAS=m
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_BRCM=m
CONFIG_AHCI_DWC=m
CONFIG_AHCI_CEVA=y
CONFIG_AHCI_MVEBU=y
CONFIG_AHCI_XGENE=y
CONFIG_AHCI_QORIQ=y
CONFIG_SATA_SIL24=y
CONFIG_SATA_RCAR=y
CONFIG_PATA_OF_PLATFORM=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_BLK_DEV_DM=m
CONFIG_DM_MIRROR=m
CONFIG_DM_ZERO=m
CONFIG_NETDEVICES=y
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_TUN=y
CONFIG_VETH=m
CONFIG_VIRTIO_NET=y
CONFIG_MHI_NET=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_MSCC_FELIX=m
CONFIG_AMD_XGBE=y
CONFIG_NET_XGENE=y
CONFIG_ATL1C=m
CONFIG_BCMGENET=m
CONFIG_BNX2X=m
CONFIG_SYSTEMPORT=m
CONFIG_MACB=y
CONFIG_THUNDER_NIC_PF=y
CONFIG_FEC=y
CONFIG_FSL_FMAN=y
CONFIG_FSL_DPAA_ETH=y
CONFIG_FSL_DPAA2_ETH=y
CONFIG_FSL_ENETC=y
CONFIG_FSL_ENETC_VF=y
CONFIG_FSL_ENETC_QOS=y
CONFIG_HIX5HD2_GMAC=y
CONFIG_HNS_DSAF=y
CONFIG_HNS_ENET=y
CONFIG_HNS3=y
CONFIG_HNS3_HCLGE=y
CONFIG_HNS3_ENET=y
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_IGB=y
CONFIG_IGBVF=y
CONFIG_MVNETA=y
CONFIG_MVPP2=y
CONFIG_SKY2=y
CONFIG_MLX4_EN=m
CONFIG_MLX5_CORE=m
CONFIG_MLX5_CORE_EN=y
CONFIG_QCOM_EMAC=m
CONFIG_RMNET=m
CONFIG_R8169=m
CONFIG_SH_ETH=y
CONFIG_RAVB=y
CONFIG_RENESAS_ETHER_SWITCH=y
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
CONFIG_SNI_AVE=y
CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
CONFIG_DWMAC_TEGRA=m
CONFIG_TI_CPSW_PROXY_CLIENT=m
CONFIG_TI_K3_AM65_CPSW_NUSS=y
CONFIG_TI_K3_AM65_CPSW_SWITCHDEV=y
CONFIG_TI_K3_AM65_CPTS=y
CONFIG_TI_AM65_CPSW_QOS=y
CONFIG_TI_ICSSG_PRUETH=m
CONFIG_QCOM_IPA=m
CONFIG_MESON_GXL_PHY=m
CONFIG_AQUANTIA_PHY=y
CONFIG_BCM54140_PHY=m
CONFIG_MARVELL_PHY=m
CONFIG_MARVELL_10G_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_MICROSEMI_PHY=y
CONFIG_AT803X_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_DP83867_PHY=y
CONFIG_DP83869_PHY=m
CONFIG_DP83TD510_PHY=y
CONFIG_VITESSE_PHY=y
CONFIG_CAN_FLEXCAN=m
CONFIG_CAN_M_CAN=m
CONFIG_CAN_M_CAN_PLATFORM=m
CONFIG_CAN_RCAR=m
CONFIG_CAN_RCAR_CANFD=m
CONFIG_CAN_MCP251XFD=m
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_ATH10K=m
CONFIG_ATH10K_PCI=m
CONFIG_ATH10K_SDIO=m
CONFIG_ATH10K_SNOC=m
CONFIG_WCN36XX=m
CONFIG_ATH11K=m
CONFIG_ATH11K_AHB=m
CONFIG_ATH11K_PCI=m
CONFIG_BRCMFMAC=m
CONFIG_IWLWIFI=m
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MT7921E=m
CONFIG_RSI_91X=m
CONFIG_WL18XX=m
CONFIG_CC33XX=m
CONFIG_CC33XX_SDIO=m
CONFIG_WLCORE_SDIO=m
CONFIG_WWAN=m
CONFIG_MHI_WWAN_CTRL=m
CONFIG_MHI_WWAN_MBIM=m
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_ADC=m
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_SNVS_PWRKEY=m
CONFIG_KEYBOARD_IMX_SC_KEY=m
CONFIG_KEYBOARD_CROS_EC=y
CONFIG_KEYBOARD_MTK_PMIC=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
CONFIG_TOUCHSCREEN_GOODIX=m
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_INPUT_MISC=y
CONFIG_INPUT_BBNSM_PWRKEY=m
CONFIG_INPUT_PM8941_PWRKEY=y
CONFIG_INPUT_PM8XXX_VIBRATOR=m
CONFIG_INPUT_TPS65219_PWRBUTTON=m
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=m
CONFIG_INPUT_HISI_POWERKEY=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_AMBAKMI=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=12
CONFIG_SERIAL_8250_RUNTIME_UARTS=12
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_BCM2835AUX=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_EM=y
CONFIG_SERIAL_8250_OMAP=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_UNIPHIER=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_MESON=y
CONFIG_SERIAL_MESON_CONSOLE=y
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_SERIAL_TEGRA=y
CONFIG_SERIAL_TEGRA_TCU=y
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SERIAL_QCOM_GENI=y
CONFIG_SERIAL_QCOM_GENI_CONSOLE=y
CONFIG_SERIAL_XILINX_PS_UART=y
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_FSL_LINFLEXUART=y
CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
CONFIG_SERIAL_STM32=y
CONFIG_SERIAL_STM32_CONSOLE=y
CONFIG_SERIAL_MVEBU_UART=y
CONFIG_SERIAL_OWL=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_IPMI_HANDLER=m
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_TCG_TPM=y
CONFIG_TCG_TIS=m
CONFIG_TCG_TIS_SPI=m
CONFIG_TCG_TIS_SPI_CR50=y
CONFIG_TCG_TIS_I2C_CR50=m
CONFIG_TCG_TIS_I2C_INFINEON=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_BCM2835=m
CONFIG_I2C_CADENCE=m
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_GPIO=m
CONFIG_I2C_IMX=y
CONFIG_I2C_IMX_LPI2C=y
CONFIG_I2C_MESON=y
CONFIG_I2C_MT65XX=y
CONFIG_I2C_MV64XXX=y
CONFIG_I2C_OMAP=y
CONFIG_I2C_OWL=y
CONFIG_I2C_PXA=y
CONFIG_I2C_QCOM_CCI=m
CONFIG_I2C_QCOM_GENI=m
CONFIG_I2C_QUP=y
CONFIG_I2C_RIIC=y
CONFIG_I2C_RK3X=y
CONFIG_I2C_RZV2M=m
CONFIG_I2C_S3C2410=y
CONFIG_I2C_SH_MOBILE=y
CONFIG_I2C_TEGRA=y
CONFIG_I2C_UNIPHIER_F=y
CONFIG_I2C_RCAR=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SPI=y
CONFIG_SPI_ARMADA_3700=y
CONFIG_SPI_BCM2835=m
CONFIG_SPI_BCM2835AUX=m
CONFIG_SPI_CADENCE_QUADSPI=y
CONFIG_SPI_DESIGNWARE=m
CONFIG_SPI_DW_DMA=y
CONFIG_SPI_DW_MMIO=m
CONFIG_SPI_FSL_LPSPI=y
CONFIG_SPI_FSL_QUADSPI=y
CONFIG_SPI_NXP_FLEXSPI=y
CONFIG_SPI_IMX=m
CONFIG_SPI_FSL_DSPI=y
CONFIG_SPI_MESON_SPICC=m
CONFIG_SPI_MESON_SPIFC=m
CONFIG_SPI_MT65XX=y
CONFIG_SPI_MTK_NOR=m
CONFIG_SPI_OMAP24XX=y
CONFIG_SPI_ORION=y
CONFIG_SPI_PL022=y
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_SFC=m
CONFIG_SPI_RPCIF=m
CONFIG_SPI_RSPI=m
CONFIG_SPI_RZV2M_CSI=m
CONFIG_SPI_QCOM_QSPI=m
CONFIG_SPI_QUP=y
CONFIG_SPI_QCOM_GENI=m
CONFIG_SPI_S3C64XX=y
CONFIG_SPI_SH_MSIOF=m
CONFIG_SPI_SUN6I=y
CONFIG_SPI_TEGRA210_QUAD=m
CONFIG_SPI_TEGRA114=m
CONFIG_SPI_SPIDEV=y
CONFIG_SPI_SLAVE=y
CONFIG_SPMI=y
CONFIG_SPMI_MTK_PMIF=m
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_RK805=m
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_OWL=y
CONFIG_PINCTRL_S700=y
CONFIG_PINCTRL_S900=y
CONFIG_PINCTRL_IMX8MM=y
CONFIG_PINCTRL_IMX8MN=y
CONFIG_PINCTRL_IMX8MP=y
CONFIG_PINCTRL_IMX8MQ=y
CONFIG_PINCTRL_IMX8QM=y
CONFIG_PINCTRL_IMX8QXP=y
CONFIG_PINCTRL_IMX8DXL=y
CONFIG_PINCTRL_IMX8ULP=y
CONFIG_PINCTRL_IMX93=y
CONFIG_PINCTRL_MSM=y
CONFIG_PINCTRL_IPQ5018=y
CONFIG_PINCTRL_IPQ5332=y
CONFIG_PINCTRL_IPQ8074=y
CONFIG_PINCTRL_IPQ6018=y
CONFIG_PINCTRL_IPQ9574=y
CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8953=y
CONFIG_PINCTRL_MSM8976=y
CONFIG_PINCTRL_MSM8994=y
CONFIG_PINCTRL_MSM8996=y
CONFIG_PINCTRL_MSM8998=y
CONFIG_PINCTRL_QCM2290=y
CONFIG_PINCTRL_QCS404=y
CONFIG_PINCTRL_QDF2XXX=y
CONFIG_PINCTRL_QDU1000=y
CONFIG_PINCTRL_SA8775P=y
CONFIG_PINCTRL_SC7180=y
CONFIG_PINCTRL_SC7280=y
CONFIG_PINCTRL_SC8180X=y
CONFIG_PINCTRL_SC8280XP=y
CONFIG_PINCTRL_SDM660=y
CONFIG_PINCTRL_SDM670=y
CONFIG_PINCTRL_SDM845=y
CONFIG_PINCTRL_SM6115=y
CONFIG_PINCTRL_SM6125=y
CONFIG_PINCTRL_SM6350=y
CONFIG_PINCTRL_SM6375=y
CONFIG_PINCTRL_SM8150=y
CONFIG_PINCTRL_SM8250=y
CONFIG_PINCTRL_SM8350=y
CONFIG_PINCTRL_SM8450=y
CONFIG_PINCTRL_SM8550=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_PINCTRL_LPASS_LPI=m
CONFIG_PINCTRL_SC7280_LPASS_LPI=m
CONFIG_PINCTRL_SM8250_LPASS_LPI=m
CONFIG_PINCTRL_SM8450_LPASS_LPI=m
CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
CONFIG_PINCTRL_SM8550_LPASS_LPI=m
CONFIG_GPIO_ALTERA=m
CONFIG_GPIO_DAVINCI=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_MB86S7X=y
CONFIG_GPIO_MPC8XXX=y
CONFIG_GPIO_MXC=y
CONFIG_GPIO_PL061=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_GPIO_VISCONTI=y
CONFIG_GPIO_WCD934X=m
CONFIG_GPIO_XGENE=y
CONFIG_GPIO_XGENE_SB=y
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_BD9571MWV=m
CONFIG_GPIO_MAX77620=y
CONFIG_GPIO_SL28CPLD=m
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_RESET_QCOM_PON=m
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_NVMEM_REBOOT_MODE=m
CONFIG_BATTERY_QCOM_BATTMGR=m
CONFIG_BATTERY_SBS=m
CONFIG_BATTERY_BQ27XXX=y
CONFIG_BATTERY_MAX17042=m
CONFIG_CHARGER_MT6360=m
CONFIG_CHARGER_BQ25890=m
CONFIG_CHARGER_BQ25980=m
CONFIG_CHARGER_RK817=m
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_SENSORS_GPIO_FAN=m
CONFIG_SENSORS_JC42=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_PWM_FAN=m
CONFIG_SENSORS_RASPBERRYPI_HWMON=m
CONFIG_SENSORS_SL28CPLD=m
CONFIG_SENSORS_INA2XX=m
CONFIG_SENSORS_INA3221=m
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_IMX_SC_THERMAL=m
CONFIG_IMX8MM_THERMAL=m
CONFIG_K3_THERMAL=m
CONFIG_QORIQ_THERMAL=m
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=m
CONFIG_RCAR_THERMAL=y
CONFIG_RCAR_GEN3_THERMAL=y
CONFIG_RZG2L_THERMAL=y
CONFIG_ARMADA_THERMAL=y
CONFIG_BCM2711_THERMAL=m
CONFIG_BCM2835_THERMAL=m
CONFIG_BRCMSTB_THERMAL=m
CONFIG_EXYNOS_THERMAL=y
CONFIG_TEGRA_SOCTHERM=m
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_QCOM_TSENS=y
CONFIG_QCOM_SPMI_ADC_TM5=m
CONFIG_QCOM_SPMI_TEMP_ALARM=m
CONFIG_QCOM_LMH=m
CONFIG_UNIPHIER_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_SL28CPLD_WATCHDOG=m
CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_ARM_SBSA_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_K3_RTI_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
CONFIG_NPCM7XX_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_IMX_SC_WDT=m
CONFIG_IMX7ULP_WDT=m
CONFIG_QCOM_WDT=m
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
CONFIG_ARM_SMC_WATCHDOG=y
CONFIG_RENESAS_WDT=y
CONFIG_RENESAS_RZG2LWDT=y
CONFIG_UNIPHIER_WATCHDOG=y
CONFIG_PM8916_WATCHDOG=m
CONFIG_BCM2835_WDT=y
CONFIG_BCM7038_WDT=m
CONFIG_MFD_ALTERA_SYSMGR=y
CONFIG_MFD_BD9571MWV=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
CONFIG_MFD_EXYNOS_LPASS=m
CONFIG_MFD_HI6421_PMIC=y
CONFIG_MFD_HI655X_PMIC=y
CONFIG_MFD_MAX77620=y
CONFIG_MFD_MT6360=y
CONFIG_MFD_MT6397=y
CONFIG_MFD_SPMI_PMIC=y
CONFIG_MFD_RK8XX_I2C=y
CONFIG_MFD_RK8XX_SPI=y
CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_SL28CPLD=y
CONFIG_RZ_MTU3=y
CONFIG_MFD_TI_AM335X_TSCADC=m
CONFIG_MFD_TPS65219=y
CONFIG_MFD_TPS6594_I2C=y
CONFIG_MFD_ROHM_BD718XX=y
CONFIG_MFD_WCD934X=m
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_BD718XX=y
CONFIG_REGULATOR_BD9571MWV=y
CONFIG_REGULATOR_CROS_EC=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_HI6421V530=y
CONFIG_REGULATOR_HI655X=y
CONFIG_REGULATOR_MAX77620=y
CONFIG_REGULATOR_MAX8973=y
CONFIG_REGULATOR_MP8859=y
CONFIG_REGULATOR_MT6315=m
CONFIG_REGULATOR_MT6357=y
CONFIG_REGULATOR_MT6358=y
CONFIG_REGULATOR_MT6359=y
CONFIG_REGULATOR_MT6360=y
CONFIG_REGULATOR_MT6397=y
CONFIG_REGULATOR_PCA9450=y
CONFIG_REGULATOR_PF8X00=y
CONFIG_REGULATOR_PFUZE100=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_QCOM_RPMH=y
CONFIG_REGULATOR_QCOM_SMD_RPM=y
CONFIG_REGULATOR_QCOM_SPMI=y
CONFIG_REGULATOR_RAA215300=y
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_TPS65132=m
CONFIG_REGULATOR_TPS65219=y
CONFIG_REGULATOR_VCTRL=m
CONFIG_RC_CORE=m
CONFIG_RC_DECODERS=y
CONFIG_RC_DEVICES=y
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_MESON=m
CONFIG_IR_SUNXI=m
CONFIG_MEDIA_SUPPORT=m
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_DVB_NET is not set
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SDR_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_CADENCE_CSI2RX=m
CONFIG_VIDEO_WAVE_VPU=m
CONFIG_VIDEO_IMG_VXD_DEC=m
CONFIG_VIDEO_IMG_VXE_ENC=m
CONFIG_VIDEO_E5010_JPEG_ENC=m
CONFIG_VIDEO_MEDIATEK_JPEG=m
CONFIG_VIDEO_MEDIATEK_VCODEC=m
CONFIG_VIDEO_IMX7_CSI=m
CONFIG_VIDEO_IMX_MIPI_CSIS=m
CONFIG_VIDEO_IMX8_ISI=m
CONFIG_VIDEO_IMX8_ISI_M2M=y
CONFIG_VIDEO_QCOM_CAMSS=m
CONFIG_VIDEO_QCOM_VENUS=m
CONFIG_VIDEO_RCAR_ISP=m
CONFIG_VIDEO_RCAR_CSI2=m
CONFIG_VIDEO_RCAR_VIN=m
CONFIG_VIDEO_RZG2L_CSI2=m
CONFIG_VIDEO_RZG2L_CRU=m
CONFIG_VIDEO_RENESAS_FCP=m
CONFIG_VIDEO_RENESAS_FDP1=m
CONFIG_VIDEO_RENESAS_VSP1=m
CONFIG_VIDEO_RCAR_DRIF=m
CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
CONFIG_VIDEO_SUN6I_CSI=m
CONFIG_VIDEO_TI_J721E_CSI2RX=m
CONFIG_VIDEO_HANTRO=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX390=m
CONFIG_VIDEO_IMX412=m
CONFIG_VIDEO_OV2312=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OX05B1S=m
CONFIG_VIDEO_DS90UB953=m
CONFIG_VIDEO_DS90UB960=m
CONFIG_DRM=m
CONFIG_DRM_I2C_NXP_TDA998X=m
CONFIG_DRM_HDLCD=m
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
CONFIG_DRM_NOUVEAU=m
CONFIG_DRM_EXYNOS=m
CONFIG_DRM_EXYNOS5433_DECON=y
CONFIG_DRM_EXYNOS7_DECON=y
CONFIG_DRM_EXYNOS_DSI=y
# CONFIG_DRM_EXYNOS_DP is not set
CONFIG_DRM_EXYNOS_HDMI=y
CONFIG_DRM_EXYNOS_MIC=y
CONFIG_DRM_ROCKCHIP=m
CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_DRM_RCAR_DU=m
CONFIG_DRM_RCAR_DW_HDMI=m
CONFIG_DRM_RZG2L_MIPI_DSI=m
CONFIG_DRM_SUN4I=m
CONFIG_DRM_MSM=m
CONFIG_DRM_TEGRA=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_PANEL_EDP=m
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
CONFIG_DRM_LONTIUM_LT8912B=m
CONFIG_DRM_LONTIUM_LT9611=m
CONFIG_DRM_LONTIUM_LT9611UXC=m
CONFIG_DRM_ITE_IT66121=m
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_PARADE_PS8640=m
CONFIG_DRM_SII902X=m
CONFIG_DRM_SIMPLE_BRIDGE=m
CONFIG_DRM_THINE_THC63LVD1024=m
CONFIG_DRM_TOSHIBA_TC358762=m
CONFIG_DRM_TOSHIBA_TC358767=m
CONFIG_DRM_TOSHIBA_TC358768=m
CONFIG_DRM_TI_TFP410=m
CONFIG_DRM_TI_SN65DSI83=m
CONFIG_DRM_TI_SN65DSI86=m
CONFIG_DRM_ANALOGIX_ANX7625=m
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_CDNS_DSI=m
CONFIG_DRM_CDNS_MHDP8546=m
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_IMX_DCSS=m
CONFIG_DRM_V3D=m
CONFIG_DRM_VC4=m
CONFIG_DRM_ETNAVIV=m
CONFIG_DRM_HISI_HIBMC=m
CONFIG_DRM_HISI_KIRIN=m
CONFIG_DRM_MEDIATEK=m
CONFIG_DRM_MEDIATEK_HDMI=m
CONFIG_DRM_MXSFB=m
CONFIG_DRM_IMX_LCDIF=m
CONFIG_DRM_MESON=m
CONFIG_DRM_PL111=m
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
CONFIG_DRM_TIDSS=m
CONFIG_FB=y
CONFIG_FB_EFI=y
CONFIG_FB_SIMPLE=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_LP855X=m
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_ALOOP=m
CONFIG_SND_HDA_TEGRA=m
CONFIG_SND_HDA_CODEC_HDMI=m
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=y
CONFIG_SND_BCM2835_SOC_I2S=m
CONFIG_SND_SOC_FSL_ASRC=m
CONFIG_SND_SOC_FSL_MICFIL=m
CONFIG_SND_SOC_FSL_EASRC=m
CONFIG_SND_IMX_SOC=m
CONFIG_SND_SOC_IMX_SGTL5000=m
CONFIG_SND_SOC_IMX_SPDIF=m
CONFIG_SND_SOC_FSL_ASOC_CARD=m
CONFIG_SND_SOC_IMX_AUDMIX=m
CONFIG_SND_SOC_MT8183=m
CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A=m
CONFIG_SND_SOC_MT8183_DA7219_MAX98357A=m
CONFIG_SND_SOC_MT8192=m
CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m
CONFIG_SND_MESON_AXG_SOUND_CARD=m
CONFIG_SND_MESON_GX_SOUND_CARD=m
CONFIG_SND_SOC_QCOM=m
CONFIG_SND_SOC_APQ8016_SBC=m
CONFIG_SND_SOC_MSM8996=m
CONFIG_SND_SOC_SDM845=m
CONFIG_SND_SOC_SM8250=m
CONFIG_SND_SOC_SC7180=m
CONFIG_SND_SOC_SC7280=m
CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
CONFIG_SND_SOC_SAMSUNG=y
CONFIG_SND_SOC_RCAR=m
CONFIG_SND_SOC_RZ=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SOC_TEGRA=m
CONFIG_SND_SOC_TEGRA210_AHUB=m
CONFIG_SND_SOC_TEGRA210_DMIC=m
CONFIG_SND_SOC_TEGRA210_I2S=m
CONFIG_SND_SOC_TEGRA210_OPE=m
CONFIG_SND_SOC_TEGRA186_ASRC=m
CONFIG_SND_SOC_TEGRA186_DSPK=m
CONFIG_SND_SOC_TEGRA210_ADMAIF=m
CONFIG_SND_SOC_TEGRA210_MVC=m
CONFIG_SND_SOC_TEGRA210_SFC=m
CONFIG_SND_SOC_TEGRA210_AMX=m
CONFIG_SND_SOC_TEGRA210_ADX=m
CONFIG_SND_SOC_TEGRA210_MIXER=m
CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
CONFIG_SND_SOC_J721E_EVM=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SOC_DA7213=m
CONFIG_SND_SOC_ES7134=m
CONFIG_SND_SOC_ES7241=m
CONFIG_SND_SOC_ES8316=m
CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_RK817=m
CONFIG_SND_SOC_RT5640=m
CONFIG_SND_SOC_RT5659=m
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
CONFIG_SND_SOC_SIMPLE_MUX=m
CONFIG_SND_SOC_TAS2552=m
CONFIG_SND_SOC_TAS571X=m
CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
CONFIG_SND_SOC_TLV320AIC3X_I2C=m
CONFIG_SND_SOC_WCD9335=m
CONFIG_SND_SOC_WCD934X=m
CONFIG_SND_SOC_WM8524=m
CONFIG_SND_SOC_WM8904=m
CONFIG_SND_SOC_WM8960=m
CONFIG_SND_SOC_WM8962=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WSA881X=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD2=m
CONFIG_HID_MULTITOUCH=m
CONFIG_I2C_HID_ACPI=m
CONFIG_I2C_HID_OF=m
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI_RENESAS=m
CONFIG_USB_XHCI_RZV2M=y
CONFIG_USB_XHCI_TEGRA=y
CONFIG_USB_BRCMSTB=m
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_EXYNOS=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_EXYNOS=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_RENESAS_USBHS_HCD=m
CONFIG_USB_RENESAS_USBHS=m
CONFIG_USB_ACM=m
CONFIG_USB_STORAGE=y
CONFIG_USB_CDNS_SUPPORT=m
CONFIG_USB_CDNS3=m
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_USB_MTU3=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC2=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_ISP1760=y
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_QCOM_EUD=m
CONFIG_USB_HSIC_USB3503=y
CONFIG_USB_ONBOARD_HUB=m
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=32
CONFIG_USB_RENESAS_USBHS_UDC=m
CONFIG_USB_RZV2M_USB3DRD=y
CONFIG_USB_RENESAS_USB3=m
CONFIG_USB_TEGRA_XUDC=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_G_NCM=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_CDC=y
CONFIG_TYPEC=m
CONFIG_TYPEC_TCPM=m
CONFIG_TYPEC_TCPCI=m
CONFIG_TYPEC_FUSB302=m
CONFIG_TYPEC_UCSI=m
CONFIG_UCSI_CCG=m
CONFIG_UCSI_PMIC_GLINK=m
CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_MUX_FSA4480=m
CONFIG_TYPEC_MUX_GPIO_SBU=m
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ACPI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_ESDHC=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_OF_SPARX5=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
CONFIG_MMC_SDHCI_TEGRA=y
CONFIG_MMC_SDHCI_F_SDH30=y
CONFIG_MMC_MESON_GX=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_MMC_SPI=y
CONFIG_MMC_SDHI=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_EXYNOS=y
CONFIG_MMC_DW_HI3798CV200=y
CONFIG_MMC_DW_K3=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SUNXI=y
CONFIG_MMC_BCM2835=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MMC_OWL=y
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFS_BSG=y
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_CDNS_PLATFORM=m
CONFIG_SCSI_UFS_QCOM=m
CONFIG_SCSI_UFS_HISI=y
CONFIG_SCSI_UFS_RENESAS=m
CONFIG_SCSI_UFS_TI_J721E=y
CONFIG_SCSI_UFS_EXYNOS=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_MULTICOLOR=m
CONFIG_LEDS_LM3692X=m
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_QCOM_LPG=m
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_EDAC=y
CONFIG_EDAC_GHES=y
CONFIG_EDAC_LAYERSCAPE=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_HYM8563=m
CONFIG_RTC_DRV_MAX77686=y
CONFIG_RTC_DRV_RK808=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_M41T80=m
CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RV3028=m
CONFIG_RTC_DRV_RV8803=m
CONFIG_RTC_DRV_S5M=y
CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_CROS_EC=y
CONFIG_RTC_DRV_FSL_FTM_ALARM=m
CONFIG_RTC_DRV_S3C=y
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_SUN6I=y
CONFIG_RTC_DRV_ARMADA38X=y
CONFIG_RTC_DRV_PM8XXX=m
CONFIG_RTC_DRV_TEGRA=y
CONFIG_RTC_DRV_SNVS=m
CONFIG_RTC_DRV_BBNSM=m
CONFIG_RTC_DRV_IMX_SC=m
CONFIG_RTC_DRV_MT6397=m
CONFIG_RTC_DRV_XGENE=y
CONFIG_RTC_DRV_TI_K3=m
CONFIG_DMADEVICES=y
CONFIG_DMA_BCM2835=y
CONFIG_DMA_SUN6I=m
CONFIG_FSL_EDMA=y
CONFIG_IMX_SDMA=m
CONFIG_K3_DMA=y
CONFIG_MV_XOR=y
CONFIG_MV_XOR_V2=y
CONFIG_OWL_DMA=y
CONFIG_PL330_DMA=y
CONFIG_TEGRA186_GPC_DMA=y
CONFIG_TEGRA20_APB_DMA=y
CONFIG_TEGRA210_ADMA=m
CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_GPI_DMA=m
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
CONFIG_RCAR_DMAC=y
CONFIG_RENESAS_USB_DMAC=m
CONFIG_RZ_DMAC=y
CONFIG_TI_K3_UDMA=y
CONFIG_TI_K3_UDMA_GLUE_LAYER=y
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
CONFIG_DMABUF_HEAPS_CARVEOUT=y
CONFIG_VFIO=y
CONFIG_VFIO_PCI=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_MMIO=y
CONFIG_XEN_GNTDEV=y
CONFIG_XEN_GRANT_DEV_ALLOC=y
CONFIG_STAGING=y
CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_MAX96712=m
CONFIG_CHROME_PLATFORMS=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_RPMSG=m
CONFIG_CROS_EC_SPI=y
CONFIG_CROS_EC_CHARDEV=m
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCPI=y
CONFIG_COMMON_CLK_CS2000_CP=y
CONFIG_COMMON_CLK_FSL_SAI=y
CONFIG_COMMON_CLK_S2MPS11=y
CONFIG_COMMON_CLK_PWM=y
CONFIG_COMMON_CLK_RS9_PCIE=y
CONFIG_COMMON_CLK_VC5=y
CONFIG_COMMON_CLK_BD718XX=m
CONFIG_CLK_RASPBERRYPI=m
CONFIG_CLK_IMX8MM=y
CONFIG_CLK_IMX8MN=y
CONFIG_CLK_IMX8MP=y
CONFIG_CLK_IMX8MQ=y
CONFIG_CLK_IMX8QXP=y
CONFIG_CLK_IMX8ULP=y
CONFIG_CLK_IMX93=y
CONFIG_TI_SCI_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_QCOM_A53PLL=y
CONFIG_QCOM_CLK_APCS_MSM8916=y
CONFIG_QCOM_CLK_APCC_MSM8996=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_5332=y
CONFIG_IPQ_GCC_6018=y
CONFIG_IPQ_GCC_8074=y
CONFIG_IPQ_GCC_9574=y
CONFIG_MSM_GCC_8916=y
CONFIG_MSM_MMCC_8994=m
CONFIG_MSM_GCC_8994=y
CONFIG_MSM_GCC_8996=y
CONFIG_MSM_MMCC_8996=m
CONFIG_MSM_GCC_8998=y
CONFIG_MSM_MMCC_8998=m
CONFIG_QCM_GCC_2290=y
CONFIG_QCM_DISPCC_2290=m
CONFIG_QCS_GCC_404=y
CONFIG_SC_DISPCC_8280XP=m
CONFIG_SA_GCC_8775P=y
CONFIG_SA_GPUCC_8775P=m
CONFIG_SC_GCC_7180=y
CONFIG_SC_GCC_7280=y
CONFIG_SC_GCC_8180X=y
CONFIG_SC_GCC_8280XP=y
CONFIG_SC_GPUCC_8280XP=m
CONFIG_SC_LPASSCC_8280XP=m
CONFIG_SDM_CAMCC_845=m
CONFIG_SDM_GPUCC_845=y
CONFIG_SDM_VIDEOCC_845=y
CONFIG_SDM_DISPCC_845=y
CONFIG_SDM_LPASSCC_845=m
CONFIG_SM_CAMCC_8250=m
CONFIG_SM_DISPCC_6115=m
CONFIG_SM_DISPCC_8250=y
CONFIG_SM_DISPCC_8450=m
CONFIG_SM_DISPCC_8550=m
CONFIG_SM_GCC_6115=y
CONFIG_SM_GCC_8350=y
CONFIG_SM_GCC_8450=y
CONFIG_SM_GCC_8550=y
CONFIG_SM_GPUCC_6115=m
CONFIG_SM_GPUCC_8150=y
CONFIG_SM_GPUCC_8250=y
CONFIG_SM_TCSRCC_8550=y
CONFIG_SM_VIDEOCC_8250=y
CONFIG_QCOM_HFPLL=y
CONFIG_CLK_GFM_LPASS_SM8250=m
CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_TEGRA186_TIMER=y
CONFIG_RENESAS_OSTM=y
CONFIG_ARM_MHU=y
CONFIG_IMX_MBOX=y
CONFIG_PLATFORM_MHU=y
CONFIG_OMAP2PLUS_MBOX=y
CONFIG_BCM2835_MBOX=y
CONFIG_QCOM_APCS_IPC=y
CONFIG_QCOM_IPCC=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_V3=y
CONFIG_MTK_IOMMU=y
CONFIG_QCOM_IOMMU=y
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
CONFIG_IMX_REMOTEPROC=y
CONFIG_MTK_SCP=m
CONFIG_QCOM_Q6V5_ADSP=m
CONFIG_QCOM_Q6V5_MSS=m
CONFIG_QCOM_Q6V5_PAS=m
CONFIG_QCOM_SYSMON=m
CONFIG_QCOM_WCNSS_PIL=m
CONFIG_TI_K3_DSP_REMOTEPROC=m
CONFIG_TI_K3_M4_REMOTEPROC=m
CONFIG_TI_K3_R5_REMOTEPROC=m
CONFIG_RPMSG_CHAR=m
CONFIG_RPMSG_CTRL=m
CONFIG_RPMSG_QCOM_GLINK_RPM=y
CONFIG_RPMSG_QCOM_GLINK_SMEM=m
CONFIG_RPMSG_QCOM_SMD=y
CONFIG_RPMSG_VIRTIO=y
CONFIG_RPMSG_PRU=m
CONFIG_SOUNDWIRE=m
CONFIG_SOUNDWIRE_QCOM=m
CONFIG_OWL_PM_DOMAINS=y
CONFIG_RASPBERRYPI_POWER=y
CONFIG_FSL_DPAA=y
CONFIG_FSL_MC_DPIO=y
CONFIG_FSL_RCPM=y
CONFIG_MTK_CMDQ=m
CONFIG_MTK_DEVAPC=m
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_SVS=m
CONFIG_QCOM_AOSS_QMP=y
CONFIG_QCOM_COMMAND_DB=y
CONFIG_QCOM_CPR=y
CONFIG_QCOM_GENI_SE=y
CONFIG_QCOM_LLCC=m
CONFIG_QCOM_OCMEM=m
CONFIG_QCOM_PMIC_GLINK=m
CONFIG_QCOM_RMTFS_MEM=m
CONFIG_QCOM_RPMH=y
CONFIG_QCOM_RPMHPD=y
CONFIG_QCOM_RPMPD=y
CONFIG_QCOM_SMEM=y
CONFIG_QCOM_SMD_RPM=y
CONFIG_QCOM_SMP2P=y
CONFIG_QCOM_SMSM=y
CONFIG_QCOM_SOCINFO=m
CONFIG_QCOM_SPM=m
CONFIG_QCOM_STATS=m
CONFIG_QCOM_WCNSS_CTRL=m
CONFIG_QCOM_APR=m
CONFIG_QCOM_ICC_BWMON=m
CONFIG_ARCH_R8A77995=y
CONFIG_ARCH_R8A77990=y
CONFIG_ARCH_R8A77951=y
CONFIG_ARCH_R8A77965=y
CONFIG_ARCH_R8A77960=y
CONFIG_ARCH_R8A77961=y
CONFIG_ARCH_R8A779F0=y
CONFIG_ARCH_R8A77980=y
CONFIG_ARCH_R8A77970=y
CONFIG_ARCH_R8A779A0=y
CONFIG_ARCH_R8A779G0=y
CONFIG_ARCH_R8A774C0=y
CONFIG_ARCH_R8A774E1=y
CONFIG_ARCH_R8A774A1=y
CONFIG_ARCH_R8A774B1=y
CONFIG_ARCH_R9A07G043=y
CONFIG_ARCH_R9A07G044=y
CONFIG_ARCH_R9A07G054=y
CONFIG_ARCH_R9A09G011=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ARCH_TEGRA_132_SOC=y
CONFIG_ARCH_TEGRA_210_SOC=y
CONFIG_ARCH_TEGRA_186_SOC=y
CONFIG_ARCH_TEGRA_194_SOC=y
CONFIG_ARCH_TEGRA_234_SOC=y
CONFIG_TI_SCI_PM_DOMAINS=y
CONFIG_TI_PRUSS=m
CONFIG_ARM_IMX_BUS_DEVFREQ=y
CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m
CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m
CONFIG_EXTCON_PTN5150=m
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
CONFIG_OMAP_GPMC=y
CONFIG_RENESAS_RPCIF=m
CONFIG_IIO=y
CONFIG_EXYNOS_ADC=y
CONFIG_IMX93_ADC=m
CONFIG_MAX9611=m
CONFIG_MEDIATEK_MT6577_AUXADC=m
CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
CONFIG_ROCKCHIP_SARADC=m
CONFIG_RZG2L_ADC=m
CONFIG_TI_ADS1015=m
CONFIG_TI_AM335X_ADC=m
CONFIG_IIO_CROS_EC_SENSORS_CORE=m
CONFIG_IIO_CROS_EC_SENSORS=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_CROS_EC_LIGHT_PROX=m
CONFIG_SENSORS_ISL29018=m
CONFIG_VCNL4000=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_CROS_EC_BARO=m
CONFIG_MPL3115=m
CONFIG_PWM=y
CONFIG_PWM_BCM2835=m
CONFIG_PWM_BRCMSTB=m
CONFIG_PWM_CROS_EC=m
CONFIG_PWM_IMX27=m
CONFIG_PWM_MESON=m
CONFIG_PWM_MTK_DISP=m
CONFIG_PWM_MEDIATEK=m
CONFIG_PWM_OMAP_DMTIMER=m
CONFIG_PWM_RCAR=m
CONFIG_PWM_RENESAS_TPU=m
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_RZ_MTU3=m
CONFIG_PWM_SAMSUNG=y
CONFIG_PWM_SL28CPLD=m
CONFIG_PWM_SUN4I=m
CONFIG_PWM_TEGRA=m
CONFIG_PWM_TIECAP=m
CONFIG_PWM_TIEHRPWM=m
CONFIG_PWM_VISCONTI=m
CONFIG_SL28CPLD_INTC=y
CONFIG_QCOM_PDC=y
CONFIG_QCOM_MPM=y
CONFIG_RESET_IMX7=y
CONFIG_RESET_QCOM_AOSS=y
CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_RESET_TI_SCI=y
CONFIG_PHY_XGENE=y
CONFIG_PHY_CAN_TRANSCEIVER=m
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_CADENCE_DPHY=m
CONFIG_PHY_CADENCE_DPHY_RX=m
CONFIG_PHY_CADENCE_SIERRA=y
CONFIG_PHY_MIXEL_MIPI_DPHY=m
CONFIG_PHY_FSL_IMX8M_PCIE=y
CONFIG_PHY_HI6220_USB=y
CONFIG_PHY_HISTB_COMBPHY=y
CONFIG_PHY_HISI_INNO_USB2=y
CONFIG_PHY_MVEBU_CP110_COMPHY=y
CONFIG_PHY_MTK_TPHY=y
CONFIG_PHY_QCOM_EDP=m
CONFIG_PHY_QCOM_PCIE2=m
CONFIG_PHY_QCOM_QMP=m
CONFIG_PHY_QCOM_QUSB2=m
CONFIG_PHY_QCOM_SNPS_EUSB2=m
CONFIG_PHY_QCOM_EUSB2_REPEATER=m
CONFIG_PHY_QCOM_USB_HS=m
CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
CONFIG_PHY_QCOM_USB_HS_28NM=m
CONFIG_PHY_QCOM_USB_SS=m
CONFIG_PHY_QCOM_SGMII_ETH=m
CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y
CONFIG_PHY_RCAR_GEN3_PCIE=y
CONFIG_PHY_RCAR_GEN3_USB2=y
CONFIG_PHY_RCAR_GEN3_USB3=m
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
CONFIG_PHY_ROCKCHIP_PCIE=m
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_SAMSUNG_UFS=y
CONFIG_PHY_UNIPHIER_USB2=y
CONFIG_PHY_UNIPHIER_USB3=y
CONFIG_PHY_TEGRA_XUSB=y
CONFIG_PHY_AM654_SERDES=y
CONFIG_PHY_J721E_WIZ=y
CONFIG_OMAP_USB2=m
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_SMMU_V3_PMU=m
CONFIG_ARM_DSU_PMU=m
CONFIG_FSL_IMX8_DDR_PMU=m
CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
CONFIG_ARM_SPE_PMU=m
CONFIG_ARM_DMC620_PMU=m
CONFIG_HISI_PMU=y
CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m
CONFIG_NVMEM_LAYOUT_SL28_VPD=m
CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_NVMEM_IMX_OCOTP_ELE=m
CONFIG_NVMEM_IMX_OCOTP_SCU=y
CONFIG_NVMEM_LAYERSCAPE_SFP=m
CONFIG_NVMEM_MESON_EFUSE=m
CONFIG_NVMEM_MTK_EFUSE=y
CONFIG_NVMEM_QCOM_QFPROM=y
CONFIG_NVMEM_RMEM=m
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_SNVS_LPGPR=y
CONFIG_NVMEM_SPMI_SDAM=m
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_UNIPHIER_EFUSE=y
CONFIG_FPGA=y
CONFIG_FPGA_MGR_ALTERA_CVP=m
CONFIG_FPGA_MGR_STRATIX10_SOC=m
CONFIG_FPGA_BRIDGE=m
CONFIG_ALTERA_FREEZE_BRIDGE=m
CONFIG_FPGA_REGION=m
CONFIG_OF_FPGA_REGION=m
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_MUX_GPIO=m
CONFIG_SLIM_QCOM_CTRL=m
CONFIG_SLIM_QCOM_NGD_CTRL=m
CONFIG_INTERCONNECT_IMX=y
CONFIG_INTERCONNECT_IMX8MM=m
CONFIG_INTERCONNECT_IMX8MN=m
CONFIG_INTERCONNECT_IMX8MQ=m
CONFIG_INTERCONNECT_IMX8MP=y
CONFIG_INTERCONNECT_QCOM=y
CONFIG_INTERCONNECT_QCOM_MSM8916=m
CONFIG_INTERCONNECT_QCOM_MSM8996=m
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
CONFIG_INTERCONNECT_QCOM_QCM2290=m
CONFIG_INTERCONNECT_QCOM_QCS404=m
CONFIG_INTERCONNECT_QCOM_SA8775P=y
CONFIG_INTERCONNECT_QCOM_SC7180=y
CONFIG_INTERCONNECT_QCOM_SC7280=y
CONFIG_INTERCONNECT_QCOM_SC8180X=y
CONFIG_INTERCONNECT_QCOM_SC8280XP=y
CONFIG_INTERCONNECT_QCOM_SDM845=y
CONFIG_INTERCONNECT_QCOM_SM8150=m
CONFIG_INTERCONNECT_QCOM_SM8250=m
CONFIG_INTERCONNECT_QCOM_SM8350=m
CONFIG_INTERCONNECT_QCOM_SM8450=y
CONFIG_INTERCONNECT_QCOM_SM8550=y
CONFIG_COUNTER=m
CONFIG_RZ_MTU3_CNT=m
CONFIG_TI_ECAP_CAPTURE=m
CONFIG_TI_EQEP=m
CONFIG_HTE=y
CONFIG_HTE_TEGRA194=y
CONFIG_HTE_TEGRA194_TEST=m
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_QUOTA=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
CONFIG_OVERLAY_FS=m
CONFIG_VFAT_FS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_EFIVAR_FS=y
CONFIG_UBIFS_FS=y
CONFIG_SQUASHFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64_CE=m
CONFIG_CRYPTO_SHA3_ARM64=m
CONFIG_CRYPTO_SM3_ARM64_CE=m
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=m
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
CONFIG_CRYPTO_DEV_SUN8I_CE=m
CONFIG_CRYPTO_DEV_FSL_CAAM=m
CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCOM_RNG=m
CONFIG_CRYPTO_DEV_CCREE=m
CONFIG_CRYPTO_DEV_HISI_SEC2=m
CONFIG_CRYPTO_DEV_HISI_ZIP=m
CONFIG_CRYPTO_DEV_HISI_HPRE=m
CONFIG_CRYPTO_DEV_HISI_TRNG=m
CONFIG_CRYPTO_DEV_SA2UL=m
CONFIG_CRYPTO_DEV_TI_MCRC64=m
CONFIG_DMA_RESTRICTED_POOL=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_FTRACE is not set
CONFIG_CORESIGHT=m
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m
CONFIG_CORESIGHT_CATU=m
CONFIG_CORESIGHT_SINK_TPIU=m
CONFIG_CORESIGHT_SINK_ETBV10=m
CONFIG_CORESIGHT_STM=m
CONFIG_CORESIGHT_CPU_DEBUG=m
CONFIG_CORESIGHT_CTI=m
CONFIG_MEMTEST=y
CONFIG_PPS=y
CONFIG_PPS_CLIENT_GPIO=y
CONFIG_PPS_CLIENT_LDISC=y
CONFIG_PPS_DEBUG=y

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Product Link: https://www.ti.com/tool/J721EXCPXEVM
 */

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>

/ {
	compatible = "ti,j721e-evm", "ti,j721e";
	model = "Texas Instruments J721e EVM";

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart0;
		serial7 = &main_uart5;
		spi3 = &main_spi3;
		spi5 = &main_spi5;
		ethernet0 = &cpsw_port1;
		mmc0 = &main_sdhci0;
		mmc1 = &main_sdhci1;
	};

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LMS140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		//gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv_alt: gpio-regulator-tps659411 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
		regulator-name = "vdd_sd_dv";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_3v3>;
		gpios = <&main_gpio0 111 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	dp_pwr_3v3: regulator-dp-pwr {
		compatible = "regulator-fixed";
		regulator-name = "dp-pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		//gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
		enable-active-high;
	};

	dp0: connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <&dp_pwr_3v3>;

		port {
			dp_connector_in: endpoint {
				remote-endpoint = <&dp0_out>;
			};
		};
	};

	pps {
		status = "okay";
		compatible = "pps-gpio";
		gpios = <&main_gpio1 13 GPIO_ACTIVE_HIGH>;
	};
};

&main_pmx0 {
	main_uart0_pins_default: main-uart0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
			J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
		>;
	};

	main_mmc1_pins_default: main-mmc1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
		>;
	};

	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
		>;
	};

	dp0_pins_default: dp0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
		>;
	};

	mcasp10_pins_default: mcasp10-default-pins {
		pinctrl-single,pins = <
			//J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ /*pin FOR I2C2  del 2025/02/25  */
			//J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */  /*pin FOR I2C2  del 2025/02/25  */
			//J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */     /*pin FOR UART3  del 2025/02/25  */
			//J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */     /*pin FOR UART3  del 2025/02/25  */
			J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
			J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
			// J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */	/* pin FOR SPI5  del 2025/02/27   */
			// J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
			// J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */	/* pin FOR SPI5  del 2025/02/27   */
		>;
	};

	audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
		>;
	};

	// main域gpio0的设备树具体内容需要各位老师确认，有需要则打开注释，最后仍保留注释部分将从设备树中删除
	// add
	main_gpio0_pins_default: main-gpio0-default-pins {
		pinctrl-single,pins = <
			// J721E_IOPAD(0x4, PIN_OUTPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
			// J721E_IOPAD(0x8, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
			// J721E_IOPAD(0xc, PIN_OUTPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
			J721E_IOPAD(0x10, PIN_OUTPUT_PULLDOWN, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
			// J721E_IOPAD(0x14, PIN_OUTPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
			// J721E_IOPAD(0x1c, PIN_OUTPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
			J721E_IOPAD(0x28, PIN_INPUT, 7) /* (AG20) PRG1_PRU0_GPO9.GPIO0_10 */
			J721E_IOPAD(0x2c, PIN_OUTPUT_PULLUP, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
			// J721E_IOPAD(0x30, PIN_OUTPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
			// J721E_IOPAD(0x34, PIN_OUTPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
			// J721E_IOPAD(0x38, PIN_INPUT, 7) /* (AG24) PRG1_PRU0_GPO13.GPIO0_14 */
			// J721E_IOPAD(0x3c, PIN_OUTPUT, 7) /* (AD24) PRG1_PRU0_GPO14.GPIO0_15 */
			// J721E_IOPAD(0x40, PIN_INPUT, 7) /* (AC24) PRG1_PRU0_GPO15.GPIO0_16 */
			// J721E_IOPAD(0x44, PIN_INPUT, 7) /* (AE24) PRG1_PRU0_GPO16.GPIO0_17 */
			// J721E_IOPAD(0x4c, PIN_INPUT, 7) /* (AJ21) PRG1_PRU0_GPO17.GPIO0_18 */
			// J721E_IOPAD(0x50, PIN_INPUT, 7) /* (AE21) PRG1_PRU0_GPO18.GPIO0_19 */
			// J721E_IOPAD(0x54, PIN_INPUT, 7) /* (AH21) PRG1_PRU0_GPO19.GPIO0_20 */
			// J721E_IOPAD(0x58, PIN_INPUT, 7) /* (AE22) PRG1_PRU1_GPO0.GPIO0_21 */
			// J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
			// J721E_IOPAD(0x60, PIN_INPUT, 7) /* (AF23) PRG1_PRU1_GPO2.GPIO0_23 */
			// J721E_IOPAD(0x64, PIN_INPUT, 7) /* (AD23) PRG1_PRU1_GPO3.GPIO0_24 */
			// J721E_IOPAD(0x68, PIN_INPUT, 7) /* (AH24) PRG1_PRU1_GPO4.GPIO0_25 */
			// J721E_IOPAD(0x6c, PIN_INPUT, 7) /* (AG21) PRG1_PRU1_GPO5.GPIO0_26 */
			// J721E_IOPAD(0x70, PIN_INPUT, 7) /* (AE23) PRG1_PRU1_GPO6.GPIO0_27 */
			// J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */
			// J721E_IOPAD(0x78, PIN_INPUT, 7) /* (Y23) PRG1_PRU1_GPO8.GPIO0_29 */
			// J721E_IOPAD(0x7c, PIN_OUTPUT, 7) /* (AF21) PRG1_PRU1_GPO9.GPIO0_30 */
			// J721E_IOPAD(0x80, PIN_OUTPUT, 7) /* (AB23) PRG1_PRU1_GPO10.GPIO0_31 */
			J721E_IOPAD(0x90, PIN_OUTPUT_PULLDOWN, 7) /* (AH26) PRG1_PRU1_GPO14.GPIO0_35 */
			J721E_IOPAD(0x94, PIN_INPUT, 7) /* (AJ27) PRG1_PRU1_GPO15.GPIO0_36 */
			// J721E_IOPAD(0xa8, PIN_OUTPUT, 7) /* (AD19) PRG1_MDIO0_MDIO.GPIO0_41 */
			// J721E_IOPAD(0xac, PIN_OUTPUT, 7) /* (AD18) PRG1_MDIO0_MDC.GPIO0_42 */
			// J721E_IOPAD(0xb0, PIN_OUTPUT, 7) /* (AF28) PRG0_PRU0_GPO0.GPIO0_43 */
			// J721E_IOPAD(0xb4, PIN_INPUT, 7) /* (AE28) PRG0_PRU0_GPO1.GPIO0_44 */
			// J721E_IOPAD(0xb8, PIN_OUTPUT, 7) /* (AE27) PRG0_PRU0_GPO2.GPIO0_45 */
			// J721E_IOPAD(0xbc, PIN_OUTPUT, 7) /* (AD26) PRG0_PRU0_GPO3.GPIO0_46 */
			// J721E_IOPAD(0xc0, PIN_INPUT, 7) /* (AD25) PRG0_PRU0_GPO4.GPIO0_47 */
			// J721E_IOPAD(0xc8, PIN_OUTPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
			// J721E_IOPAD(0xcc, PIN_OUTPUT, 7) /* (AC28) PRG0_PRU0_GPO7.GPIO0_50 */
			// J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (AC27) PRG0_PRU0_GPO8.GPIO0_51 */
			// J721E_IOPAD(0xdc, PIN_OUTPUT, 7) /* (AJ28) PRG0_PRU0_GPO11.GPIO0_54 */
			// J721E_IOPAD(0xe0, PIN_OUTPUT, 7) /* (AH27) PRG0_PRU0_GPO12.GPIO0_55 */
			// J721E_IOPAD(0xe4, PIN_INPUT, 7) /* (AH29) PRG0_PRU0_GPO13.GPIO0_56 */
			// J721E_IOPAD(0xe8, PIN_INPUT, 7) /* (AG28) PRG0_PRU0_GPO14.GPIO0_57 */
			// J721E_IOPAD(0xec, PIN_INPUT, 7) /* (AG27) PRG0_PRU0_GPO15.GPIO0_58 */
			// J721E_IOPAD(0xf0, PIN_OUTPUT, 7) /* (AH28) PRG0_PRU0_GPO16.GPIO0_59 */
			// J721E_IOPAD(0xf8, PIN_OUTPUT, 7) /* (AB29) PRG0_PRU0_GPO18.GPIO0_61 */
			// J721E_IOPAD(0xfc, PIN_INPUT, 7) /* (AB28) PRG0_PRU0_GPO19.GPIO0_62 */
			// J721E_IOPAD(0x100, PIN_INPUT, 7) /* (AE29) PRG0_PRU1_GPO0.GPIO0_63 */
			// J721E_IOPAD(0x104, PIN_INPUT, 7) /* (AD28) PRG0_PRU1_GPO1.GPIO0_64 */
			J721E_IOPAD(0x130, PIN_INPUT, 7) /* (AF27) PRG0_PRU1_GPO12.GPIO0_75 */
			J721E_IOPAD(0x134, PIN_OUTPUT_PULLUP, 7) /* (AF26) PRG0_PRU1_GPO13.GPIO0_76 */
			J721E_IOPAD(0x138, PIN_OUTPUT_PULLUP, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
			// J721E_IOPAD(0x13c, PIN_OUTPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
			// J721E_IOPAD(0x140, PIN_INPUT, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */
			J721E_IOPAD(0x150, PIN_OUTPUT_PULLDOWN, 7) /* (Y26) PRG0_MDIO0_MDIO.GPIO0_83 */
			J721E_IOPAD(0x154, PIN_OUTPUT_PULLDOWN, 7) /* (AA27) PRG0_MDIO0_MDC.GPIO0_84 */
			// J721E_IOPAD(0x168, PIN_OUTPUT, 7) /* (V27) RGMII5_TD1.GPIO0_89 */
			J721E_IOPAD(0x16c, PIN_INPUT, 7) /* (U28) RGMII5_TD0.GPIO0_90  OPEN for SPI3_CS2 IRQ */
			J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 7) /* (U29) RGMII5_TXC.GPIO0_91 */
			J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 7) /* (U25) RGMII5_RXC.GPIO0_92 */
			// J721E_IOPAD(0x178, PIN_OUTPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
			// J721E_IOPAD(0x17c, PIN_OUTPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
			J721E_IOPAD(0x180, PIN_OUTPUT_PULLDOWN, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
			J721E_IOPAD(0x184, PIN_OUTPUT_PULLDOWN, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
			// J721E_IOPAD(0x188, PIN_OUTPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
			J721E_IOPAD(0x18c, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
			J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
			// J721E_IOPAD(0x194, PIN_OUTPUT, 7) /* (W28) RGMII6_TD2.GPIO0_100 */
			// J721E_IOPAD(0x198, PIN_OUTPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
			// J721E_IOPAD(0x19c, PIN_OUTPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
			// J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
			J721E_IOPAD(0x1a4, PIN_INPUT, 7) /* (W26) RGMII6_RXC.GPIO0_104 */
			// J721E_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
			// J721E_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (Y4) SPI0_CS1.GPIO0_112 */
			// J721E_IOPAD(0x1c8, PIN_OUTPUT, 7) /* (AA1) SPI0_CLK.GPIO0_113 */
			// J721E_IOPAD(0x1cc, PIN_OUTPUT, 7) /* (AB5) SPI0_D0.GPIO0_114 */
			// J721E_IOPAD(0x1d0, PIN_OUTPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
			// J721E_IOPAD(0x1dc, PIN_INPUT, 7) /* (Y1) SPI1_CLK.GPIO0_118 */
			// J721E_IOPAD(0x1e0, PIN_INPUT, 7) /* (Y5) SPI1_D0.GPIO0_119 */
			J721E_IOPAD(0x1e4, PIN_INPUT, 7) /* (Y2) SPI1_D1.GPIO0_120 */
		>;
	};

	// main域gpio1的设备树具体内容需要各位老师确认，有需要则打开注释，最后仍保留注释部分将从设备树中删除
	// add
	main_gpio1_pins_default: main-gpio1-default-pins {
		pinctrl-single,pins = <
			// J721E_IOPAD(0x218, PIN_OUTPUT, 7) /* (W2) I3C0_SCL.GPIO1_5 */
			// J721E_IOPAD(0x21c, PIN_INPUT, 7) /* (W1) I3C0_SDA.GPIO1_6 */
			// J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
			// J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
			J721E_IOPAD(0x260, PIN_OUTPUT_PULLDOWN, 7) /* (T28) MMC2_DAT3.GPIO1_23 */
			// J721E_IOPAD(0x264, PIN_INPUT, 7) /* (T29) MMC2_DAT2.GPIO1_24 */
			//J721E_IOPAD(0x268, PIN_OUTPUT_PULLUP, 7) /* (T27) MMC2_DAT1.GPIO1_25 */ /*pin FOR TDA4_LG69T_RST  del 2025/02/25  */
			// J721E_IOPAD(0x26c, PIN_OUTPUT, 7) /* (T24) MMC2_DAT0.GPIO1_26 */
			// J721E_IOPAD(0x270, PIN_INPUT, 7) /* (T26) MMC2_CLK.GPIO1_27 */
			// J721E_IOPAD(0x274, PIN_INPUT, 7) /* (T25) MMC2_CMD.GPIO1_28 */
			// J721E_IOPAD(0x290, PIN_OUTPUT, 7) /* (U6) USB0_DRVVBUS.GPIO1_29 */
			// J721E_IOPAD(0x294, PIN_INPUT, 7) /* (AD1) MLB0_MLBSP.GPIO1_30 */
			// J721E_IOPAD(0x298, PIN_INPUT, 7) /* (AC1) MLB0_MLBSN.GPIO1_31 */
			// J721E_IOPAD(0x29c, PIN_INPUT, 7) /* (AC3) MLB0_MLBDP.GPIO1_32 */
			// J721E_IOPAD(0x2a0, PIN_INPUT, 7) /* (AD3) MLB0_MLBDN.GPIO1_33 */
			// J721E_IOPAD(0x2a4, PIN_INPUT, 7) /* (AD2) MLB0_MLBCP.GPIO1_34 */
			// J721E_IOPAD(0x2a8, PIN_INPUT, 7) /* (AE2) MLB0_MLBCN.GPIO1_35 */
		>;
	};

	// add
	main_mcasp1_pins_default: main-mcasp1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x108, PIN_INPUT, 12) /* (AD27) PRG0_PRU1_GPO2.MCASP1_ACLKR */
			J721E_IOPAD(0x114, PIN_INPUT, 12) /* (AB27) PRG0_PRU1_GPO5.MCASP1_ACLKX */
			J721E_IOPAD(0x120, PIN_INPUT, 12) /* (AA28) PRG0_PRU1_GPO8.MCASP1_AFSX */
			J721E_IOPAD(0x10c, PIN_INPUT, 13) /* (AC25) PRG0_PRU1_GPO3.MCASP1_AXR11 */
		>;
	};

	// add
	main_mmcsd1_pins_default: main-mmcsd1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
		>;
	};

	// add
	main_pcie3_pins_default: main-pcie3-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x25c, PIN_INPUT, 6) /* (R28) MMC1_SDWP.PCIE3_CLKREQn */
		>;
	};

	/* AG190W SPI <---> TDA4 SPI3 */
	main_spi3_pins_default: main-spi3-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x144, PIN_INPUT, 4) /* (Y25) PRG0_PRU1_GPO17.SPI3_CLK */
			J721E_IOPAD(0x11c, PIN_INPUT, 4) /* (AA24) PRG0_PRU1_GPO7.SPI3_CS0 */
			J721E_IOPAD(0xd4, PIN_INPUT, 4) /* (AB26) PRG0_PRU0_GPO9.SPI3_CS1 */
			J721E_IOPAD(0xd8, PIN_INPUT, 4) /* (AB25) PRG0_PRU0_GPO10.SPI3_CS2 */
			J721E_IOPAD(0x124, PIN_INPUT, 4) /* (Y24) PRG0_PRU1_GPO9.SPI3_CS3 */
			J721E_IOPAD(0x148, PIN_INPUT, 4) /* (AA26) PRG0_PRU1_GPO18.SPI3_D0 */
			J721E_IOPAD(0x14c, PIN_INPUT, 4) /* (AA29) PRG0_PRU1_GPO19.SPI3_D1 */
		>;
	};

	/* Add for A2 Sample AG568N <---> TDA4 SPI5 */
	main_spi5_pins_default: main_spi5-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1a0, PIN_INPUT, 3) /* (W29) RGMII6_TXC.SPI5_CLK */
			J721E_IOPAD(0x1b4, PIN_INPUT, 3) /* (W25) RGMII6_RD0.SPI5_CS1 */
			J721E_IOPAD(0x198, PIN_INPUT, 3) /* (V25) RGMII6_TD1.SPI5_D0 */
			J721E_IOPAD(0x1b0, PIN_INPUT, 3) /* (W24) RGMII6_RD1.SPI5_D1 */
		>;
	};

	// add
	main_system0_pins_default: main-system0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x278, PIN_OUTPUT, 0) /* (T6) RESETSTATz */
			J721E_IOPAD(0x280, PIN_INPUT, 0) /* (U4) SOC_SAFETY_ERRORn */
		>;
	};

	// add
	main_timer0_pins_default: main-timer0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x238, PIN_INPUT, 0) /* (V6) TIMER_IO0 */
		>;
	};
	
	/* AG190W Uart3 <----> TDA4 Uart5 */
	main_uart5_pins_default: main-uart5-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d4, PIN_INPUT, 3) /* (Y3) SPI1_CS0.UART5_RXD */
			J721E_IOPAD(0x1d8, PIN_OUTPUT, 3) /* (W4) SPI1_CS1.UART5_TXD */
		>;
	};
};

&wkup_pmx0 {
	/delete-node/ pmic-irq-default-pins;

	mcu_fss0_ospi0_pins_default: mcu_fss0_ospi0-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
			J721E_WKUP_IOPAD(0x3c, PIN_INPUT_PULLUP, 6) /* (B23) MCU_OSPI1_DQS.MCU_OSPI0_ECC_FAIL */
			J721E_WKUP_IOPAD(0x38, PIN_OUTPUT_PULLUP, 6) /* (A23) MCU_OSPI1_LBCLKO.MCU_OSPI0_RESET_OUT0 */
		>;
	};

	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
		>;
	};

	// modify
	// mcu_mdio_pins_default: mcu-mdio1-default-pins {
	// 	pinctrl-single,pins = <
	// 		J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
	// 		J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
	// 	>;
	// };
	mcu_mdio_pins_default: mcu-mdio1-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
			J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
		>;
	};

	// wkup域gpio0的设备树具体内容需要各位老师确认，有需要则打开注释，最后仍保留注释部分将从设备树中删除
	wkup_gpio_pins_default: wkup-gpio-default-pins {
		pinctrl-single,pins = <
	//		J721E_WKUP_IOPAD(0xbc, PIN_OUTPUT_PULLDOWN, 7) /* (F27) WKUP_GPIO0_3 */ /*pin Board_ID_EEPROM_WP  del 2025/02/25  */
	// 		J721E_WKUP_IOPAD(0xc8, PIN_INPUT, 7) /* (F29) WKUP_GPIO0_6 */
	// 		J721E_WKUP_IOPAD(0xcc, PIN_OUTPUT, 7) /* (G28) WKUP_GPIO0_7 */
	// 		J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_8 */
	// 		J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */
	// 		J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (H26) WKUP_GPIO0_10 */
	// 		J721E_WKUP_IOPAD(0xdc, PIN_OUTPUT, 7) /* (H27) WKUP_GPIO0_11 */
	// 		J721E_WKUP_IOPAD(0x4, PIN_INPUT_PULLUP, 7) /* (C21) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */
	// 		J721E_WKUP_IOPAD(0x34, PIN_INPUT, 7) /* (F22) MCU_OSPI1_CLK.WKUP_GPIO0_29 */
	// 		J721E_WKUP_IOPAD(0x40, PIN_OUTPUT, 7) /* (D22) MCU_OSPI1_D0.WKUP_GPIO0_32 */
	// 		J721E_WKUP_IOPAD(0x44, PIN_OUTPUT, 7) /* (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
	// 		J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
	// 		J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
	// 		J721E_WKUP_IOPAD(0x50, PIN_OUTPUT_PULLUP, 7) /* (C22) MCU_OSPI1_CSn0.WKUP_GPIO0_36 */
	// 		J721E_WKUP_IOPAD(0x9c, PIN_INPUT, 7) /* (E25) MCU_SPI0_CS0.WKUP_GPIO0_55 */
	// 		J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 7) /* (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
	// 		J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 7) /* (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
	//		J721E_WKUP_IOPAD(0x108, PIN_OUTPUT_PULLDOWN, 7) /* (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */  /*pin BOOT_EEPROM_WP  del 2025/02/25  */
		>;
	};


	// add
	mcu_rgmii1_pins_default: mcu-rgmii1-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
			J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
		>;
	};

};

&main_spi3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi3_pins_default>;
	spidev@0 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <0>;
		spi-cpol = <1>; // CPOL = 1
		spi-cpha = <1>; // CPHA = 1
	};
	spidev@1 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <1>;
		spi-cpol = <0>; // CPOL = 0
		spi-cpha = <1>; // CPHA = 1
	};
	spidev@2 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <2>;
		spi-cpol = <0>; // CPOL = 0
		spi-cpha = <0>; // CPHA = 0
		// interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
	};
	spidev@3 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <3>;
		spi-cpol = <0>; // CPOL = 0
		spi-cpha = <1>; // CPHA = 1
	};
};

&main_spi5 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi5_pins_default>;
	spidev@0 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <0>;
		spi-cpol = <1>; // CPOL = 1
		spi-cpha = <1>; // CPHA = 1
	};
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	status = "reserved";
};

&mcu_uart0 {
	status = "reserved";

};

&main_uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	/* Shared with ATF on this platform */
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart1 {
	status = "disabled";
};

&main_uart2 {
	status = "disabled";
};

&main_uart4 {
	status = "disabled";
};

&wkup_gpio0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_gpio_pins_default>;
};

&main_gpio0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_gpio0_pins_default>;
};

&main_gpio1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_gpio1_pins_default>;
};

&main_sdhci0 {
	/* eMMC */
	status = "okay";
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	/* SD/MMC */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	no-1-8-v;
	sdhci-caps-mask = <0x8000000F 0x0>;

};

&ufs_wrapper {
	status = "okay";
	ufs@4e84000 {
	/* ufs */
	status = "okay";
	freq-table-hz = <26000000 26000000>,      // 高速频率  
                	<19200000 19200000>,      // 低速频率1  
                	<19200000 19200000>;      // 低速频率2	
	};
};

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&cpsw0 {
	status = "okay";
};

&cpsw9g_mdio {
	status = "okay";
};

&cpsw0_port3 {
	//phy-handle = <&debug_phy>;
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 3>, <&serdes1_sgmii_link>;
	//phy-names = "portmode", "serdes-phy";
	phy-names = "mac", "serdes";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&serdes_wiz3 {
	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
};

&serdes3 {
	serdes3_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
	};
};


&ospi0 {
	status = "okay";
	flash@0 {
		cdns,read-delay = <4>;
	};
};

&ospi1 {
	status = "disabled";
};

&tscadc0 {
	status = "okay";
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&tscadc1 {
	status = "okay";
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&k3_clks {
	/* Confiure AUDIO_EXT_REFCLK2 pin as output */
	pinctrl-names = "default";
	pinctrl-0 = <&audi_ext_refclk2_pins_default>;
};

&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;

	cpts@3d000 {
		/* Map HW4_TS_PUSH to GENF1 */
		ti,pps = <3 1>;
	};
};

&davinci_mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
	};
	phy2: ethernet-phy@2 {
		reg = <2>;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&phy0>, <&phy2>;
};

&dss {
	/*
	 * These clock assignments are chosen to enable the following outputs:
	 *
	 * VP0 - DisplayPort SST
	 * VP1 - DPI0
	 * VP2 - DSI
	 * VP3 - DPI1
	 */

	assigned-clocks = <&k3_clks 152 1>,
			  <&k3_clks 152 4>,
			  <&k3_clks 152 9>,
			  <&k3_clks 152 13>;
	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
};

&dss_ports {
	port {
		dpi0_out: endpoint {
			remote-endpoint = <&dp0_in>;
		};
	};
};

&dp0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dp0_in: endpoint {
			remote-endpoint = <&dpi0_out>;
		};
	};

	port@4 {
		reg = <4>;
		dp0_out: endpoint {
			remote-endpoint = <&dp_connector_in>;
		};
	};
};

&mcasp10 {
	status = "okay";
	#sound-dai-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp10_pins_default>;

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	auxclk-fs-ratio = <256>;

	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 1 1 1
		2 2 2 0
	>;
	tx-num-evt = <0>;
	rx-num-evt = <0>;
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz0_refclk_dig {
	assigned-clocks = <&wiz0_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_pll1_refclk {
	assigned-clocks = <&wiz1_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_refclk_dig {
	assigned-clocks = <&wiz1_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_pll1_refclk {
	assigned-clocks = <&wiz2_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_refclk_dig {
	assigned-clocks = <&wiz2_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&serdes0 {
	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz0_pll1_refclk>;

	// serdes0_pcie_link: phy@0 {
	// 	reg = <0>;
	// 	cdns,num-lanes = <1>;
	// 	#phy-cells = <0>;
	// 	cdns,phy-type = <PHY_TYPE_PCIE>;
	// 	resets = <&serdes_wiz0 1>;
	// };

	serdes0_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
	};
};

&serdes1 {

	// serdes1_pcie_link: phy@0 {
	// 	reg = <0>;
	// 	cdns,num-lanes = <2>;
	// 	#phy-cells = <0>;
	// 	cdns,phy-type = <PHY_TYPE_PCIE>;
	// 	resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
	// };

	serdes1_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz1 1>;
		assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
		assigned-clock-parents = <&wiz1_pll1_refclk>;
	};
};

&serdes2 {
	assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz2_pll1_refclk>;

	serdes2_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};
};

&serdes4 {
	torrent_phy_dp: phy@0 {
		reg = <0>;
		resets = <&serdes_wiz4 1>;
		cdns,phy-type = <PHY_TYPE_DP>;
		cdns,num-lanes = <4>;
		cdns,max-bit-rate = <2700>;
		#phy-cells = <0>;
	};
};

&mhdp {
	phys = <&torrent_phy_dp>;
	phy-names = "dpphy";
	pinctrl-names = "default";
	pinctrl-0 = <&dp0_pins_default>;
};

// &pcie0_rc {
// 	status = "okay";
// 	//reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
// 	phys = <&serdes0_pcie_link>;
// 	phy-names = "pcie-phy";
// 	num-lanes = <1>;
// };

// &pcie1_rc {
// 	status = "okay";
// 	//reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
// 	phys = <&serdes1_pcie_link>;
// 	phy-names = "pcie-phy";
// 	num-lanes = <2>;
// };

&pcie2_rc {
	status = "okay";
	//reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
	phys = <&serdes2_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
};

#define K3_TS_OFFSET(pa, val)	(0x4+(pa)*4) (0x10000 | val)

&timesync_router {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_cpts>;

	/* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */
	mcu_cpsw_cpts: mcu-cpsw-cpts {
		pinctrl-single,pins = <
			/* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */
			K3_TS_OFFSET(25, 17)
			>;
	};
};

&wkup_i2c0 {
	/delete-node/ eeprom@50;
	/delete-node/ pmic@48;
	/delete-node/ pmic@4c;
	/*status = "reserved";*/
};

&cbass_main {
	phy@4580000 {
                status = "disable";
                };

	phy@4590000 {
                status = "disable";
                };

	dp-bridge@a000000  {
                status = "disable";
                };
};

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721E SoC Family Main Domain peripherals
 *
 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
 */
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-ti.h>
#include <dt-bindings/mux/mux.h>

#include "k3-serdes.h"

/ {
	cmn_refclk: clock-cmnrefclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	cmn_refclk1: clock-cmnrefclk1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};
};

&cbass_main {
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x800000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x800000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};
	};

	scm_conf: scm-conf@100000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x00100000 0x1c000>;

		serdes_ln_ctrl: mux-controller@4080 {
			compatible = "reg-mux";
			reg = <0x4080 0x50>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
					<0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
					<0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
					<0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
					<0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
					<0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
			idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
				      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
				      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
				      <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
				      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
				      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
		};

		cpsw0_phy_gmii_sel: phy@4044 {
			compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
			ti,qsgmii-main-ports = <2>, <2>;
			reg = <0x4044 0x20>;
			#phy-cells = <1>;
		};

		usb_serdes_mux: mux-controller@4000 {
			compatible = "reg-mux";
			reg = <0x4000 0x20>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
					<0x10 0x8000000>; /* USB1 to SERDES1/2 mux */
		};

		ehrpwm_tbclk: clock-controller@4140 {
			compatible = "ti,am654-ehrpwm-tbclk";
			reg = <0x4140 0x18>;
			#clock-cells = <1>;
		};
	};

	main_ehrpwm0: pwm@3000000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3000000 0x00 0x100>;
		power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm1: pwm@3010000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3010000 0x00 0x100>;
		power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm2: pwm@3020000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3020000 0x00 0x100>;
		power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm3: pwm@3030000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3030000 0x00 0x100>;
		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm4: pwm@3040000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3040000 0x00 0x100>;
		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm5: pwm@3050000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3050000 0x00 0x100>;
		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
		      <0x00 0x01900000 0x00 0x100000>,	/* GICR */
		      <0x00 0x6f000000 0x00 0x2000>,	/* GICC */
		      <0x00 0x6f010000 0x00 0x1000>,	/* GICH */
		      <0x00 0x6f020000 0x00 0x2000>;	/* GICV */

		/* vcpumntirq: virtual CPU interface maintenance interrupt */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	main_gpio_intr: interrupt-controller@a00000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x00a00000 0x00 0x800>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <131>;
		ti,interrupt-ranges = <8 392 56>;
	};

	main_navss: bus@30000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
		dma-coherent;
		dma-ranges;

		ti,sci-dev-id = <199>;

		main_navss_intr: interrupt-controller@310e0000 {
			compatible = "ti,sci-intr";
			reg = <0x0 0x310e0000 0x0 0x4000>;
			ti,intr-trigger-type = <4>;
			interrupt-controller;
			interrupt-parent = <&gic500>;
			#interrupt-cells = <1>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <213>;
			ti,interrupt-ranges = <0 64 64>,
					      <64 448 64>,
					      <128 672 64>;
		};

		main_udmass_inta: interrupt-controller@33d00000 {
			compatible = "ti,sci-inta";
			reg = <0x0 0x33d00000 0x0 0x100000>;
			interrupt-controller;
			interrupt-parent = <&main_navss_intr>;
			msi-controller;
			#interrupt-cells = <0>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <209>;
			ti,interrupt-ranges = <0 0 256>;
		};

		secure_proxy_main: mailbox@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x32c00000 0x00 0x100000>,
			      <0x00 0x32400000 0x00 0x100000>,
			      <0x00 0x32800000 0x00 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		smmu0: iommu@36600000 {
			compatible = "arm,smmu-v3";
			reg = <0x0 0x36600000 0x0 0x100000>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			#iommu-cells = <1>;
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x00 0x30e00000 0x00 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f81000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f82000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f83000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f84000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f85000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f86000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f87000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f88000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f89000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		main_ringacc: ringacc@3c000000 {
			compatible = "ti,am654-navss-ringacc";
			reg = <0x0 0x3c000000 0x0 0x400000>,
			      <0x0 0x38000000 0x0 0x400000>,
			      <0x0 0x31120000 0x0 0x100>,
			      <0x0 0x33000000 0x0 0x40000>,
			      <0x0 0x31080000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
			ti,num-rings = <1024>;
			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <211>;
			msi-parent = <&main_udmass_inta>;
		};

		main_udmap: dma-controller@31150000 {
			compatible = "ti,j721e-navss-main-udmap";
			reg = <0x0 0x31150000 0x0 0x100>,
			      <0x0 0x34000000 0x0 0x100000>,
			      <0x0 0x35000000 0x0 0x100000>,
			      <0x0 0x30b00000 0x0 0x20000>,
			      <0x0 0x30c00000 0x0 0x10000>,
			      <0x0 0x30d00000 0x0 0x8000>;
			reg-names = "gcfg", "rchanrt", "tchanrt",
				    "tchan", "rchan", "rflow";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&dmsc>;
			ti,sci-dev-id = <212>;
			ti,ringacc = <&main_ringacc>;

			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>, /* TX_HCHAN */
						<0x10>; /* TX_UHCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>, /* RX_HCHAN */
						<0x0c>; /* RX_UHCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};

		cpts@310d0000 {
			compatible = "ti,j721e-cpts";
			reg = <0x0 0x310d0000 0x0 0x400>;
			reg-names = "cpts";
			clocks = <&k3_clks 201 1>;
			clock-names = "cpts";
			interrupts-extended = <&main_navss_intr 391>;
			interrupt-names = "cpts";
			ti,cpts-periodic-outputs = <6>;
			ti,cpts-ext-ts-inputs = <8>;
		};
	};

	cpsw0: ethernet@c000000 {
		compatible = "ti,j721e-cpswxg-nuss";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x0 0xc000000 0x0 0x200000>;
		reg-names = "cpsw_nuss";
		ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
		clocks = <&k3_clks 19 89>;
		clock-names = "fck";
		power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			cpsw0_port1: port@1 {
				reg = <1>;
				ti,mac-only;
				label = "port1";
				status = "disabled";
			};

			cpsw0_port2: port@2 {
				reg = <2>;
				ti,mac-only;
				label = "port2";
				status = "disabled";
			};

			cpsw0_port3: port@3 {
				reg = <3>;
				ti,mac-only;
				label = "port3";
			};

			cpsw0_port4: port@4 {
				reg = <4>;
				ti,mac-only;
				label = "port4";
				status = "disabled";
			};

			cpsw0_port5: port@5 {
				reg = <5>;
				ti,mac-only;
				label = "port5";
				status = "disabled";
			};

			cpsw0_port6: port@6 {
				reg = <6>;
				ti,mac-only;
				label = "port6";
				status = "disabled";
			};

			cpsw0_port7: port@7 {
				reg = <7>;
				ti,mac-only;
				label = "port7";
				status = "disabled";
			};

			cpsw0_port8: port@8 {
				reg = <8>;
				ti,mac-only;
				label = "port8";
				status = "disabled";
			};
		};

		cpsw9g_mdio: mdio@f00 {
			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
			reg = <0x0 0xf00 0x0 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k3_clks 19 89>;
			clock-names = "fck";
			bus_freq = <1000000>;
		};

		cpts@3d000 {
			compatible = "ti,j721e-cpts";
			reg = <0x0 0x3d000 0x0 0x400>;
			clocks = <&k3_clks 19 16>;
			clock-names = "cpts";
			interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cpts";
			ti,cpts-ext-ts-inputs = <4>;
			ti,cpts-periodic-outputs = <2>;
		};
	};

	main_crypto: crypto@4e00000 {
		compatible = "ti,j721e-sa2ul";
		reg = <0x0 0x4e00000 0x0 0x1200>;
		power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;

		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
				<&main_udmap 0x4001>;
		dma-names = "tx", "rx1", "rx2";

		rng: rng@4e10000 {
			compatible = "inside-secure,safexcel-eip76";
			reg = <0x0 0x4e10000 0x0 0x7d>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	main_pmx0: pinctrl@11c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x0 0x11c000 0x0 0x2b4>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
	main_timerio_input: pinctrl@104200 {
		compatible = "pinctrl-single";
		reg = <0x00 0x104200 0x00 0x50>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x00000007>;
	};

	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
	main_timerio_output: pinctrl@104280 {
		compatible = "pinctrl-single";
		reg = <0x00 0x104280 0x00 0x20>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x0000001f>;
	};

	ti_csi2rx0: ticsi2rx@4500000 {
		compatible = "ti,j721e-csi2rx-shim";
		reg = <0x0 0x4500000 0x0 0x1000>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>, <&main_udmap 0x4942>,
		       <&main_udmap 0x4943>, <&main_udmap 0x4944>, <&main_udmap 0x4945>,
		       <&main_udmap 0x4946>, <&main_udmap 0x4947>, <&main_udmap 0x4948>,
		       <&main_udmap 0x4949>, <&main_udmap 0x494a>, <&main_udmap 0x494b>,
		       <&main_udmap 0x494c>, <&main_udmap 0x494d>, <&main_udmap 0x494e>,
		       <&main_udmap 0x494f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";

		cdns_csi2rx0: csi-bridge@4504000 {
			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
			reg = <0x0 0x4504000 0x0 0x1000>;
			clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
				 <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				      "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy0>;
			phy-names = "dphy";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi0_port0: port@0 {
					reg = <0>;
					status = "disabled";
				};

				csi0_port1: port@1 {
					reg = <1>;
					status = "disabled";
				};

				csi0_port2: port@2 {
					reg = <2>;
					status = "disabled";
				};

				csi0_port3: port@3 {
					reg = <3>;
					status = "disabled";
				};

				csi0_port4: port@4 {
					reg = <4>;
					status = "disabled";
				};
			};
		};
	};

	ti_csi2rx1: ticsi2rx@4510000 {
		compatible = "ti,j721e-csi2rx-shim";
		reg = <0x0 0x4510000 0x0 0x1000>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		dmas = <&main_udmap 0x4960>, <&main_udmap 0x4961>, <&main_udmap 0x4962>,
		       <&main_udmap 0x4963>, <&main_udmap 0x4964>, <&main_udmap 0x4965>,
		       <&main_udmap 0x4966>, <&main_udmap 0x4967>, <&main_udmap 0x4968>,
		       <&main_udmap 0x4969>, <&main_udmap 0x496a>, <&main_udmap 0x496b>,
		       <&main_udmap 0x496c>, <&main_udmap 0x496d>, <&main_udmap 0x496e>,
		       <&main_udmap 0x496f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";

		cdns_csi2rx1: csi-bridge@4514000 {
			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
			reg = <0x0 0x4514000 0x0 0x1000>;
			clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
				 <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				      "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy1>;
			phy-names = "dphy";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi1_port0: port@0 {
					reg = <0>;
					status = "disabled";
				};

				csi1_port1: port@1 {
					reg = <1>;
					status = "disabled";
				};

				csi1_port2: port@2 {
					reg = <2>;
					status = "disabled";
				};

				csi1_port3: port@3 {
					reg = <3>;
					status = "disabled";
				};

				csi1_port4: port@4 {
					reg = <4>;
					status = "disabled";
				};
			};
		};
	};

	dphy0: phy@4580000 {
		compatible = "cdns,dphy-rx";
		reg = <0x0 0x4580000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	dphy1: phy@4590000 {
		compatible = "cdns,dphy-rx";
		reg = <0x0 0x4590000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	serdes_wiz0: wiz@5000000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5000000 0x0 0x5000000 0x10000>;

		wiz0_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 292 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 292 0>;
		};

		wiz0_refclk_dig: refclk-dig {
			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_refclk_dig>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz0_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz0_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes0: serdes@5000000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5000000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz0 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
				 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
				      "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz1: wiz@5010000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5010000 0x0 0x5010000 0x10000>;

		wiz1_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 293 13>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 293 0>;
		};

		wiz1_refclk_dig: refclk-dig {
			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_refclk_dig>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz1_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz1_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes1: serdes@5010000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5010000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz1 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
				 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
				      "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz2: wiz@5020000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5020000 0x0 0x5020000 0x10000>;

		wiz2_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 294 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 294 0>;
		};

		wiz2_refclk_dig: refclk-dig {
			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_refclk_dig>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz2_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz2_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes2: serdes@5020000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5020000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz2 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
				 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
				      "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz3: wiz@5030000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5030000 0x0 0x5030000 0x10000>;

		wiz3_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 295 9>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 295 0>;
		};

		wiz3_refclk_dig: refclk-dig {
			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_refclk_dig>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz3_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz3_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes3: serdes@5030000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5030000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz3 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
				 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
				      "pll0_refclk", "pll1_refclk";
		};
	};

	pcie0_rc: pcie@2900000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02900000 0x00 0x1000>,
		      <0x00 0x02907000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x00 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 239 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		status = "disabled";
	};

	pcie1_rc: pcie@2910000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 240 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x10000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		status = "disabled";
	};

	pcie2_rc: pcie@2920000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 241 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x20000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		status = "disabled";
	};

	pcie3_rc: pcie@2930000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02930000 0x00 0x1000>,
		      <0x00 0x02937000 0x00 0x400>,
		      <0x00 0x0e800000 0x00 0x00800000>,
		      <0x44 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 242 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x30000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		status = "disabled";
	};

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,am64-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 10>;
		assigned-clock-rates = <19200000>;
		num-lanes = <4>;
		#reset-cells = <1>;
		#clock-cells = <1>;
		ranges = <0x05050000 0x00 0x05050000 0x010000>,
			<0x0a030a00 0x00 0x0a030a00 0x40>;

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x05050000 0x010000>,
			      <0x0a030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
			clock-names = "refclk";
			assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
					  <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
					  <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
			assigned-clock-parents = <&k3_clks 297 9>,
						 <&k3_clks 297 9>,
						 <&k3_clks 297 9>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	main_timer0: timer@2400000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2400000 0x00 0x400>;
		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 49 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 49 1>;
		assigned-clock-parents = <&k3_clks 49 2>;
		power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer1: timer@2410000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2410000 0x00 0x400>;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 50 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
		assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
		power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer2: timer@2420000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2420000 0x00 0x400>;
		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 51 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 51 1>;
		assigned-clock-parents = <&k3_clks 51 2>;
		power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer3: timer@2430000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2430000 0x00 0x400>;
		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 52 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
		assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
		power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer4: timer@2440000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2440000 0x00 0x400>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 53 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 53 1>;
		assigned-clock-parents = <&k3_clks 53 2>;
		power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer5: timer@2450000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2450000 0x00 0x400>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 54 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
		assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
		power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer6: timer@2460000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2460000 0x00 0x400>;
		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 55 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 55 1>;
		assigned-clock-parents = <&k3_clks 55 2>;
		power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer7: timer@2470000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2470000 0x00 0x400>;
		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 57 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
		assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
		power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer8: timer@2480000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2480000 0x00 0x400>;
		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 58 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 58 1>;
		assigned-clock-parents = <&k3_clks 58 2>;
		power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer9: timer@2490000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2490000 0x00 0x400>;
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 59 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
		assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
		power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer10: timer@24a0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24a0000 0x00 0x400>;
		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 60 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 60 1>;
		assigned-clock-parents = <&k3_clks 60 2>;
		power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer11: timer@24b0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24b0000 0x00 0x400>;
		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 62 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
		assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
		power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer12: timer@24c0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24c0000 0x00 0x400>;
		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 63 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 63 1>;
		assigned-clock-parents = <&k3_clks 63 2>;
		power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer13: timer@24d0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24d0000 0x00 0x400>;
		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 64 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
		assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer14: timer@24e0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24e0000 0x00 0x400>;
		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 65 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 65 1>;
		assigned-clock-parents = <&k3_clks 65 2>;
		power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer15: timer@24f0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24f0000 0x00 0x400>;
		interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 66 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
		assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
		power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer16: timer@2500000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2500000 0x00 0x400>;
		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 67 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 67 1>;
		assigned-clock-parents = <&k3_clks 67 2>;
		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer17: timer@2510000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2510000 0x00 0x400>;
		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 68 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
		assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
		power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer18: timer@2520000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2520000 0x00 0x400>;
		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 69 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 69 1>;
		assigned-clock-parents = <&k3_clks 69 2>;
		power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer19: timer@2530000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2530000 0x00 0x400>;
		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 70 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
		assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
		power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_uart0: serial@2800000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x100>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 146 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart1: serial@2810000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x100>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 278 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart2: serial@2820000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x100>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 279 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart3: serial@2830000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02830000 0x00 0x100>;
		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 280 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart4: serial@2840000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02840000 0x00 0x100>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 281 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart5: serial@2850000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02850000 0x00 0x100>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 282 0>;
		clock-names = "fclk";
		status = "okay";
	};

	main_uart6: serial@2860000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02860000 0x00 0x100>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 283 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart7: serial@2870000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02870000 0x00 0x100>;
		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 284 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart8: serial@2880000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02880000 0x00 0x100>;
		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 285 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart9: serial@2890000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02890000 0x00 0x100>;
		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 286 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_gpio0: gpio@600000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00600000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <256>, <257>, <258>, <259>,
			     <260>, <261>, <262>, <263>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 105 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio1: gpio@601000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00601000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <288>, <289>, <290>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 106 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio2: gpio@610000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00610000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <264>, <265>, <266>, <267>,
			     <268>, <269>, <270>, <271>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 107 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio3: gpio@611000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00611000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <292>, <293>, <294>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 108 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio4: gpio@620000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00620000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <272>, <273>, <274>, <275>,
			     <276>, <277>, <278>, <279>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 109 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio5: gpio@621000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00621000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <296>, <297>, <298>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 110 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio6: gpio@630000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00630000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <280>, <281>, <282>, <283>,
			     <284>, <285>, <286>, <287>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 111 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio7: gpio@631000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00631000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <300>, <301>, <302>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 112 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_sdhci0: mmc@4f80000 {
		compatible = "ti,j721e-sdhci-8bit";
		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
		assigned-clocks = <&k3_clks 91 1>;
		assigned-clock-parents = <&k3_clks 91 2>;
		bus-width = <8>;
		mmc-hs200-1_8v;
		mmc-ddr-1_8v;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-mmc-hs = <0x0>;
		ti,otap-del-sel-ddr52 = <0x5>;
		ti,otap-del-sel-hs200 = <0x6>;
		ti,otap-del-sel-hs400 = <0x0>;
		ti,itap-del-sel-legacy = <0x10>;
		ti,itap-del-sel-mmc-hs = <0xa>;
		ti,itap-del-sel-ddr52 = <0x3>;
		ti,trm-icp = <0x8>;
		dma-coherent;
		status = "disabled";
	};

	main_sdhci1: mmc@4fb0000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
		assigned-clocks = <&k3_clks 92 0>;
		assigned-clock-parents = <&k3_clks 92 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0x0>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,otap-del-sel-sdr104 = <0x5>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,itap-del-sel-ddr50 = <0x2>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
		sdhci-caps-mask = <0x2 0x0>;
		status = "disabled";
	};

	main_sdhci2: mmc@4f98000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
		assigned-clocks = <&k3_clks 93 0>;
		assigned-clock-parents = <&k3_clks 93 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0x0>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,otap-del-sel-sdr104 = <0x5>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,itap-del-sel-ddr50 = <0x2>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
		sdhci-caps-mask = <0x2 0x0>;
		status = "disabled";
	};

	usbss0: cdns-usb@4104000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4104000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb0: usb@6000000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6000000 0x00 0x10000>,
			      <0x00 0x6010000 0x00 0x10000>,
			      <0x00 0x6020000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	usbss1: cdns-usb@4114000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4114000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb1: usb@6400000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6400000 0x00 0x10000>,
			      <0x00 0x6410000 0x00 0x10000>,
			      <0x00 0x6420000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2000000 0x0 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 187 0>;
		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
		status = "disabled";
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2010000 0x0 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 188 0>;
		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2020000 0x0 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 189 0>;
		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2030000 0x0 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 190 0>;
		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c4: i2c@2040000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2040000 0x0 0x100>;
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 191 0>;
		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c5: i2c@2050000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2050000 0x0 0x100>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 192 0>;
		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c6: i2c@2060000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2060000 0x0 0x100>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 193 0>;
		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	vxe384: video-encoder@4200000 {
		compatible = "img,vxe384";
		reg = <0x00 0x04200000>,
			<0x00 0x100000>;
		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
	};

	d5520: video-decoder@4300000 {
		compatible = "img,d5500-vxd";
		reg = <0x00 0x04300000>,
			<0x00 0x100000>;
		power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	};

	ufs_wrapper: ufs-wrapper@4e80000 {
		compatible = "ti,j721e-ufs";
		reg = <0x0 0x4e80000 0x0 0x100>;
		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 277 1>;
		assigned-clocks = <&k3_clks 277 1>;
		assigned-clock-parents = <&k3_clks 277 4>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		ufs@4e84000 {
			compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
			reg = <0x0 0x4e84000 0x0 0x10000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
			clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
			clock-names = "core_clk", "phy_clk", "ref_clk";
			dma-coherent;
		};
	};

	mhdp: dp-bridge@a000000 {
		compatible = "ti,j721e-mhdp8546";
		/*
		 * Note: we do not map DPTX PHY area, as that is handled by
		 * the PHY driver.
		 */
		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
		reg-names = "mhdptx", "j721e-intg";

		clocks = <&k3_clks 151 36>;

		interrupt-parent = <&gic500>;
		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;

		dp0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
			    reg = <0>;
			};

			port@4 {
			    reg = <4>;
			};
		};
	};

	dsi0: dsi@48000000 {
		compatible = "ti,j721e-dsi";
		reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
		clocks = <&k3_clks 150 1>, <&k3_clks 150 5>;
		clock-names = "dsi_p_clk", "dsi_sys_clk";
		power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
		interrupt-parent = <&gic500>;
		interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&dphy2>;
		phy-names = "dphy";
		status = "disabled";

		dsi0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	dss: dss@4a00000 {
		compatible = "ti,j721e-dss";
		reg =
			<0x00 0x04a00000 0x00 0x10000>, /* common_m */
			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/

			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */

			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */

			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
			<0x00 0x04af0000 0x00 0x10000>; /* wb */

		reg-names = "common_m", "common_s0",
			"common_s1", "common_s2",
			"vidl1", "vidl2","vid1","vid2",
			"ovr1", "ovr2", "ovr3", "ovr4",
			"vp1", "vp2", "vp3", "vp4",
			"wb";

		clocks = <&k3_clks 152 0>,
			 <&k3_clks 152 1>,
			 <&k3_clks 152 4>,
			 <&k3_clks 152 9>,
			 <&k3_clks 152 13>;
		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";

		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;

		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "common_m",
				  "common_s0",
				  "common_s1",
				  "common_s2";

		dss_ports: ports {
		};
	};

	mcasp0: mcasp@2b00000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b00000 0x0 0x2000>,
			<0x0 0x02b08000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 174 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp1: mcasp@2b10000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b10000 0x0 0x2000>,
			<0x0 0x02b18000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 175 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp2: mcasp@2b20000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b20000 0x0 0x2000>,
			<0x0 0x02b28000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 176 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp3: mcasp@2b30000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b30000 0x0 0x2000>,
			<0x0 0x02b38000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 177 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp4: mcasp@2b40000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b40000 0x0 0x2000>,
			<0x0 0x02b48000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 178 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp5: mcasp@2b50000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b50000 0x0 0x2000>,
			<0x0 0x02b58000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 179 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp6: mcasp@2b60000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b60000 0x0 0x2000>,
			<0x0 0x02b68000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 180 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp7: mcasp@2b70000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b70000 0x0 0x2000>,
			<0x0 0x02b78000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 181 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp8: mcasp@2b80000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b80000 0x0 0x2000>,
			<0x0 0x02b88000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 182 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp9: mcasp@2b90000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b90000 0x0 0x2000>,
			<0x0 0x02b98000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 183 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp10: mcasp@2ba0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02ba0000 0x0 0x2000>,
			<0x0 0x02ba8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 184 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp11: mcasp@2bb0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02bb0000 0x0 0x2000>,
			<0x0 0x02bb8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 185 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	watchdog0: watchdog@2200000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2200000 0x0 0x100>;
		clocks = <&k3_clks 252 1>;
		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 252 1>;
		assigned-clock-parents = <&k3_clks 252 5>;
	};

	watchdog1: watchdog@2210000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2210000 0x0 0x100>;
		clocks = <&k3_clks 253 1>;
		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 253 1>;
		assigned-clock-parents = <&k3_clks 253 5>;
	};

	main_r5fss0: r5fss@5c00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
			 <0x5d00000 0x00 0x5d00000 0x20000>;
		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss0_core0: r5f@5c00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5c00000 0x00008000>,
			      <0x5c10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <245>;
			ti,sci-proc-ids = <0x06 0xff>;
			resets = <&k3_reset 245 1>;
			firmware-name = "j7-main-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss0_core1: r5f@5d00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5d00000 0x00008000>,
			      <0x5d10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <246>;
			ti,sci-proc-ids = <0x07 0xff>;
			resets = <&k3_reset 246 1>;
			firmware-name = "j7-main-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	main_r5fss1: r5fss@5e00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
			 <0x5f00000 0x00 0x5f00000 0x20000>;
		power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss1_core0: r5f@5e00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5e00000 0x00008000>,
			      <0x5e10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <247>;
			ti,sci-proc-ids = <0x08 0xff>;
			resets = <&k3_reset 247 1>;
			firmware-name = "j7-main-r5f1_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss1_core1: r5f@5f00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5f00000 0x00008000>,
			      <0x5f10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <248>;
			ti,sci-proc-ids = <0x09 0xff>;
			resets = <&k3_reset 248 1>;
			firmware-name = "j7-main-r5f1_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	c66_0: dsp@4d80800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x80800000 0x00 0x00048000>,
		      <0x4d 0x80e00000 0x00 0x00008000>,
		      <0x4d 0x80f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <142>;
		ti,sci-proc-ids = <0x03 0xff>;
		resets = <&k3_reset 142 1>;
		firmware-name = "j7-c66_0-fw";
		status = "disabled";
	};

	c66_1: dsp@4d81800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x81800000 0x00 0x00048000>,
		      <0x4d 0x81e00000 0x00 0x00008000>,
		      <0x4d 0x81f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <143>;
		ti,sci-proc-ids = <0x04 0xff>;
		resets = <&k3_reset 143 1>;
		firmware-name = "j7-c66_1-fw";
		status = "disabled";
	};

	c71_0: dsp@64800000 {
		compatible = "ti,j721e-c71-dsp";
		reg = <0x00 0x64800000 0x00 0x00080000>,
		      <0x00 0x64e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <15>;
		ti,sci-proc-ids = <0x30 0xff>;
		resets = <&k3_reset 15 1>;
		firmware-name = "j7-c71_0-fw";
		status = "disabled";
	};

	timesync_router: pinctrl@a40000 {
		compatible = "pinctrl-single";
		reg = <0x0 0xa40000 0x0 0x800>;
		#address-cells = <1>;
		#size-cells = <0>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x000107ff>;
		status = "disabled";
	};

	icssg0: icssg@b000000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb000000 0x00 0x80000>;
		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b000000 0x100000>;

		icssg0_mem: memories@0 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg0_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg0_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
						 <&k3_clks 119 1>;  /* icssg0_iclk */
					assigned-clocks = <&icssg0_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 119 1>;
				};

				icssg0_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 3>,	/* icssg0_iep_clk */
						 <&icssg0_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg0_iepclk_mux>;
					assigned-clock-parents = <&icssg0_coreclk_mux>;
				};
			};
		};

		icssg0_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg0_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg0_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru0_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x3000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_0-fw";
		};

		rtu0_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_0-fw";
		};

		tx_pru0_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_0-fw";
		};

		pru0_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x3000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_1-fw";
		};

		rtu0_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_1-fw";
		};

		tx_pru0_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_1-fw";
		};

		icssg0_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 119 1>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	icssg1: icssg@b100000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb100000 0x00 0x80000>;
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b100000 0x100000>;

		icssg1_mem: memories@b100000 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg1_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg1_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
						 <&k3_clks 120 4>;  /* icssg1_iclk */
					assigned-clocks = <&icssg1_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 120 4>;
				};

				icssg1_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 9>,	/* icssg1_iep_clk */
						 <&icssg1_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg1_iepclk_mux>;
					assigned-clock-parents = <&icssg1_coreclk_mux>;
				};
			};
		};

		icssg1_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg1_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg1_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru1_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x4000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_0-fw";
		};

		rtu1_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_0-fw";
		};

		tx_pru1_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_0-fw";
		};

		pru1_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x4000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_1-fw";
		};

		rtu1_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_1-fw";
		};

		tx_pru1_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_1-fw";
		};

		icssg1_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 120 4>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	gpu: gpu@4e20000000 {
		compatible = "ti,j721e-pvr", "img,pvr-ge8430";
		reg = <0x4e 0x20000000 0x00 0x80000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
		power-domain-names = "firmware", "dust";
		clocks = <&k3_clks 125 0>;
		assigned-clocks = <&k3_clks 125 0>;
		assigned-clock-rates = <750000000>;
		clock-names = "core";
	};

	main_mcan0: can@2701000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02701000 0x00 0x200>,
		      <0x00 0x02708000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan1: can@2711000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02711000 0x00 0x200>,
		      <0x00 0x02718000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan2: can@2721000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02721000 0x00 0x200>,
		      <0x00 0x02728000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan3: can@2731000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02731000 0x00 0x200>,
		      <0x00 0x02738000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan4: can@2741000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02741000 0x00 0x200>,
		      <0x00 0x02748000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan5: can@2751000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02751000 0x00 0x200>,
		      <0x00 0x02758000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan6: can@2761000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02761000 0x00 0x200>,
		      <0x00 0x02768000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan7: can@2771000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02771000 0x00 0x200>,
		      <0x00 0x02778000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan8: can@2781000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02781000 0x00 0x200>,
		      <0x00 0x02788000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan9: can@2791000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02791000 0x00 0x200>,
		      <0x00 0x02798000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan10: can@27a1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027a1000 0x00 0x200>,
		      <0x00 0x027a8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan11: can@27b1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027b1000 0x00 0x200>,
		      <0x00 0x027b8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan12: can@27c1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027c1000 0x00 0x200>,
		      <0x00 0x027c8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan13: can@27d1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027d1000 0x00 0x200>,
		      <0x00 0x027d8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_spi0: spi@2100000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02100000 0x00 0x400>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 266 1>;
		status = "disabled";
	};

	main_spi1: spi@2110000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02110000 0x00 0x400>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 267 1>;
		status = "disabled";
	};

	main_spi2: spi@2120000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02120000 0x00 0x400>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 268 1>;
		status = "disabled";
	};

	main_spi3: spi@2130000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02130000 0x00 0x400>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 269 1>;
		status = "okay";
		ti,spi-num-cs = <4>;
	};

	main_spi4: spi@2140000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02140000 0x00 0x400>;
		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 270 1>;
		status = "disabled";
	};

	main_spi5: spi@2150000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02150000 0x00 0x400>;
		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 271 1>;
		status = "okay";
	};

	main_spi6: spi@2160000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02160000 0x00 0x400>;
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 272 1>;
		status = "disabled";
	};

	main_spi7: spi@2170000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02170000 0x00 0x400>;
		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 273 1>;
		status = "disabled";
	};

	main_esm: esm@700000 {
		compatible = "ti,j721e-esm";
		reg = <0x0 0x700000 0x0 0x1000>;
		ti,esm-pins = <344>, <345>;
	};

	dphy2: phy@4480000 {
		compatible = "ti,j721e-dphy";
		reg = <0x0 0x04480000 0x0 0x1000>;
		clocks = <&k3_clks 296 1>, <&k3_clks 296 3>;
		clock-names = "psm", "pll_ref";
		#phy-cells = <0>;
		power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 296 3>;
		assigned-clock-parents = <&k3_clks 296 4>;
		assigned-clock-rates = <19200000>;
		status = "disabled";
	};
};

Hi,

Please configure the SerDes1 lane control of SGMII, by defailt these are enabled for PCIe.
&serdes_ln_ctrl {
    idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
              <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,


Also, can you please confirm are you using SBL boot flow with u-boot or SPL boot flow?
If SBL boot flow without u-boot then you need to unlock CTRL MMRs from SBL.

Best Regards,
Sudheer

Currently it is SPL startup. I tested the following two configurationsCurrently it is SPL startup. I tested the following two configurations
error log is : probe of c000000.ethernet failed with error-110.

&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_QSGMII_LANE1>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
<J721E_SERDES1_LANE0_QSGMII_LANE3>, <J721E_SERDES1_LANE1_QSGMII_LANE4>,

&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_QSGMII_LANE1>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
<J721E_SERDES1_LANE0_SGMII_LANE0>, <J721E_SERDES1_LANE1_SGMII_LANE1>,

Hi,

zs xu said:

&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_QSGMII_LANE1>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
<J721E_SERDES1_LANE0_SGMII_LANE0>, <J721E_SERDES1_LANE1_SGMII_LANE1>,

You are trying to configure from Linux right.

Please make sure u-boot is not enabling the SerDes1.
Also, make sure serdes_ln_ctrl is configured as per required functionality or not?

Best Regards,
Sudheer

The configuration related to serdes1 in the j721e device tree in uboot is deleted
k3-j721e-beagleboneai64-u-boot.dtsi
k3-j721e-beagleboneai64.dts
k3-j721e-common-proc-board-u-boot.dtsi
k3-j721e-common-proc-board.dts
k3-j721e-main.dtsi
k3-j721e-sk-u-boot.dtsi
k3-j721e-sk.dts
But this error still occurs:probe of c000000.ethernet failed with error-110.

Hi,

zs xu said:

But this error still occurs:probe of c000000.ethernet failed with error-110.

Can you please share your dtb file to check whether SerDes1 node and wiz1 are enabled or not?

Best Regards,
Sudheer

This is the dts decompiled from /sys/firmware/fdt
I can see the configurations for serdes@5010000 and wiz@5010000 .

/dts-v1/;

/ {
	serial-number = "0000000000000318";
	model = "Texas Instruments J721e EVM";
	compatible = "ti,j721e-evm\0ti,j721e";
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;

	dma_buf_phys {
		compatible = "ti,dma-buf-phys";
	};

	chosen {
		u-boot,version = "2024.04";
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 root=PARTUUID=89f100e2-02 rw rootfstype=ext4 rootwait";
	};

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		cpu-map {

			cluster0 {
				phandle = <0x7e>;

				core0 {
					cpu = <0x02>;
				};

				core1 {
					cpu = <0x03>;
				};
			};
		};

		cpu@0 {
			compatible = "arm,cortex-a72";
			reg = <0x00>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x04>;
			phandle = <0x02>;
		};

		cpu@1 {
			compatible = "arm,cortex-a72";
			reg = <0x01>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x04>;
			phandle = <0x03>;
		};
	};

	l2-cache0 {
		compatible = "cache";
		cache-level = <0x02>;
		cache-unified;
		cache-size = <0x100000>;
		cache-line-size = <0x40>;
		cache-sets = <0x400>;
		next-level-cache = <0x05>;
		phandle = <0x04>;
	};

	l3-cache0 {
		compatible = "cache";
		cache-level = <0x03>;
		cache-unified;
		phandle = <0x05>;
	};

	firmware {

		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci {
			compatible = "arm,psci-1.0";
			method = "smc";
			phandle = <0x7f>;
		};
	};

	timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
		phandle = <0x80>;
	};

	pmu {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <0x01 0x07 0x04>;
		phandle = <0x81>;
	};

	bus@100000 {
		compatible = "simple-bus";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges = <0x00 0x100000 0x00 0x100000 0x00 0x20000 0x00 0x600000 0x00 0x600000 0x00 0x31100 0x00 0x700000 0x00 0x700000 0x00 0x1000 0x00 0x900000 0x00 0x900000 0x00 0x12000 0x00 0xa40000 0x00 0xa40000 0x00 0x800 0x00 0x6000000 0x00 0x6000000 0x00 0x400000 0x00 0x6400000 0x00 0x6400000 0x00 0x400000 0x00 0x1000000 0x00 0x1000000 0x00 0xaf02400 0x00 0xc000000 0x00 0xc000000 0x00 0xd000000 0x00 0x30000000 0x00 0x30000000 0x00 0xc400000 0x00 0xd000000 0x00 0xd000000 0x00 0x1800000 0x00 0xe000000 0x00 0xe000000 0x00 0x1800000 0x00 0x10000000 0x00 0x10000000 0x00 0x10000000 0x00 0x64800000 0x00 0x64800000 0x00 0x800000 0x00 0x6f000000 0x00 0x6f000000 0x00 0x310000 0x44 0x00 0x44 0x00 0x00 0x8000000 0x44 0x10000000 0x44 0x10000000 0x00 0x8000000 0x4d 0x80800000 0x4d 0x80800000 0x00 0x800000 0x4d 0x81800000 0x4d 0x81800000 0x00 0x800000 0x4e 0x20000000 0x4e 0x20000000 0x00 0x80000 0x00 0x70000000 0x00 0x70000000 0x00 0x800000 0x00 0x28380000 0x00 0x28380000 0x00 0x3880000 0x00 0x40200000 0x00 0x40200000 0x00 0x998400 0x00 0x40f00000 0x00 0x40f00000 0x00 0x20000 0x00 0x41000000 0x00 0x41000000 0x00 0x20000 0x00 0x41400000 0x00 0x41400000 0x00 0x20000 0x00 0x41c00000 0x00 0x41c00000 0x00 0x100000 0x00 0x42040000 0x00 0x42040000 0x00 0x3ac2400 0x00 0x45100000 0x00 0x45100000 0x00 0xc24000 0x00 0x46000000 0x00 0x46000000 0x00 0x200000 0x00 0x47000000 0x00 0x47000000 0x00 0x68400 0x00 0x50000000 0x00 0x50000000 0x00 0x10000000 0x05 0x00 0x05 0x00 0x01 0x00 0x07 0x00 0x07 0x00 0x01 0x00>;
		phandle = <0x82>;

		bus@28380000 {
			compatible = "simple-bus";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x3880000 0x00 0x40200000 0x00 0x40200000 0x00 0x998400 0x00 0x40f00000 0x00 0x40f00000 0x00 0x20000 0x00 0x41000000 0x00 0x41000000 0x00 0x20000 0x00 0x41400000 0x00 0x41400000 0x00 0x20000 0x00 0x41c00000 0x00 0x41c00000 0x00 0x100000 0x00 0x42040000 0x00 0x42040000 0x00 0x3ac2400 0x00 0x45100000 0x00 0x45100000 0x00 0xc24000 0x00 0x46000000 0x00 0x46000000 0x00 0x200000 0x00 0x47000000 0x00 0x47000000 0x00 0x68400 0x00 0x50000000 0x00 0x50000000 0x00 0x10000000 0x05 0x00 0x05 0x00 0x01 0x00 0x07 0x00 0x07 0x00 0x01 0x00>;
			phandle = <0x83>;

			system-controller@44083000 {
				compatible = "ti,k2g-sci";
				ti,host-id = <0x0c>;
				mbox-names = "rx\0tx";
				mboxes = <0x06 0x0b 0x06 0x0d>;
				reg-names = "debug_messages";
				reg = <0x00 0x44083000 0x00 0x1000>;
				phandle = <0x09>;

				power-controller {
					compatible = "ti,sci-pm-domain";
					#power-domain-cells = <0x02>;
					phandle = <0x08>;
				};

				clock-controller {
					compatible = "ti,k2g-sci-clk";
					#clock-cells = <0x02>;
					phandle = <0x07>;
				};

				reset-controller {
					compatible = "ti,sci-reset";
					#reset-cells = <0x02>;
					phandle = <0x1a>;
				};
			};

			syscon@40f00000 {
				compatible = "syscon\0simple-mfd";
				reg = <0x00 0x40f00000 0x00 0x20000>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x40f00000 0x20000>;
				phandle = <0x16>;

				phy@4040 {
					compatible = "ti,am654-phy-gmii-sel";
					reg = <0x4040 0x04>;
					#phy-cells = <0x01>;
					phandle = <0x17>;
				};
			};

			bus@43000000 {
				compatible = "simple-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x43000000 0x20000>;
				phandle = <0x84>;

				chipid@14 {
					compatible = "ti,am654-chipid";
					reg = <0x14 0x04>;
					bootph-all;
					phandle = <0x85>;
				};
			};

			pinctrl@4301c000 {
				compatible = "pinctrl-single";
				reg = <0x00 0x4301c000 0x00 0x178>;
				#pinctrl-cells = <0x01>;
				pinctrl-single,register-width = <0x20>;
				pinctrl-single,function-mask = <0xffffffff>;
				phandle = <0x86>;

				wkup-i2c0-default-pins {
					pinctrl-single,pins = <0xf8 0x60000 0xfc 0x60000>;
					phandle = <0x0c>;
				};

				mcu_fss0_ospi0-default-pins {
					pinctrl-single,pins = <0x00 0x10000 0x2c 0x10000 0x0c 0x50000 0x10 0x50000 0x14 0x50000 0x18 0x50000 0x1c 0x50000 0x20 0x50000 0x24 0x50000 0x28 0x50000 0x08 0x50000 0x3c 0x60006 0x38 0x20006>;
					phandle = <0x0f>;
				};

				mcu-fss0-hpb0-default-pins {
					pinctrl-single,pins = <0x00 0x10001 0x04 0x10001 0x2c 0x10001 0x54 0x10003 0x30 0x10001 0x08 0x50001 0x0c 0x50001 0x10 0x50001 0x14 0x50001 0x18 0x50001 0x1c 0x50001 0x20 0x50001 0x24 0x50001 0x28 0x50001>;
					phandle = <0x0e>;
				};

				mcu-cpsw-default-pins {
					pinctrl-single,pins = <0x58 0x10000 0x5c 0x50000 0x60 0x10000 0x64 0x10000 0x68 0x10000 0x6c 0x10000 0x78 0x50000 0x7c 0x50000 0x80 0x50000 0x84 0x50000 0x70 0x10000 0x74 0x50000>;
					phandle = <0x14>;
				};

				mcu-mdio1-default-pins {
					pinctrl-single,pins = <0x8c 0x10000 0x88 0x50000>;
					phandle = <0x15>;
				};

				wkup-gpio-default-pins {
					pinctrl-single,pins;
					phandle = <0x0b>;
				};

				mcu-rgmii1-default-pins {
					pinctrl-single,pins = <0x84 0x50000 0x80 0x50000 0x7c 0x50000 0x78 0x50000 0x74 0x50000 0x5c 0x50000 0x6c 0x10000 0x68 0x10000 0x64 0x10000 0x60 0x10000 0x70 0x10000 0x58 0x10000>;
					phandle = <0x87>;
				};
			};

			pinctrl@40f04200 {
				compatible = "pinctrl-single";
				reg = <0x00 0x40f04200 0x00 0x28>;
				#pinctrl-cells = <0x01>;
				pinctrl-single,register-width = <0x20>;
				pinctrl-single,function-mask = <0x0f>;
				status = "reserved";
				phandle = <0x88>;
			};

			pinctrl@40f04280 {
				compatible = "pinctrl-single";
				reg = <0x00 0x40f04280 0x00 0x28>;
				#pinctrl-cells = <0x01>;
				pinctrl-single,register-width = <0x20>;
				pinctrl-single,function-mask = <0x0f>;
				status = "reserved";
				phandle = <0x89>;
			};

			sram@41c00000 {
				compatible = "mmio-sram";
				reg = <0x00 0x41c00000 0x00 0x100000>;
				ranges = <0x00 0x00 0x41c00000 0x100000>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				phandle = <0x8a>;
			};

			timer@40400000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40400000 0x00 0x400>;
				interrupts = <0x00 0x330 0x04>;
				clocks = <0x07 0x23 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x23 0x01>;
				assigned-clock-parents = <0x07 0x23 0x02>;
				power-domains = <0x08 0x23 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x8b>;
			};

			timer@40410000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40410000 0x00 0x400>;
				interrupts = <0x00 0x331 0x04>;
				clocks = <0x07 0x47 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x47 0x01 0x07 0x142 0x00>;
				assigned-clock-parents = <0x07 0x47 0x02 0x07 0x142 0x01>;
				power-domains = <0x08 0x47 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x8c>;
			};

			timer@40420000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40420000 0x00 0x400>;
				interrupts = <0x00 0x332 0x04>;
				clocks = <0x07 0x48 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x48 0x01>;
				assigned-clock-parents = <0x07 0x48 0x02>;
				power-domains = <0x08 0x48 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x8d>;
			};

			timer@40430000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40430000 0x00 0x400>;
				interrupts = <0x00 0x333 0x04>;
				clocks = <0x07 0x49 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x49 0x01 0x07 0x143 0x00>;
				assigned-clock-parents = <0x07 0x49 0x02 0x07 0x143 0x01>;
				power-domains = <0x08 0x49 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x8e>;
			};

			timer@40440000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40440000 0x00 0x400>;
				interrupts = <0x00 0x334 0x04>;
				clocks = <0x07 0x4a 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x4a 0x01>;
				assigned-clock-parents = <0x07 0x4a 0x02>;
				power-domains = <0x08 0x4a 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x8f>;
			};

			timer@40450000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40450000 0x00 0x400>;
				interrupts = <0x00 0x335 0x04>;
				clocks = <0x07 0x4b 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x4b 0x01 0x07 0x144 0x00>;
				assigned-clock-parents = <0x07 0x4b 0x02 0x07 0x144 0x01>;
				power-domains = <0x08 0x4b 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x90>;
			};

			timer@40460000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40460000 0x00 0x400>;
				interrupts = <0x00 0x336 0x04>;
				clocks = <0x07 0x4c 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x4c 0x01>;
				assigned-clock-parents = <0x07 0x4c 0x02>;
				power-domains = <0x08 0x4c 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x91>;
			};

			timer@40470000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40470000 0x00 0x400>;
				interrupts = <0x00 0x337 0x04>;
				clocks = <0x07 0x4d 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x4d 0x01 0x07 0x145 0x00>;
				assigned-clock-parents = <0x07 0x4d 0x02 0x07 0x145 0x01>;
				power-domains = <0x08 0x4d 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x92>;
			};

			timer@40480000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40480000 0x00 0x400>;
				interrupts = <0x00 0x338 0x04>;
				clocks = <0x07 0x4e 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x4e 0x01>;
				assigned-clock-parents = <0x07 0x4e 0x02>;
				power-domains = <0x08 0x4e 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x93>;
			};

			timer@40490000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x40490000 0x00 0x400>;
				interrupts = <0x00 0x339 0x04>;
				clocks = <0x07 0x4f 0x01>;
				clock-names = "fck";
				assigned-clocks = <0x07 0x4f 0x01 0x07 0x146 0x00>;
				assigned-clock-parents = <0x07 0x4f 0x02 0x07 0x146 0x01>;
				power-domains = <0x08 0x4f 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x94>;
			};

			serial@42300000 {
				compatible = "ti,j721e-uart\0ti,am654-uart";
				reg = <0x00 0x42300000 0x00 0x100>;
				interrupts = <0x00 0x381 0x04>;
				clock-frequency = <0x2dc6c00>;
				current-speed = <0x1c200>;
				power-domains = <0x08 0x11f 0x01>;
				clocks = <0x07 0x11f 0x00>;
				clock-names = "fclk";
				status = "reserved";
				phandle = <0x95>;
			};

			serial@40a00000 {
				compatible = "ti,j721e-uart\0ti,am654-uart";
				reg = <0x00 0x40a00000 0x00 0x100>;
				interrupts = <0x00 0x34e 0x04>;
				clock-frequency = <0x5b8d800>;
				current-speed = <0x1c200>;
				power-domains = <0x08 0x95 0x01>;
				clocks = <0x07 0x95 0x00>;
				clock-names = "fclk";
				status = "reserved";
				phandle = <0x96>;
			};

			interrupt-controller@42200000 {
				compatible = "ti,sci-intr";
				reg = <0x00 0x42200000 0x00 0x400>;
				ti,intr-trigger-type = <0x01>;
				interrupt-controller;
				interrupt-parent = <0x01>;
				#interrupt-cells = <0x01>;
				ti,sci = <0x09>;
				ti,sci-dev-id = <0x89>;
				ti,interrupt-ranges = <0x10 0x3c0 0x10>;
				phandle = <0x0a>;
			};

			gpio@42110000 {
				compatible = "ti,j721e-gpio\0ti,keystone-gpio";
				reg = <0x00 0x42110000 0x00 0x100>;
				gpio-controller;
				#gpio-cells = <0x02>;
				interrupt-parent = <0x0a>;
				interrupts = <0x67 0x68 0x69 0x6a 0x6b 0x6c>;
				interrupt-controller;
				#interrupt-cells = <0x02>;
				ti,ngpio = <0x54>;
				ti,davinci-gpio-unbanked = <0x00>;
				power-domains = <0x08 0x71 0x01>;
				clocks = <0x07 0x71 0x00>;
				clock-names = "gpio";
				status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <0x0b>;
				phandle = <0x97>;
			};

			gpio@42100000 {
				compatible = "ti,j721e-gpio\0ti,keystone-gpio";
				reg = <0x00 0x42100000 0x00 0x100>;
				gpio-controller;
				#gpio-cells = <0x02>;
				interrupt-parent = <0x0a>;
				interrupts = <0x70 0x71 0x72 0x73 0x74 0x75>;
				interrupt-controller;
				#interrupt-cells = <0x02>;
				ti,ngpio = <0x54>;
				ti,davinci-gpio-unbanked = <0x00>;
				power-domains = <0x08 0x72 0x01>;
				clocks = <0x07 0x72 0x00>;
				clock-names = "gpio";
				status = "disabled";
				phandle = <0x98>;
			};

			i2c@40b00000 {
				compatible = "ti,j721e-i2c\0ti,omap4-i2c";
				reg = <0x00 0x40b00000 0x00 0x100>;
				interrupts = <0x00 0x354 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clock-names = "fck";
				clocks = <0x07 0xc2 0x00>;
				power-domains = <0x08 0xc2 0x01>;
				status = "disabled";
				phandle = <0x99>;
			};

			i2c@40b10000 {
				compatible = "ti,j721e-i2c\0ti,omap4-i2c";
				reg = <0x00 0x40b10000 0x00 0x100>;
				interrupts = <0x00 0x355 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clock-names = "fck";
				clocks = <0x07 0xc3 0x00>;
				power-domains = <0x08 0xc3 0x01>;
				status = "disabled";
				phandle = <0x9a>;
			};

			i2c@42120000 {
				compatible = "ti,j721e-i2c\0ti,omap4-i2c";
				reg = <0x00 0x42120000 0x00 0x100>;
				interrupts = <0x00 0x380 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clock-names = "fck";
				clocks = <0x07 0xc5 0x00>;
				power-domains = <0x08 0xc5 0x00>;
				status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <0x0c>;
				clock-frequency = <0x61a80>;
				phandle = <0x9b>;
			};

			bus@47000000 {
				compatible = "simple-bus";
				reg = <0x00 0x47000000 0x00 0x100>;
				#address-cells = <0x02>;
				#size-cells = <0x02>;
				ranges;
				phandle = <0x9c>;

				mux-controller@47000004 {
					compatible = "reg-mux";
					reg = <0x00 0x47000004 0x00 0x02>;
					#mux-control-cells = <0x01>;
					mux-reg-masks = <0x04 0x02>;
					phandle = <0x0d>;
				};

				hyperbus@47034000 {
					compatible = "ti,am654-hbmc";
					reg = <0x00 0x47034000 0x00 0x100 0x05 0x00 0x01 0x00>;
					power-domains = <0x08 0x66 0x01>;
					clocks = <0x07 0x66 0x00>;
					assigned-clocks = <0x07 0x66 0x05>;
					assigned-clock-rates = <0x13de4355>;
					#address-cells = <0x02>;
					#size-cells = <0x01>;
					mux-controls = <0x0d 0x00>;
					status = "disabled";
					pinctrl-names = "default";
					pinctrl-0 = <0x0e>;
					ranges = <0x00 0x00 0x05 0x00 0x4000000 0x01 0x00 0x05 0x4000000 0x800000>;
					phandle = <0x9d>;

					flash@0,0 {
						compatible = "cypress,hyperflash\0cfi-flash";
						reg = <0x00 0x00 0x4000000>;

						partitions {
							compatible = "fixed-partitions";
							#address-cells = <0x01>;
							#size-cells = <0x01>;

							partition@0 {
								label = "hbmc.tiboot3";
								reg = <0x00 0x80000>;
							};

							partition@80000 {
								label = "hbmc.tispl";
								reg = <0x80000 0x200000>;
							};

							partition@280000 {
								label = "hbmc.u-boot";
								reg = <0x280000 0x400000>;
							};

							partition@680000 {
								label = "hbmc.env";
								reg = <0x680000 0x40000>;
							};

							partition@6c0000 {
								label = "hbmc.sysfw";
								reg = <0x6c0000 0x100000>;
							};

							partition@800000 {
								label = "hbmc.rootfs";
								reg = <0x800000 0x3800000>;
							};
						};
					};
				};

				spi@47040000 {
					compatible = "ti,am654-ospi\0cdns,qspi-nor";
					reg = <0x00 0x47040000 0x00 0x100 0x05 0x00 0x01 0x00>;
					interrupts = <0x00 0x348 0x04>;
					cdns,fifo-depth = <0x100>;
					cdns,fifo-width = <0x04>;
					cdns,trigger-address = <0x00>;
					clocks = <0x07 0x67 0x00>;
					assigned-clocks = <0x07 0x67 0x00>;
					assigned-clock-parents = <0x07 0x67 0x02>;
					assigned-clock-rates = <0x9ef21aa>;
					power-domains = <0x08 0x67 0x01>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					status = "okay";
					pinctrl-names = "default";
					pinctrl-0 = <0x0f>;
					phandle = <0x9e>;

					flash@0 {
						compatible = "jedec,spi-nor";
						reg = <0x00>;
						spi-tx-bus-width = <0x08>;
						spi-rx-bus-width = <0x08>;
						spi-max-frequency = <0x17d7840>;
						cdns,tshsl-ns = <0x3c>;
						cdns,tsd2d-ns = <0x3c>;
						cdns,tchsh-ns = <0x3c>;
						cdns,tslch-ns = <0x3c>;
						cdns,read-delay = <0x04>;

						partitions {
							compatible = "fixed-partitions";
							#address-cells = <0x01>;
							#size-cells = <0x01>;

							partition@0 {
								label = "ospi.tiboot3";
								reg = <0x00 0x80000>;
							};

							partition@80000 {
								label = "ospi.tispl";
								reg = <0x80000 0x200000>;
							};

							partition@280000 {
								label = "ospi.u-boot";
								reg = <0x280000 0x400000>;
							};

							partition@680000 {
								label = "ospi.env";
								reg = <0x680000 0x40000>;
							};

							partition@6c0000 {
								label = "ospi.sysfw";
								reg = <0x6c0000 0x100000>;
							};

							partition@7c0000 {
								label = "ospi.env.backup";
								reg = <0x7c0000 0x40000>;
							};

							partition@800000 {
								label = "ospi.rootfs";
								reg = <0x800000 0x37c0000>;
							};

							partition@3fc0000 {
								label = "ospi.phypattern";
								reg = <0x3fc0000 0x40000>;
							};
						};
					};
				};

				spi@47050000 {
					compatible = "ti,am654-ospi\0cdns,qspi-nor";
					reg = <0x00 0x47050000 0x00 0x100 0x07 0x00 0x01 0x00>;
					interrupts = <0x00 0x349 0x04>;
					cdns,fifo-depth = <0x100>;
					cdns,fifo-width = <0x04>;
					cdns,trigger-address = <0x00>;
					clocks = <0x07 0x68 0x00>;
					power-domains = <0x08 0x68 0x01>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					status = "disabled";
					phandle = <0x9f>;
				};
			};

			tscadc@40200000 {
				compatible = "ti,am3359-tscadc";
				reg = <0x00 0x40200000 0x00 0x1000>;
				interrupts = <0x00 0x35c 0x04>;
				power-domains = <0x08 0x00 0x01>;
				clocks = <0x07 0x00 0x01>;
				assigned-clocks = <0x07 0x00 0x03>;
				assigned-clock-rates = <0x3938700>;
				clock-names = "fck";
				dmas = <0x10 0x7400 0x10 0x7401>;
				dma-names = "fifo0\0fifo1";
				status = "okay";
				phandle = <0xa0>;

				adc {
					#io-channel-cells = <0x01>;
					compatible = "ti,am3359-adc";
					ti,adc-channels = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>;
				};
			};

			tscadc@40210000 {
				compatible = "ti,am3359-tscadc";
				reg = <0x00 0x40210000 0x00 0x1000>;
				interrupts = <0x00 0x35d 0x04>;
				power-domains = <0x08 0x01 0x01>;
				clocks = <0x07 0x01 0x01>;
				assigned-clocks = <0x07 0x01 0x03>;
				assigned-clock-rates = <0x3938700>;
				clock-names = "fck";
				dmas = <0x10 0x7402 0x10 0x7403>;
				dma-names = "fifo0\0fifo1";
				status = "okay";
				phandle = <0xa1>;

				adc {
					#io-channel-cells = <0x01>;
					compatible = "ti,am3359-adc";
					ti,adc-channels = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>;
				};
			};

			bus@28380000 {
				compatible = "simple-bus";
				#address-cells = <0x02>;
				#size-cells = <0x02>;
				ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x3880000>;
				dma-coherent;
				dma-ranges;
				ti,sci-dev-id = <0xe8>;
				phandle = <0xa2>;

				ringacc@2b800000 {
					compatible = "ti,am654-navss-ringacc";
					reg = <0x00 0x2b800000 0x00 0x400000 0x00 0x2b000000 0x00 0x400000 0x00 0x28590000 0x00 0x100 0x00 0x2a500000 0x00 0x40000 0x00 0x28440000 0x00 0x40000>;
					reg-names = "rt\0fifos\0proxy_gcfg\0proxy_target\0cfg";
					ti,num-rings = <0x11e>;
					ti,sci-rm-range-gp-rings = <0x01>;
					ti,sci = <0x09>;
					ti,sci-dev-id = <0xeb>;
					msi-parent = <0x11>;
					phandle = <0x12>;
				};

				dma-controller@285c0000 {
					compatible = "ti,j721e-navss-mcu-udmap";
					reg = <0x00 0x285c0000 0x00 0x100 0x00 0x2a800000 0x00 0x40000 0x00 0x2aa00000 0x00 0x40000 0x00 0x284a0000 0x00 0x4000 0x00 0x284c0000 0x00 0x4000 0x00 0x28400000 0x00 0x2000>;
					reg-names = "gcfg\0rchanrt\0tchanrt\0tchan\0rchan\0rflow";
					msi-parent = <0x11>;
					#dma-cells = <0x01>;
					ti,sci = <0x09>;
					ti,sci-dev-id = <0xec>;
					ti,ringacc = <0x12>;
					ti,sci-rm-range-tchan = <0x0d 0x0f>;
					ti,sci-rm-range-rchan = <0x0a 0x0b>;
					ti,sci-rm-range-rflow = <0x00>;
					phandle = <0x13>;
				};
			};

			mailbox@2a480000 {
				compatible = "ti,am654-secure-proxy";
				#mbox-cells = <0x01>;
				reg-names = "target_data\0rt\0scfg";
				reg = <0x00 0x2a480000 0x00 0x80000 0x00 0x2a380000 0x00 0x80000 0x00 0x2a400000 0x00 0x80000>;
				status = "disabled";
				phandle = <0xa3>;
			};

			ethernet@46000000 {
				compatible = "ti,j721e-cpsw-nuss";
				#address-cells = <0x02>;
				#size-cells = <0x02>;
				reg = <0x00 0x46000000 0x00 0x200000>;
				reg-names = "cpsw_nuss";
				ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
				dma-coherent;
				clocks = <0x07 0x12 0x16>;
				clock-names = "fck";
				power-domains = <0x08 0x12 0x01>;
				dmas = <0x13 0xf000 0x13 0xf001 0x13 0xf002 0x13 0xf003 0x13 0xf004 0x13 0xf005 0x13 0xf006 0x13 0xf007 0x13 0x7000>;
				dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";
				pinctrl-names = "default";
				pinctrl-0 = <0x14 0x15>;
				phandle = <0xa4>;

				ethernet-ports {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					port@1 {
						reg = <0x01>;
						ti,mac-only;
						label = "port1";
						ti,syscon-efuse = <0x16 0x200>;
						phys = <0x17 0x01>;
						phy-mode = "rgmii-rxid";
						phy-handle = <0x18>;
						phandle = <0xa5>;
					};
				};

				mdio@f00 {
					compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
					reg = <0x00 0xf00 0x00 0x100>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					clocks = <0x07 0x12 0x16>;
					clock-names = "fck";
					bus_freq = <0xf4240>;
					phandle = <0xa6>;

					ethernet-phy@2 {
						reg = <0x02>;
						mv88q2220-reset-gpios = <0x19 0x4c 0x00>;
						reset-assert-us = <0x2710>;
						reset-deassert-us = <0x2710>;
						phandle = <0x18>;
					};
				};

				cpts@3d000 {
					compatible = "ti,am65-cpts";
					reg = <0x00 0x3d000 0x00 0x400>;
					clocks = <0x07 0x12 0x02>;
					clock-names = "cpts";
					interrupts-extended = <0x01 0x00 0x35a 0x04>;
					interrupt-names = "cpts";
					ti,cpts-ext-ts-inputs = <0x04>;
					ti,cpts-periodic-outputs = <0x02>;
					ti,pps = <0x03 0x01>;
				};
			};

			r5fss@41000000 {
				compatible = "ti,j721e-r5fss";
				ti,cluster-mode = <0x01>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x41000000 0x00 0x41000000 0x20000 0x41400000 0x00 0x41400000 0x20000>;
				power-domains = <0x08 0xf9 0x01>;
				phandle = <0xa7>;

				r5f@41000000 {
					compatible = "ti,j721e-r5f";
					reg = <0x41000000 0x8000 0x41010000 0x8000>;
					reg-names = "atcm\0btcm";
					ti,sci = <0x09>;
					ti,sci-dev-id = <0xfa>;
					ti,sci-proc-ids = <0x01 0xff>;
					resets = <0x1a 0xfa 0x01>;
					firmware-name = "j7-mcu-r5f0_0-fw";
					ti,atcm-enable = <0x01>;
					ti,btcm-enable = <0x01>;
					ti,loczrama = <0x01>;
					mboxes = <0x1b 0x1c>;
					memory-region = <0x185 0x186>;
					phandle = <0xa8>;
				};

				r5f@41400000 {
					compatible = "ti,j721e-r5f";
					reg = <0x41400000 0x8000 0x41410000 0x8000>;
					reg-names = "atcm\0btcm";
					ti,sci = <0x09>;
					ti,sci-dev-id = <0xfb>;
					ti,sci-proc-ids = <0x02 0xff>;
					resets = <0x1a 0xfb 0x01>;
					firmware-name = "j7-mcu-r5f0_1-fw";
					ti,atcm-enable = <0x01>;
					ti,btcm-enable = <0x01>;
					ti,loczrama = <0x01>;
					mboxes = <0x1b 0x1f>;
					memory-region = <0x187 0x188>;
					phandle = <0xa9>;
				};
			};

			can@40528000 {
				compatible = "bosch,m_can";
				reg = <0x00 0x40528000 0x00 0x200 0x00 0x40500000 0x00 0x8000>;
				reg-names = "m_can\0message_ram";
				power-domains = <0x08 0xac 0x01>;
				clocks = <0x07 0xac 0x00 0x07 0xac 0x01>;
				clock-names = "hclk\0cclk";
				interrupts = <0x00 0x340 0x04 0x00 0x341 0x04>;
				interrupt-names = "int0\0int1";
				bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
				status = "disabled";
				phandle = <0xaa>;
			};

			can@40568000 {
				compatible = "bosch,m_can";
				reg = <0x00 0x40568000 0x00 0x200 0x00 0x40540000 0x00 0x8000>;
				reg-names = "m_can\0message_ram";
				power-domains = <0x08 0xad 0x01>;
				clocks = <0x07 0xad 0x00 0x07 0xad 0x01>;
				clock-names = "hclk\0cclk";
				interrupts = <0x00 0x343 0x04 0x00 0x344 0x04>;
				interrupt-names = "int0\0int1";
				bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
				status = "disabled";
				phandle = <0xab>;
			};

			spi@40300000 {
				compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
				reg = <0x00 0x40300000 0x00 0x400>;
				interrupts = <0x00 0x350 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				power-domains = <0x08 0x112 0x01>;
				clocks = <0x07 0x112 0x00>;
				status = "disabled";
				phandle = <0xac>;
			};

			spi@40310000 {
				compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
				reg = <0x00 0x40310000 0x00 0x400>;
				interrupts = <0x00 0x351 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				power-domains = <0x08 0x113 0x01>;
				clocks = <0x07 0x113 0x00>;
				status = "disabled";
				phandle = <0xad>;
			};

			spi@40320000 {
				compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
				reg = <0x00 0x40320000 0x00 0x400>;
				interrupts = <0x00 0x352 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				power-domains = <0x08 0x114 0x01>;
				clocks = <0x07 0x114 0x00>;
				status = "disabled";
				phandle = <0xae>;
			};

			temperature-sensor@42040000 {
				compatible = "ti,j721e-vtm";
				reg = <0x00 0x42040000 0x00 0x350 0x00 0x42050000 0x00 0x350 0x00 0x43000300 0x00 0x10>;
				power-domains = <0x08 0x9a 0x01>;
				#thermal-sensor-cells = <0x01>;
				phandle = <0x78>;
			};

			esm@40800000 {
				compatible = "ti,j721e-esm";
				reg = <0x00 0x40800000 0x00 0x1000>;
				ti,esm-pins = <0x5f>;
				bootph-pre-ram;
				phandle = <0xaf>;
			};
		};

		sram@70000000 {
			compatible = "mmio-sram";
			reg = <0x00 0x70000000 0x00 0x7f0000>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x00 0x70000000 0x7f0000>;
			phandle = <0xb0>;

			atf-sram@0 {
				reg = <0x00 0x20000>;
			};
		};

		scm-conf@100000 {
			compatible = "ti,j721e-system-controller\0syscon\0simple-mfd";
			reg = <0x00 0x100000 0x00 0x1c000>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x00 0x100000 0x1c000>;
			phandle = <0x47>;

			mux-controller@4080 {
				compatible = "reg-mux";
				reg = <0x4080 0x50>;
				#mux-control-cells = <0x01>;
				mux-reg-masks = <0x00 0x03 0x04 0x03 0x10 0x03 0x14 0x03 0x20 0x03 0x24 0x03 0x30 0x03 0x34 0x03 0x40 0x03 0x44 0x03 0x48 0x03 0x4c 0x03>;
				idle-states = <0x01 0x00 0x01 0x01 0x01 0x01 0x02 0x02 0x00 0x00 0x00 0x00>;
				phandle = <0xb1>;
			};

			phy@4044 {
				compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
				ti,qsgmii-main-ports = <0x02 0x02>;
				reg = <0x4044 0x20>;
				#phy-cells = <0x01>;
				phandle = <0x25>;
			};

			mux-controller@4000 {
				compatible = "reg-mux";
				reg = <0x4000 0x20>;
				#mux-control-cells = <0x01>;
				mux-reg-masks = <0x00 0x8000000 0x10 0x8000000>;
				phandle = <0xb2>;
			};

			clock-controller@4140 {
				compatible = "ti,am654-ehrpwm-tbclk";
				reg = <0x4140 0x18>;
				#clock-cells = <0x01>;
				phandle = <0x22>;
			};
		};

		pwm@3000000 {
			compatible = "ti,am654-ehrpwm\0ti,am3352-ehrpwm";
			#pwm-cells = <0x03>;
			reg = <0x00 0x3000000 0x00 0x100>;
			power-domains = <0x08 0x53 0x01>;
			clocks = <0x22 0x00 0x07 0x53 0x00>;
			clock-names = "tbclk\0fck";
			status = "disabled";
			phandle = <0xb3>;
		};

		pwm@3010000 {
			compatible = "ti,am654-ehrpwm\0ti,am3352-ehrpwm";
			#pwm-cells = <0x03>;
			reg = <0x00 0x3010000 0x00 0x100>;
			power-domains = <0x08 0x54 0x01>;
			clocks = <0x22 0x01 0x07 0x54 0x00>;
			clock-names = "tbclk\0fck";
			status = "disabled";
			phandle = <0xb4>;
		};

		pwm@3020000 {
			compatible = "ti,am654-ehrpwm\0ti,am3352-ehrpwm";
			#pwm-cells = <0x03>;
			reg = <0x00 0x3020000 0x00 0x100>;
			power-domains = <0x08 0x55 0x01>;
			clocks = <0x22 0x02 0x07 0x55 0x00>;
			clock-names = "tbclk\0fck";
			status = "disabled";
			phandle = <0xb5>;
		};

		pwm@3030000 {
			compatible = "ti,am654-ehrpwm\0ti,am3352-ehrpwm";
			#pwm-cells = <0x03>;
			reg = <0x00 0x3030000 0x00 0x100>;
			power-domains = <0x08 0x56 0x01>;
			clocks = <0x22 0x03 0x07 0x56 0x00>;
			clock-names = "tbclk\0fck";
			status = "disabled";
			phandle = <0xb6>;
		};

		pwm@3040000 {
			compatible = "ti,am654-ehrpwm\0ti,am3352-ehrpwm";
			#pwm-cells = <0x03>;
			reg = <0x00 0x3040000 0x00 0x100>;
			power-domains = <0x08 0x57 0x01>;
			clocks = <0x22 0x04 0x07 0x57 0x00>;
			clock-names = "tbclk\0fck";
			status = "disabled";
			phandle = <0xb7>;
		};

		pwm@3050000 {
			compatible = "ti,am654-ehrpwm\0ti,am3352-ehrpwm";
			#pwm-cells = <0x03>;
			reg = <0x00 0x3050000 0x00 0x100>;
			power-domains = <0x08 0x58 0x01>;
			clocks = <0x22 0x05 0x07 0x58 0x00>;
			clock-names = "tbclk\0fck";
			status = "disabled";
			phandle = <0xb8>;
		};

		interrupt-controller@1800000 {
			compatible = "arm,gic-v3";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges;
			#interrupt-cells = <0x03>;
			interrupt-controller;
			reg = <0x00 0x1800000 0x00 0x10000 0x00 0x1900000 0x00 0x100000 0x00 0x6f000000 0x00 0x2000 0x00 0x6f010000 0x00 0x1000 0x00 0x6f020000 0x00 0x2000>;
			interrupts = <0x01 0x09 0x04>;
			phandle = <0x01>;

			msi-controller@1820000 {
				compatible = "arm,gic-v3-its";
				reg = <0x00 0x1820000 0x00 0x10000>;
				socionext,synquacer-pre-its = <0x1000000 0x400000>;
				msi-controller;
				#msi-cells = <0x01>;
				phandle = <0x48>;
			};
		};

		interrupt-controller@a00000 {
			compatible = "ti,sci-intr";
			reg = <0x00 0xa00000 0x00 0x800>;
			ti,intr-trigger-type = <0x01>;
			interrupt-controller;
			interrupt-parent = <0x01>;
			#interrupt-cells = <0x01>;
			ti,sci = <0x09>;
			ti,sci-dev-id = <0x83>;
			ti,interrupt-ranges = <0x08 0x188 0x38>;
			phandle = <0x4d>;
		};

		bus@30000000 {
			compatible = "simple-bus";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0xc400000>;
			dma-coherent;
			dma-ranges;
			ti,sci-dev-id = <0xc7>;
			phandle = <0xb9>;

			interrupt-controller@310e0000 {
				compatible = "ti,sci-intr";
				reg = <0x00 0x310e0000 0x00 0x4000>;
				ti,intr-trigger-type = <0x04>;
				interrupt-controller;
				interrupt-parent = <0x01>;
				#interrupt-cells = <0x01>;
				ti,sci = <0x09>;
				ti,sci-dev-id = <0xd5>;
				ti,interrupt-ranges = <0x00 0x40 0x40 0x40 0x1c0 0x40 0x80 0x2a0 0x40>;
				phandle = <0x23>;
			};

			interrupt-controller@33d00000 {
				compatible = "ti,sci-inta";
				reg = <0x00 0x33d00000 0x00 0x100000>;
				interrupt-controller;
				interrupt-parent = <0x23>;
				msi-controller;
				#interrupt-cells = <0x00>;
				ti,sci = <0x09>;
				ti,sci-dev-id = <0xd1>;
				ti,interrupt-ranges = <0x00 0x00 0x100>;
				phandle = <0x11>;
			};

			mailbox@32c00000 {
				compatible = "ti,am654-secure-proxy";
				#mbox-cells = <0x01>;
				reg-names = "target_data\0rt\0scfg";
				reg = <0x00 0x32c00000 0x00 0x100000 0x00 0x32400000 0x00 0x100000 0x00 0x32800000 0x00 0x100000>;
				interrupt-names = "rx_011";
				interrupts = <0x00 0x25 0x04>;
				phandle = <0x06>;
			};

			iommu@36600000 {
				compatible = "arm,smmu-v3";
				reg = <0x00 0x36600000 0x00 0x100000>;
				interrupt-parent = <0x01>;
				interrupts = <0x00 0x304 0x01 0x00 0x300 0x01>;
				interrupt-names = "eventq\0gerror";
				#iommu-cells = <0x01>;
				phandle = <0xba>;
			};

			spinlock@30e00000 {
				compatible = "ti,am654-hwspinlock";
				reg = <0x00 0x30e00000 0x00 0x1000>;
				#hwlock-cells = <0x01>;
				phandle = <0xbb>;
			};

			mailbox@31f80000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f80000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "okay";
				interrupts = <0x1b4>;
				phandle = <0x1b>;

				mbox-mcu-r5fss0-core0 {
					ti,mbox-rx = <0x00 0x00 0x00>;
					ti,mbox-tx = <0x01 0x00 0x00>;
					phandle = <0x1c>;
				};

				mbox-mcu-r5fss0-core1 {
					ti,mbox-rx = <0x02 0x00 0x00>;
					ti,mbox-tx = <0x03 0x00 0x00>;
					phandle = <0x1f>;
				};
			};

			mailbox@31f81000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f81000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "okay";
				interrupts = <0x1b0>;
				phandle = <0x58>;

				mbox-main-r5fss0-core0 {
					ti,mbox-rx = <0x00 0x00 0x00>;
					ti,mbox-tx = <0x01 0x00 0x00>;
					phandle = <0x59>;
				};

				mbox-main-r5fss0-core1 {
					ti,mbox-rx = <0x02 0x00 0x00>;
					ti,mbox-tx = <0x03 0x00 0x00>;
					phandle = <0x5c>;
				};
			};

			mailbox@31f82000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f82000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "okay";
				interrupts = <0x1ac>;
				phandle = <0x5f>;

				mbox-main-r5fss1-core0 {
					ti,mbox-rx = <0x00 0x00 0x00>;
					ti,mbox-tx = <0x01 0x00 0x00>;
					phandle = <0x60>;
				};

				mbox-main-r5fss1-core1 {
					ti,mbox-rx = <0x02 0x00 0x00>;
					ti,mbox-tx = <0x03 0x00 0x00>;
					phandle = <0x63>;
				};
			};

			mailbox@31f83000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f83000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "okay";
				interrupts = <0x1a8>;
				phandle = <0x66>;

				mbox-c66-0 {
					ti,mbox-rx = <0x00 0x00 0x00>;
					ti,mbox-tx = <0x01 0x00 0x00>;
					phandle = <0x67>;
				};

				mbox-c66-1 {
					ti,mbox-rx = <0x02 0x00 0x00>;
					ti,mbox-tx = <0x03 0x00 0x00>;
					phandle = <0x6a>;
				};
			};

			mailbox@31f84000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f84000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "okay";
				interrupts = <0x1a4>;
				phandle = <0x6d>;

				mbox-c71-0 {
					ti,mbox-rx = <0x00 0x00 0x00>;
					ti,mbox-tx = <0x01 0x00 0x00>;
					phandle = <0x6e>;
				};
			};

			mailbox@31f85000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f85000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "disabled";
				phandle = <0xbc>;
			};

			mailbox@31f86000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f86000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "disabled";
				phandle = <0xbd>;
			};

			mailbox@31f87000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f87000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "disabled";
				phandle = <0xbe>;
			};

			mailbox@31f88000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f88000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "disabled";
				phandle = <0xbf>;
			};

			mailbox@31f89000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f89000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "disabled";
				phandle = <0xc0>;
			};

			mailbox@31f8a000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f8a000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "disabled";
				phandle = <0xc1>;
			};

			mailbox@31f8b000 {
				compatible = "ti,am654-mailbox";
				reg = <0x00 0x31f8b000 0x00 0x200>;
				#mbox-cells = <0x01>;
				ti,mbox-num-users = <0x04>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x23>;
				status = "disabled";
				phandle = <0xc2>;
			};

			ringacc@3c000000 {
				compatible = "ti,am654-navss-ringacc";
				reg = <0x00 0x3c000000 0x00 0x400000 0x00 0x38000000 0x00 0x400000 0x00 0x31120000 0x00 0x100 0x00 0x33000000 0x00 0x40000 0x00 0x31080000 0x00 0x40000>;
				reg-names = "rt\0fifos\0proxy_gcfg\0proxy_target\0cfg";
				ti,num-rings = <0x400>;
				ti,sci-rm-range-gp-rings = <0x01>;
				ti,sci = <0x09>;
				ti,sci-dev-id = <0xd3>;
				msi-parent = <0x11>;
				phandle = <0x24>;
			};

			dma-controller@31150000 {
				compatible = "ti,j721e-navss-main-udmap";
				reg = <0x00 0x31150000 0x00 0x100 0x00 0x34000000 0x00 0x100000 0x00 0x35000000 0x00 0x100000 0x00 0x30b00000 0x00 0x20000 0x00 0x30c00000 0x00 0x10000 0x00 0x30d00000 0x00 0x8000>;
				reg-names = "gcfg\0rchanrt\0tchanrt\0tchan\0rchan\0rflow";
				msi-parent = <0x11>;
				#dma-cells = <0x01>;
				ti,sci = <0x09>;
				ti,sci-dev-id = <0xd4>;
				ti,ringacc = <0x24>;
				ti,sci-rm-range-tchan = <0x0d 0x0f 0x10>;
				ti,sci-rm-range-rchan = <0x0a 0x0b 0x0c>;
				ti,sci-rm-range-rflow = <0x00>;
				phandle = <0x10>;
			};

			cpts@310d0000 {
				compatible = "ti,j721e-cpts";
				reg = <0x00 0x310d0000 0x00 0x400>;
				reg-names = "cpts";
				clocks = <0x07 0xc9 0x01>;
				clock-names = "cpts";
				interrupts-extended = <0x23 0x187>;
				interrupt-names = "cpts";
				ti,cpts-periodic-outputs = <0x06>;
				ti,cpts-ext-ts-inputs = <0x08>;
			};
		};

		ethernet@c000000 {
			compatible = "ti,j721e-cpswxg-nuss";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			reg = <0x00 0xc000000 0x00 0x200000>;
			reg-names = "cpsw_nuss";
			ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
			clocks = <0x07 0x13 0x59>;
			clock-names = "fck";
			power-domains = <0x08 0x13 0x01>;
			dmas = <0x10 0xca00 0x10 0xca01 0x10 0xca02 0x10 0xca03 0x10 0xca04 0x10 0xca05 0x10 0xca06 0x10 0xca07 0x10 0x4a00>;
			dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";
			status = "okay";
			phandle = <0xc3>;

			ethernet-ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@1 {
					reg = <0x01>;
					ti,mac-only;
					label = "port1";
					status = "disabled";
					phandle = <0xc4>;
				};

				port@2 {
					reg = <0x02>;
					ti,mac-only;
					label = "port2";
					status = "disabled";
					phandle = <0xc5>;
				};

				port@3 {
					reg = <0x03>;
					ti,mac-only;
					label = "port3";
					phy-mode = "sgmii";
					phys = <0x25 0x03 0x26>;
					mac-address = [00 00 00 00 00 00];
					phy-names = "mac\0serdes";
					status = "okay";
					phandle = <0xc6>;

					fixed-link {
						speed = <0x3e8>;
						full-duplex;
					};
				};

				port@4 {
					reg = <0x04>;
					ti,mac-only;
					label = "port4";
					status = "disabled";
					phandle = <0xc7>;
				};

				port@5 {
					reg = <0x05>;
					ti,mac-only;
					label = "port5";
					status = "disabled";
					phandle = <0xc8>;
				};

				port@6 {
					reg = <0x06>;
					ti,mac-only;
					label = "port6";
					status = "disabled";
					phandle = <0xc9>;
				};

				port@7 {
					reg = <0x07>;
					ti,mac-only;
					label = "port7";
					status = "disabled";
					phandle = <0xca>;
				};

				port@8 {
					reg = <0x08>;
					ti,mac-only;
					label = "port8";
					status = "disabled";
					phandle = <0xcb>;
				};
			};

			mdio@f00 {
				compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
				reg = <0x00 0xf00 0x00 0x100>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clocks = <0x07 0x13 0x59>;
				clock-names = "fck";
				bus_freq = <0xf4240>;
				status = "okay";
				phandle = <0xcc>;
			};

			cpts@3d000 {
				compatible = "ti,j721e-cpts";
				reg = <0x00 0x3d000 0x00 0x400>;
				clocks = <0x07 0x13 0x10>;
				clock-names = "cpts";
				interrupts-extended = <0x01 0x00 0x10 0x04>;
				interrupt-names = "cpts";
				ti,cpts-ext-ts-inputs = <0x04>;
				ti,cpts-periodic-outputs = <0x02>;
			};
		};

		crypto@4e00000 {
			compatible = "ti,j721e-sa2ul";
			reg = <0x00 0x4e00000 0x00 0x1200>;
			power-domains = <0x08 0x108 0x01>;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges = <0x00 0x4e00000 0x00 0x4e00000 0x00 0x30000>;
			dmas = <0x10 0xc000 0x10 0x4000 0x10 0x4001>;
			dma-names = "tx\0rx1\0rx2";
			phandle = <0xcd>;

			rng@4e10000 {
				compatible = "inside-secure,safexcel-eip76";
				reg = <0x00 0x4e10000 0x00 0x7d>;
				interrupts = <0x00 0x0b 0x04>;
				phandle = <0xce>;
			};
		};

		pinctrl@11c000 {
			compatible = "pinctrl-single";
			reg = <0x00 0x11c000 0x00 0x2b4>;
			#pinctrl-cells = <0x01>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0xffffffff>;
			phandle = <0xcf>;

			main-uart0-default-pins {
				pinctrl-single,pins = <0x1f0 0x50000 0x1f4 0x10000 0x1e8 0x50000 0x1ec 0x10000>;
				phandle = <0x4c>;
			};

			main-mmc1-default-pins {
				pinctrl-single,pins = <0x254 0x50000 0x250 0x50000 0x2ac 0x50000 0x24c 0x50000 0x248 0x50000 0x244 0x50000 0x240 0x50000 0x258 0x50000 0x25c 0x50000>;
				phandle = <0x50>;
			};

			vdd-sd-dv-alt-default-pins {
				pinctrl-single,pins = <0x1c0 0x10007>;
				phandle = <0x7b>;
			};

			dp0-default-pins {
				pinctrl-single,pins = <0x1c4 0x50005>;
				phandle = <0x52>;
			};

			mcasp10-default-pins {
				pinctrl-single,pins;
				phandle = <0x57>;
			};

			main-gpio0-default-pins {
				pinctrl-single,pins = <0x10 0x07 0x28 0x50007 0x2c 0x20007 0x94 0x50007 0xa4 0x50007 0x130 0x50007 0x134 0x20007 0x16c 0x50007 0x18c 0x50007 0x190 0x50007 0x1a4 0x50007 0x1e4 0x50007>;
				phandle = <0x4e>;
			};

			main-gpio1-default-pins {
				pinctrl-single,pins = <0x238 0x50007 0x260 0x07>;
				phandle = <0x4f>;
			};

			main-mcasp1-default-pins {
				pinctrl-single,pins = <0x108 0x5000c 0x114 0x5000c 0x120 0x5000c 0x10c 0x5000d>;
				phandle = <0xd0>;
			};

			main-mmcsd1-default-pins {
				pinctrl-single,pins = <0x254 0x50000 0x250 0x50000 0x2ac 0x50000 0x24c 0x50000 0x248 0x50000 0x244 0x50000 0x240 0x50000 0x258 0x50000>;
				phandle = <0xd1>;
			};

			main-pcie3-default-pins {
				pinctrl-single,pins = <0x25c 0x50006>;
				phandle = <0xd2>;
			};

			main-spi3-default-pins {
				pinctrl-single,pins = <0x144 0x50004 0x11c 0x50004 0xd4 0x50004 0xd8 0x50004 0x124 0x50004 0x148 0x50004 0x14c 0x50004>;
				phandle = <0x76>;
			};

			main_spi5-default-pins {
				pinctrl-single,pins = <0x1a0 0x50003 0x1b4 0x50003 0x198 0x50003 0x1b0 0x50003>;
				phandle = <0x77>;
			};

			main-system0-default-pins {
				pinctrl-single,pins = <0x278 0x10000 0x280 0x50000>;
				phandle = <0xd3>;
			};

			main-uart5-default-pins {
				pinctrl-single,pins = <0x1d4 0x50003 0x1d8 0x10003>;
				phandle = <0xd4>;
			};
		};

		pinctrl@104200 {
			compatible = "pinctrl-single";
			reg = <0x00 0x104200 0x00 0x50>;
			#pinctrl-cells = <0x01>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x07>;
			phandle = <0xd5>;
		};

		pinctrl@104280 {
			compatible = "pinctrl-single";
			reg = <0x00 0x104280 0x00 0x20>;
			#pinctrl-cells = <0x01>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x1f>;
			phandle = <0xd6>;
		};

		ticsi2rx@4500000 {
			compatible = "ti,j721e-csi2rx-shim";
			reg = <0x00 0x4500000 0x00 0x1000>;
			ranges;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			dmas = <0x10 0x4940 0x10 0x4941 0x10 0x4942 0x10 0x4943 0x10 0x4944 0x10 0x4945 0x10 0x4946 0x10 0x4947 0x10 0x4948 0x10 0x4949 0x10 0x494a 0x10 0x494b 0x10 0x494c 0x10 0x494d 0x10 0x494e 0x10 0x494f>;
			dma-names = "rx0\0rx1\0rx2\0rx3\0rx4\0rx5\0rx6\0rx7\0rx8\0rx9\0rx10\0rx11\0rx12\0rx13\0rx14\0rx15";
			power-domains = <0x08 0x1a 0x01>;
			status = "disabled";
			phandle = <0xd7>;

			csi-bridge@4504000 {
				compatible = "ti,j721e-csi2rx\0cdns,csi2rx";
				reg = <0x00 0x4504000 0x00 0x1000>;
				clocks = <0x07 0x1a 0x02 0x07 0x1a 0x00 0x07 0x1a 0x02 0x07 0x1a 0x02 0x07 0x1a 0x03 0x07 0x1a 0x03>;
				clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";
				phys = <0x27>;
				phy-names = "dphy";
				phandle = <0xd8>;

				ports {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					port@0 {
						reg = <0x00>;
						status = "disabled";
						phandle = <0xd9>;
					};

					port@1 {
						reg = <0x01>;
						status = "disabled";
						phandle = <0xda>;
					};

					port@2 {
						reg = <0x02>;
						status = "disabled";
						phandle = <0xdb>;
					};

					port@3 {
						reg = <0x03>;
						status = "disabled";
						phandle = <0xdc>;
					};

					port@4 {
						reg = <0x04>;
						status = "disabled";
						phandle = <0xdd>;
					};
				};
			};
		};

		ticsi2rx@4510000 {
			compatible = "ti,j721e-csi2rx-shim";
			reg = <0x00 0x4510000 0x00 0x1000>;
			ranges;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			dmas = <0x10 0x4960 0x10 0x4961 0x10 0x4962 0x10 0x4963 0x10 0x4964 0x10 0x4965 0x10 0x4966 0x10 0x4967 0x10 0x4968 0x10 0x4969 0x10 0x496a 0x10 0x496b 0x10 0x496c 0x10 0x496d 0x10 0x496e 0x10 0x496f>;
			dma-names = "rx0\0rx1\0rx2\0rx3\0rx4\0rx5\0rx6\0rx7\0rx8\0rx9\0rx10\0rx11\0rx12\0rx13\0rx14\0rx15";
			power-domains = <0x08 0x1b 0x01>;
			status = "disabled";
			phandle = <0xde>;

			csi-bridge@4514000 {
				compatible = "ti,j721e-csi2rx\0cdns,csi2rx";
				reg = <0x00 0x4514000 0x00 0x1000>;
				clocks = <0x07 0x1b 0x02 0x07 0x1b 0x00 0x07 0x1b 0x02 0x07 0x1b 0x02 0x07 0x1b 0x03 0x07 0x1b 0x03>;
				clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";
				phys = <0x28>;
				phy-names = "dphy";
				phandle = <0xdf>;

				ports {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					port@0 {
						reg = <0x00>;
						status = "disabled";
						phandle = <0xe0>;
					};

					port@1 {
						reg = <0x01>;
						status = "disabled";
						phandle = <0xe1>;
					};

					port@2 {
						reg = <0x02>;
						status = "disabled";
						phandle = <0xe2>;
					};

					port@3 {
						reg = <0x03>;
						status = "disabled";
						phandle = <0xe3>;
					};

					port@4 {
						reg = <0x04>;
						status = "disabled";
						phandle = <0xe4>;
					};
				};
			};
		};

		phy@4580000 {
			compatible = "cdns,dphy-rx";
			reg = <0x00 0x4580000 0x00 0x1100>;
			#phy-cells = <0x00>;
			power-domains = <0x08 0x93 0x01>;
			status = "disable";
			phandle = <0x27>;
		};

		phy@4590000 {
			compatible = "cdns,dphy-rx";
			reg = <0x00 0x4590000 0x00 0x1100>;
			#phy-cells = <0x00>;
			power-domains = <0x08 0x94 0x01>;
			status = "disable";
			phandle = <0x28>;
		};

		wiz@5000000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			power-domains = <0x08 0x124 0x01>;
			clocks = <0x07 0x124 0x05 0x07 0x124 0x0b 0x29>;
			clock-names = "fck\0core_ref_clk\0ext_ref_clk";
			assigned-clocks = <0x07 0x124 0x0b 0x07 0x124 0x00>;
			assigned-clock-parents = <0x07 0x124 0x0f 0x07 0x124 0x04>;
			num-lanes = <0x02>;
			#reset-cells = <0x01>;
			ranges = <0x5000000 0x00 0x5000000 0x10000>;
			phandle = <0x2e>;

			pll0-refclk {
				clocks = <0x07 0x124 0x0b 0x29>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x2a>;
				assigned-clock-parents = <0x07 0x124 0x0b>;
				phandle = <0x2a>;
			};

			pll1-refclk {
				clocks = <0x07 0x124 0x00 0x2b>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x2c>;
				assigned-clock-parents = <0x2b>;
				phandle = <0x2c>;
			};

			refclk-dig {
				clocks = <0x07 0x124 0x0b 0x07 0x124 0x00 0x29 0x2b>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x2d>;
				assigned-clock-parents = <0x2b>;
				phandle = <0x2d>;
			};

			cmn-refclk-dig-div {
				clocks = <0x2d>;
				#clock-cells = <0x00>;
				phandle = <0x2f>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x2c>;
				#clock-cells = <0x00>;
				phandle = <0x30>;
			};

			serdes@5000000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5000000 0x10000>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				#clock-cells = <0x01>;
				resets = <0x2e 0x00>;
				reset-names = "sierra_reset";
				clocks = <0x2f 0x30 0x2a 0x2c>;
				clock-names = "cmn_refclk_dig_div\0cmn_refclk1_dig_div\0pll0_refclk\0pll1_refclk";
				assigned-clocks = <0x31 0x00>;
				assigned-clock-parents = <0x2c>;
				phandle = <0x31>;

				phy@0 {
					reg = <0x00>;
					cdns,num-lanes = <0x01>;
					#phy-cells = <0x00>;
					cdns,phy-type = <0x02>;
					resets = <0x2e 0x01>;
					phandle = <0x49>;
				};
			};
		};

		wiz@5010000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			power-domains = <0x08 0x125 0x01>;
			clocks = <0x07 0x125 0x05 0x07 0x125 0x0d 0x29>;
			clock-names = "fck\0core_ref_clk\0ext_ref_clk";
			assigned-clocks = <0x07 0x125 0x0d 0x07 0x125 0x00>;
			assigned-clock-parents = <0x07 0x125 0x11 0x07 0x125 0x04>;
			num-lanes = <0x02>;
			#reset-cells = <0x01>;
			ranges = <0x5010000 0x00 0x5010000 0x10000>;
			status = "okay";
			phandle = <0x35>;

			pll0-refclk {
				clocks = <0x07 0x125 0x0d 0x29>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x32>;
				assigned-clock-parents = <0x07 0x125 0x0d>;
				phandle = <0x32>;
			};

			pll1-refclk {
				clocks = <0x07 0x125 0x00 0x2b>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x33>;
				assigned-clock-parents = <0x2b>;
				phandle = <0x33>;
			};

			refclk-dig {
				clocks = <0x07 0x125 0x0d 0x07 0x125 0x00 0x29 0x2b>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x34>;
				assigned-clock-parents = <0x2b>;
				phandle = <0x34>;
			};

			cmn-refclk-dig-div {
				clocks = <0x34>;
				#clock-cells = <0x00>;
				phandle = <0x36>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x33>;
				#clock-cells = <0x00>;
				phandle = <0x37>;
			};

			serdes@5010000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5010000 0x10000>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				#clock-cells = <0x01>;
				resets = <0x35 0x00>;
				reset-names = "sierra_reset";
				clocks = <0x36 0x37 0x32 0x33>;
				clock-names = "cmn_refclk_dig_div\0cmn_refclk1_dig_div\0pll0_refclk\0pll1_refclk";
				status = "okay";
				assigned-clocks = <0x38 0x00>;
				assigned-clock-parents = <0x33>;
				phandle = <0x38>;

				phy@0 {
					reg = <0x00>;
					cdns,num-lanes = <0x01>;
					#phy-cells = <0x00>;
					cdns,phy-type = <0x08>;
					resets = <0x35 0x01>;
					phandle = <0x26>;
				};
			};
		};

		wiz@5020000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			power-domains = <0x08 0x126 0x01>;
			clocks = <0x07 0x126 0x05 0x07 0x126 0x0b 0x29>;
			clock-names = "fck\0core_ref_clk\0ext_ref_clk";
			assigned-clocks = <0x07 0x126 0x0b 0x07 0x126 0x00>;
			assigned-clock-parents = <0x07 0x126 0x0f 0x07 0x126 0x04>;
			num-lanes = <0x02>;
			#reset-cells = <0x01>;
			ranges = <0x5020000 0x00 0x5020000 0x10000>;
			phandle = <0x3c>;

			pll0-refclk {
				clocks = <0x07 0x126 0x0b 0x29>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x39>;
				assigned-clock-parents = <0x07 0x126 0x0b>;
				phandle = <0x39>;
			};

			pll1-refclk {
				clocks = <0x07 0x126 0x00 0x2b>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x3a>;
				assigned-clock-parents = <0x2b>;
				phandle = <0x3a>;
			};

			refclk-dig {
				clocks = <0x07 0x126 0x0b 0x07 0x126 0x00 0x29 0x2b>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x3b>;
				assigned-clock-parents = <0x2b>;
				phandle = <0x3b>;
			};

			cmn-refclk-dig-div {
				clocks = <0x3b>;
				#clock-cells = <0x00>;
				phandle = <0x3d>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x3a>;
				#clock-cells = <0x00>;
				phandle = <0x3e>;
			};

			serdes@5020000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5020000 0x10000>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				#clock-cells = <0x01>;
				resets = <0x3c 0x00>;
				reset-names = "sierra_reset";
				clocks = <0x3d 0x3e 0x39 0x3a>;
				clock-names = "cmn_refclk_dig_div\0cmn_refclk1_dig_div\0pll0_refclk\0pll1_refclk";
				assigned-clocks = <0x3f 0x00>;
				assigned-clock-parents = <0x3a>;
				phandle = <0x3f>;

				phy@0 {
					reg = <0x00>;
					cdns,num-lanes = <0x02>;
					#phy-cells = <0x00>;
					cdns,phy-type = <0x02>;
					resets = <0x3c 0x01 0x3c 0x02>;
					phandle = <0x4a>;
				};
			};
		};

		wiz@5030000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			power-domains = <0x08 0x127 0x01>;
			clocks = <0x07 0x127 0x05 0x07 0x127 0x09 0x29>;
			clock-names = "fck\0core_ref_clk\0ext_ref_clk";
			assigned-clocks = <0x07 0x127 0x09 0x07 0x127 0x00>;
			assigned-clock-parents = <0x07 0x127 0x0d 0x07 0x127 0x04>;
			num-lanes = <0x02>;
			#reset-cells = <0x01>;
			ranges = <0x5030000 0x00 0x5030000 0x10000>;
			typec-dir-gpios = <0x40 0x03 0x00>;
			typec-dir-debounce-ms = <0x2bc>;
			phandle = <0x44>;

			pll0-refclk {
				clocks = <0x07 0x127 0x09 0x29>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x41>;
				assigned-clock-parents = <0x07 0x127 0x09>;
				phandle = <0x41>;
			};

			pll1-refclk {
				clocks = <0x07 0x127 0x00 0x2b>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x42>;
				assigned-clock-parents = <0x07 0x127 0x00>;
				phandle = <0x42>;
			};

			refclk-dig {
				clocks = <0x07 0x127 0x09 0x07 0x127 0x00 0x29 0x2b>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x43>;
				assigned-clock-parents = <0x07 0x127 0x09>;
				phandle = <0x43>;
			};

			cmn-refclk-dig-div {
				clocks = <0x43>;
				#clock-cells = <0x00>;
				phandle = <0x45>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x42>;
				#clock-cells = <0x00>;
				phandle = <0x46>;
			};

			serdes@5030000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5030000 0x10000>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				#clock-cells = <0x01>;
				resets = <0x44 0x00>;
				reset-names = "sierra_reset";
				clocks = <0x45 0x46 0x41 0x42>;
				clock-names = "cmn_refclk_dig_div\0cmn_refclk1_dig_div\0pll0_refclk\0pll1_refclk";
				phandle = <0xe5>;

				phy@0 {
					reg = <0x00>;
					cdns,num-lanes = <0x02>;
					#phy-cells = <0x00>;
					cdns,phy-type = <0x04>;
					resets = <0x44 0x01 0x44 0x02>;
					phandle = <0xe6>;
				};
			};
		};

		pcie@2900000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x00 0x2900000 0x00 0x1000 0x00 0x2907000 0x00 0x400 0x00 0xd000000 0x00 0x800000 0x00 0x10000000 0x00 0x1000>;
			reg-names = "intd_cfg\0user_cfg\0reg\0cfg";
			interrupt-names = "link_state";
			interrupts = <0x00 0x13e 0x01>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x47 0x4070>;
			max-link-speed = <0x03>;
			num-lanes = <0x01>;
			power-domains = <0x08 0xef 0x01>;
			clocks = <0x07 0xef 0x01>;
			clock-names = "fck";
			#address-cells = <0x03>;
			#size-cells = <0x02>;
			bus-range = <0x00 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x00 0x48 0x00 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x00 0x10001000 0x00 0x10001000 0x00 0x10000 0x2000000 0x00 0x10011000 0x00 0x10011000 0x00 0x7fef000>;
			dma-ranges = <0x2000000 0x00 0x00 0x00 0x00 0x10000 0x00>;
			status = "okay";
			phys = <0x49>;
			phy-names = "pcie-phy";
			phandle = <0xe7>;
		};

		pcie@2910000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x00 0x2910000 0x00 0x1000 0x00 0x2917000 0x00 0x400 0x00 0xd800000 0x00 0x800000 0x00 0x18000000 0x00 0x1000>;
			reg-names = "intd_cfg\0user_cfg\0reg\0cfg";
			interrupt-names = "link_state";
			interrupts = <0x00 0x14a 0x01>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x47 0x4074>;
			max-link-speed = <0x03>;
			num-lanes = <0x02>;
			power-domains = <0x08 0xf0 0x01>;
			clocks = <0x07 0xf0 0x01>;
			clock-names = "fck";
			#address-cells = <0x03>;
			#size-cells = <0x02>;
			bus-range = <0x00 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x00 0x48 0x10000 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x00 0x18001000 0x00 0x18001000 0x00 0x10000 0x2000000 0x00 0x18011000 0x00 0x18011000 0x00 0x7fef000>;
			dma-ranges = <0x2000000 0x00 0x00 0x00 0x00 0x10000 0x00>;
			status = "okay";
			phy-names = "pcie-phy";
			phandle = <0xe8>;
		};

		pcie@2920000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x00 0x2920000 0x00 0x1000 0x00 0x2927000 0x00 0x400 0x00 0xe000000 0x00 0x800000 0x44 0x00 0x00 0x1000>;
			reg-names = "intd_cfg\0user_cfg\0reg\0cfg";
			interrupt-names = "link_state";
			interrupts = <0x00 0x156 0x01>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x47 0x4078>;
			max-link-speed = <0x03>;
			num-lanes = <0x02>;
			power-domains = <0x08 0xf1 0x01>;
			clocks = <0x07 0xf1 0x01>;
			clock-names = "fck";
			#address-cells = <0x03>;
			#size-cells = <0x02>;
			bus-range = <0x00 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x00 0x48 0x20000 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x00 0x1000 0x44 0x1000 0x00 0x10000 0x2000000 0x00 0x11000 0x44 0x11000 0x00 0x7fef000>;
			dma-ranges = <0x2000000 0x00 0x00 0x00 0x00 0x10000 0x00>;
			status = "okay";
			phys = <0x4a>;
			phy-names = "pcie-phy";
			phandle = <0xe9>;
		};

		pcie@2930000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x00 0x2930000 0x00 0x1000 0x00 0x2937000 0x00 0x400 0x00 0xe800000 0x00 0x800000 0x44 0x10000000 0x00 0x1000>;
			reg-names = "intd_cfg\0user_cfg\0reg\0cfg";
			interrupt-names = "link_state";
			interrupts = <0x00 0x162 0x01>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x47 0x407c>;
			max-link-speed = <0x03>;
			num-lanes = <0x02>;
			power-domains = <0x08 0xf2 0x01>;
			clocks = <0x07 0xf2 0x01>;
			clock-names = "fck";
			#address-cells = <0x03>;
			#size-cells = <0x02>;
			bus-range = <0x00 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x00 0x48 0x30000 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x00 0x1000 0x44 0x10001000 0x00 0x10000 0x2000000 0x00 0x11000 0x44 0x10011000 0x00 0x7fef000>;
			dma-ranges = <0x2000000 0x00 0x00 0x00 0x00 0x10000 0x00>;
			status = "disabled";
			phandle = <0xea>;
		};

		wiz@5050000 {
			status = "disabled";
			compatible = "ti,am64-wiz-10g";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			power-domains = <0x08 0x129 0x01>;
			clocks = <0x07 0x129 0x01 0x07 0x129 0x09 0x29>;
			clock-names = "fck\0core_ref_clk\0ext_ref_clk";
			assigned-clocks = <0x07 0x129 0x09>;
			assigned-clock-parents = <0x07 0x129 0x0a>;
			assigned-clock-rates = <0x124f800>;
			num-lanes = <0x04>;
			#reset-cells = <0x01>;
			#clock-cells = <0x01>;
			ranges = <0x5050000 0x00 0x5050000 0x10000 0xa030a00 0x00 0xa030a00 0x40>;
			phandle = <0x4b>;

			serdes@5050000 {
				compatible = "ti,j721e-serdes-10g";
				reg = <0x5050000 0x10000 0xa030a00 0x40>;
				reg-names = "torrent_phy\0dptx_phy";
				resets = <0x4b 0x00>;
				reset-names = "torrent_reset";
				clocks = <0x4b 0x00>;
				clock-names = "refclk";
				assigned-clocks = <0x4b 0x00 0x4b 0x01 0x4b 0x02>;
				assigned-clock-parents = <0x07 0x129 0x09 0x07 0x129 0x09 0x07 0x129 0x09>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				phandle = <0xeb>;

				phy@0 {
					reg = <0x00>;
					resets = <0x4b 0x01>;
					cdns,phy-type = <0x06>;
					cdns,num-lanes = <0x04>;
					cdns,max-bit-rate = <0xa8c>;
					#phy-cells = <0x00>;
					phandle = <0x51>;
				};
			};
		};

		timer@2400000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2400000 0x00 0x400>;
			interrupts = <0x00 0xe0 0x04>;
			clocks = <0x07 0x31 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x31 0x01>;
			assigned-clock-parents = <0x07 0x31 0x02>;
			power-domains = <0x08 0x31 0x01>;
			ti,timer-pwm;
			status = "reserved";
			phandle = <0xec>;
		};

		timer@2410000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2410000 0x00 0x400>;
			interrupts = <0x00 0xe1 0x04>;
			clocks = <0x07 0x32 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x32 0x01 0x07 0x147 0x00>;
			assigned-clock-parents = <0x07 0x32 0x02 0x07 0x147 0x01>;
			power-domains = <0x08 0x32 0x01>;
			ti,timer-pwm;
			status = "reserved";
			phandle = <0xed>;
		};

		timer@2420000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2420000 0x00 0x400>;
			interrupts = <0x00 0xe2 0x04>;
			clocks = <0x07 0x33 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x33 0x01>;
			assigned-clock-parents = <0x07 0x33 0x02>;
			power-domains = <0x08 0x33 0x01>;
			ti,timer-pwm;
			status = "reserved";
			phandle = <0xee>;
		};

		timer@2430000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2430000 0x00 0x400>;
			interrupts = <0x00 0xe3 0x04>;
			clocks = <0x07 0x34 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x34 0x01 0x07 0x148 0x00>;
			assigned-clock-parents = <0x07 0x34 0x02 0x07 0x148 0x01>;
			power-domains = <0x08 0x34 0x01>;
			ti,timer-pwm;
			phandle = <0xef>;
		};

		timer@2440000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2440000 0x00 0x400>;
			interrupts = <0x00 0xe4 0x04>;
			clocks = <0x07 0x35 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x35 0x01>;
			assigned-clock-parents = <0x07 0x35 0x02>;
			power-domains = <0x08 0x35 0x01>;
			ti,timer-pwm;
			phandle = <0xf0>;
		};

		timer@2450000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2450000 0x00 0x400>;
			interrupts = <0x00 0xe5 0x04>;
			clocks = <0x07 0x36 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x36 0x01 0x07 0x149 0x00>;
			assigned-clock-parents = <0x07 0x36 0x02 0x07 0x149 0x01>;
			power-domains = <0x08 0x36 0x01>;
			ti,timer-pwm;
			phandle = <0xf1>;
		};

		timer@2460000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2460000 0x00 0x400>;
			interrupts = <0x00 0xe6 0x04>;
			clocks = <0x07 0x37 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x37 0x01>;
			assigned-clock-parents = <0x07 0x37 0x02>;
			power-domains = <0x08 0x37 0x01>;
			ti,timer-pwm;
			phandle = <0xf2>;
		};

		timer@2470000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2470000 0x00 0x400>;
			interrupts = <0x00 0xe7 0x04>;
			clocks = <0x07 0x39 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x39 0x01 0x07 0x14a 0x00>;
			assigned-clock-parents = <0x07 0x39 0x02 0x07 0x14a 0x01>;
			power-domains = <0x08 0x39 0x01>;
			ti,timer-pwm;
			phandle = <0xf3>;
		};

		timer@2480000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2480000 0x00 0x400>;
			interrupts = <0x00 0xe8 0x04>;
			clocks = <0x07 0x3a 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x3a 0x01>;
			assigned-clock-parents = <0x07 0x3a 0x02>;
			power-domains = <0x08 0x3a 0x01>;
			ti,timer-pwm;
			phandle = <0xf4>;
		};

		timer@2490000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2490000 0x00 0x400>;
			interrupts = <0x00 0xe9 0x04>;
			clocks = <0x07 0x3b 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x3b 0x01 0x07 0x14b 0x00>;
			assigned-clock-parents = <0x07 0x3b 0x02 0x07 0x14b 0x01>;
			power-domains = <0x08 0x3b 0x01>;
			ti,timer-pwm;
			phandle = <0xf5>;
		};

		timer@24a0000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x24a0000 0x00 0x400>;
			interrupts = <0x00 0xea 0x04>;
			clocks = <0x07 0x3c 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x3c 0x01>;
			assigned-clock-parents = <0x07 0x3c 0x02>;
			power-domains = <0x08 0x3c 0x01>;
			ti,timer-pwm;
			phandle = <0xf6>;
		};

		timer@24b0000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x24b0000 0x00 0x400>;
			interrupts = <0x00 0xeb 0x04>;
			clocks = <0x07 0x3e 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x3e 0x01 0x07 0x14c 0x00>;
			assigned-clock-parents = <0x07 0x3e 0x02 0x07 0x14c 0x01>;
			power-domains = <0x08 0x3e 0x01>;
			ti,timer-pwm;
			phandle = <0xf7>;
		};

		timer@24c0000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x24c0000 0x00 0x400>;
			interrupts = <0x00 0xec 0x04>;
			clocks = <0x07 0x3f 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x3f 0x01>;
			assigned-clock-parents = <0x07 0x3f 0x02>;
			power-domains = <0x08 0x3f 0x01>;
			ti,timer-pwm;
			status = "reserved";
			phandle = <0xf8>;
		};

		timer@24d0000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x24d0000 0x00 0x400>;
			interrupts = <0x00 0xed 0x04>;
			clocks = <0x07 0x40 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x40 0x01 0x07 0x14d 0x00>;
			assigned-clock-parents = <0x07 0x40 0x02 0x07 0x14d 0x01>;
			power-domains = <0x08 0x40 0x01>;
			ti,timer-pwm;
			status = "reserved";
			phandle = <0xf9>;
		};

		timer@24e0000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x24e0000 0x00 0x400>;
			interrupts = <0x00 0xee 0x04>;
			clocks = <0x07 0x41 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x41 0x01>;
			assigned-clock-parents = <0x07 0x41 0x02>;
			power-domains = <0x08 0x41 0x01>;
			ti,timer-pwm;
			status = "reserved";
			phandle = <0xfa>;
		};

		timer@24f0000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x24f0000 0x00 0x400>;
			interrupts = <0x00 0xef 0x04>;
			clocks = <0x07 0x42 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x42 0x01 0x07 0x14e 0x00>;
			assigned-clock-parents = <0x07 0x42 0x02 0x07 0x14e 0x01>;
			power-domains = <0x08 0x42 0x01>;
			ti,timer-pwm;
			status = "reserved";
			phandle = <0xfb>;
		};

		timer@2500000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2500000 0x00 0x400>;
			interrupts = <0x00 0xf0 0x04>;
			clocks = <0x07 0x43 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x43 0x01>;
			assigned-clock-parents = <0x07 0x43 0x02>;
			power-domains = <0x08 0x43 0x01>;
			ti,timer-pwm;
			phandle = <0xfc>;
		};

		timer@2510000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2510000 0x00 0x400>;
			interrupts = <0x00 0xf1 0x04>;
			clocks = <0x07 0x44 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x44 0x01 0x07 0x14f 0x00>;
			assigned-clock-parents = <0x07 0x44 0x02 0x07 0x14f 0x01>;
			power-domains = <0x08 0x44 0x01>;
			ti,timer-pwm;
			phandle = <0xfd>;
		};

		timer@2520000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2520000 0x00 0x400>;
			interrupts = <0x00 0xf2 0x04>;
			clocks = <0x07 0x45 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x45 0x01>;
			assigned-clock-parents = <0x07 0x45 0x02>;
			power-domains = <0x08 0x45 0x01>;
			ti,timer-pwm;
			phandle = <0xfe>;
		};

		timer@2530000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2530000 0x00 0x400>;
			interrupts = <0x00 0xf3 0x04>;
			clocks = <0x07 0x46 0x01>;
			clock-names = "fck";
			assigned-clocks = <0x07 0x46 0x01 0x07 0x150 0x00>;
			assigned-clock-parents = <0x07 0x46 0x02 0x07 0x150 0x01>;
			power-domains = <0x08 0x46 0x01>;
			ti,timer-pwm;
			phandle = <0xff>;
		};

		serial@2800000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2800000 0x00 0x100>;
			interrupts = <0x00 0xc0 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x92 0x00>;
			clocks = <0x07 0x92 0x00>;
			clock-names = "fclk";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x4c>;
			phandle = <0x100>;
		};

		serial@2810000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2810000 0x00 0x100>;
			interrupts = <0x00 0xc1 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x116 0x01>;
			clocks = <0x07 0x116 0x00>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0x101>;
		};

		serial@2820000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2820000 0x00 0x100>;
			interrupts = <0x00 0xc2 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x117 0x01>;
			clocks = <0x07 0x117 0x00>;
			clock-names = "fclk";
			status = "reserved";
			phandle = <0x102>;
		};

		serial@2830000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2830000 0x00 0x100>;
			interrupts = <0x00 0xc3 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x118 0x01>;
			clocks = <0x07 0x118 0x00>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0x103>;
		};

		serial@2840000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2840000 0x00 0x100>;
			interrupts = <0x00 0xc4 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x119 0x01>;
			clocks = <0x07 0x119 0x00>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0x104>;
		};

		serial@2850000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2850000 0x00 0x100>;
			interrupts = <0x00 0xc5 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x11a 0x01>;
			clocks = <0x07 0x11a 0x00>;
			clock-names = "fclk";
			status = "okay";
			phandle = <0x105>;
		};

		serial@2860000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2860000 0x00 0x100>;
			interrupts = <0x00 0xc6 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x11b 0x01>;
			clocks = <0x07 0x11b 0x00>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0x106>;
		};

		serial@2870000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2870000 0x00 0x100>;
			interrupts = <0x00 0xc7 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x11c 0x01>;
			clocks = <0x07 0x11c 0x00>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0x107>;
		};

		serial@2880000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2880000 0x00 0x100>;
			interrupts = <0x00 0xf8 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x11d 0x01>;
			clocks = <0x07 0x11d 0x00>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0x108>;
		};

		serial@2890000 {
			compatible = "ti,j721e-uart\0ti,am654-uart";
			reg = <0x00 0x2890000 0x00 0x100>;
			interrupts = <0x00 0xf9 0x04>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x08 0x11e 0x01>;
			clocks = <0x07 0x11e 0x00>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0x109>;
		};

		gpio@600000 {
			compatible = "ti,j721e-gpio\0ti,keystone-gpio";
			reg = <0x00 0x600000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x4d>;
			interrupts = <0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x08 0x69 0x01>;
			clocks = <0x07 0x69 0x00>;
			clock-names = "gpio";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x4e>;
			phandle = <0x19>;
		};

		gpio@601000 {
			compatible = "ti,j721e-gpio\0ti,keystone-gpio";
			reg = <0x00 0x601000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x4d>;
			interrupts = <0x120 0x121 0x122>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x08 0x6a 0x01>;
			clocks = <0x07 0x6a 0x00>;
			clock-names = "gpio";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x4f>;
			phandle = <0x40>;
		};

		gpio@610000 {
			compatible = "ti,j721e-gpio\0ti,keystone-gpio";
			reg = <0x00 0x610000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x4d>;
			interrupts = <0x108 0x109 0x10a 0x10b 0x10c 0x10d 0x10e 0x10f>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x08 0x6b 0x01>;
			clocks = <0x07 0x6b 0x00>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0x10a>;
		};

		gpio@611000 {
			compatible = "ti,j721e-gpio\0ti,keystone-gpio";
			reg = <0x00 0x611000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x4d>;
			interrupts = <0x124 0x125 0x126>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x08 0x6c 0x01>;
			clocks = <0x07 0x6c 0x00>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0x10b>;
		};

		gpio@620000 {
			compatible = "ti,j721e-gpio\0ti,keystone-gpio";
			reg = <0x00 0x620000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x4d>;
			interrupts = <0x110 0x111 0x112 0x113 0x114 0x115 0x116 0x117>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x08 0x6d 0x01>;
			clocks = <0x07 0x6d 0x00>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0x10c>;
		};

		gpio@621000 {
			compatible = "ti,j721e-gpio\0ti,keystone-gpio";
			reg = <0x00 0x621000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x4d>;
			interrupts = <0x128 0x129 0x12a>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x08 0x6e 0x01>;
			clocks = <0x07 0x6e 0x00>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0x10d>;
		};

		gpio@630000 {
			compatible = "ti,j721e-gpio\0ti,keystone-gpio";
			reg = <0x00 0x630000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x4d>;
			interrupts = <0x118 0x119 0x11a 0x11b 0x11c 0x11d 0x11e 0x11f>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x08 0x6f 0x01>;
			clocks = <0x07 0x6f 0x00>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0x10e>;
		};

		gpio@631000 {
			compatible = "ti,j721e-gpio\0ti,keystone-gpio";
			reg = <0x00 0x631000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x4d>;
			interrupts = <0x12c 0x12d 0x12e>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x08 0x70 0x01>;
			clocks = <0x07 0x70 0x00>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0x10f>;
		};

		mmc@4f80000 {
			compatible = "ti,j721e-sdhci-8bit";
			reg = <0x00 0x4f80000 0x00 0x1000 0x00 0x4f88000 0x00 0x400>;
			interrupts = <0x00 0x03 0x04>;
			power-domains = <0x08 0x5b 0x01>;
			clock-names = "clk_ahb\0clk_xin";
			clocks = <0x07 0x5b 0x00 0x07 0x5b 0x01>;
			assigned-clocks = <0x07 0x5b 0x01>;
			assigned-clock-parents = <0x07 0x5b 0x02>;
			bus-width = <0x08>;
			mmc-hs200-1_8v;
			mmc-ddr-1_8v;
			ti,otap-del-sel-legacy = <0x00>;
			ti,otap-del-sel-mmc-hs = <0x00>;
			ti,otap-del-sel-ddr52 = <0x05>;
			ti,otap-del-sel-hs200 = <0x06>;
			ti,otap-del-sel-hs400 = <0x00>;
			ti,itap-del-sel-legacy = <0x10>;
			ti,itap-del-sel-mmc-hs = <0x0a>;
			ti,itap-del-sel-ddr52 = <0x03>;
			ti,trm-icp = <0x08>;
			dma-coherent;
			status = "okay";
			non-removable;
			ti,driver-strength-ohm = <0x32>;
			disable-wp;
			phandle = <0x110>;
		};

		mmc@4fb0000 {
			compatible = "ti,j721e-sdhci-4bit";
			reg = <0x00 0x4fb0000 0x00 0x1000 0x00 0x4fb8000 0x00 0x400>;
			interrupts = <0x00 0x04 0x04>;
			power-domains = <0x08 0x5c 0x01>;
			clock-names = "clk_ahb\0clk_xin";
			clocks = <0x07 0x5c 0x05 0x07 0x5c 0x00>;
			assigned-clocks = <0x07 0x5c 0x00>;
			assigned-clock-parents = <0x07 0x5c 0x01>;
			ti,otap-del-sel-legacy = <0x00>;
			ti,otap-del-sel-sd-hs = <0x00>;
			ti,otap-del-sel-sdr12 = <0x0f>;
			ti,otap-del-sel-sdr25 = <0x0f>;
			ti,otap-del-sel-sdr50 = <0x0c>;
			ti,otap-del-sel-ddr50 = <0x0c>;
			ti,otap-del-sel-sdr104 = <0x05>;
			ti,itap-del-sel-legacy = <0x00>;
			ti,itap-del-sel-sd-hs = <0x00>;
			ti,itap-del-sel-sdr12 = <0x00>;
			ti,itap-del-sel-sdr25 = <0x00>;
			ti,itap-del-sel-ddr50 = <0x02>;
			ti,trm-icp = <0x08>;
			ti,clkbuf-sel = <0x07>;
			dma-coherent;
			sdhci-caps-mask = <0x8000000f 0x00>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x50>;
			ti,driver-strength-ohm = <0x32>;
			disable-wp;
			no-1-8-v;
			phandle = <0x111>;
		};

		mmc@4f98000 {
			compatible = "ti,j721e-sdhci-4bit";
			reg = <0x00 0x4f98000 0x00 0x1000 0x00 0x4f90000 0x00 0x400>;
			interrupts = <0x00 0x05 0x04>;
			power-domains = <0x08 0x5d 0x01>;
			clock-names = "clk_ahb\0clk_xin";
			clocks = <0x07 0x5d 0x05 0x07 0x5d 0x00>;
			assigned-clocks = <0x07 0x5d 0x00>;
			assigned-clock-parents = <0x07 0x5d 0x01>;
			ti,otap-del-sel-legacy = <0x00>;
			ti,otap-del-sel-sd-hs = <0x00>;
			ti,otap-del-sel-sdr12 = <0x0f>;
			ti,otap-del-sel-sdr25 = <0x0f>;
			ti,otap-del-sel-sdr50 = <0x0c>;
			ti,otap-del-sel-ddr50 = <0x0c>;
			ti,otap-del-sel-sdr104 = <0x05>;
			ti,itap-del-sel-legacy = <0x00>;
			ti,itap-del-sel-sd-hs = <0x00>;
			ti,itap-del-sel-sdr12 = <0x00>;
			ti,itap-del-sel-sdr25 = <0x00>;
			ti,itap-del-sel-ddr50 = <0x02>;
			ti,trm-icp = <0x08>;
			ti,clkbuf-sel = <0x07>;
			dma-coherent;
			sdhci-caps-mask = <0x02 0x00>;
			status = "disabled";
			phandle = <0x112>;
		};

		cdns-usb@4104000 {
			compatible = "ti,j721e-usb";
			reg = <0x00 0x4104000 0x00 0x100>;
			dma-coherent;
			power-domains = <0x08 0x120 0x01>;
			clocks = <0x07 0x120 0x0f 0x07 0x120 0x03>;
			clock-names = "ref\0lpm";
			assigned-clocks = <0x07 0x120 0x0f>;
			assigned-clock-parents = <0x07 0x120 0x10>;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges;
			phandle = <0x113>;

			usb@6000000 {
				compatible = "cdns,usb3";
				reg = <0x00 0x6000000 0x00 0x10000 0x00 0x6010000 0x00 0x10000 0x00 0x6020000 0x00 0x10000>;
				reg-names = "otg\0xhci\0dev";
				interrupts = <0x00 0x60 0x04 0x00 0x66 0x04 0x00 0x78 0x04>;
				interrupt-names = "host\0peripheral\0otg";
				maximum-speed = "super-speed";
				dr_mode = "otg";
				phandle = <0x114>;
			};
		};

		cdns-usb@4114000 {
			compatible = "ti,j721e-usb";
			reg = <0x00 0x4114000 0x00 0x100>;
			dma-coherent;
			power-domains = <0x08 0x121 0x01>;
			clocks = <0x07 0x121 0x0f 0x07 0x121 0x03>;
			clock-names = "ref\0lpm";
			assigned-clocks = <0x07 0x121 0x0f>;
			assigned-clock-parents = <0x07 0x121 0x10>;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges;
			phandle = <0x115>;

			usb@6400000 {
				compatible = "cdns,usb3";
				reg = <0x00 0x6400000 0x00 0x10000 0x00 0x6410000 0x00 0x10000 0x00 0x6420000 0x00 0x10000>;
				reg-names = "otg\0xhci\0dev";
				interrupts = <0x00 0x68 0x04 0x00 0x6e 0x04 0x00 0x79 0x04>;
				interrupt-names = "host\0peripheral\0otg";
				maximum-speed = "super-speed";
				dr_mode = "otg";
				phandle = <0x116>;
			};
		};

		i2c@2000000 {
			compatible = "ti,j721e-i2c\0ti,omap4-i2c";
			reg = <0x00 0x2000000 0x00 0x100>;
			interrupts = <0x00 0xc8 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			clock-names = "fck";
			clocks = <0x07 0xbb 0x00>;
			power-domains = <0x08 0xbb 0x00>;
			status = "disabled";
			phandle = <0x117>;
		};

		i2c@2010000 {
			compatible = "ti,j721e-i2c\0ti,omap4-i2c";
			reg = <0x00 0x2010000 0x00 0x100>;
			interrupts = <0x00 0xc9 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			clock-names = "fck";
			clocks = <0x07 0xbc 0x00>;
			power-domains = <0x08 0xbc 0x01>;
			status = "disabled";
			phandle = <0x118>;
		};

		i2c@2020000 {
			compatible = "ti,j721e-i2c\0ti,omap4-i2c";
			reg = <0x00 0x2020000 0x00 0x100>;
			interrupts = <0x00 0xca 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			clock-names = "fck";
			clocks = <0x07 0xbd 0x00>;
			power-domains = <0x08 0xbd 0x01>;
			status = "disabled";
			phandle = <0x119>;
		};

		i2c@2030000 {
			compatible = "ti,j721e-i2c\0ti,omap4-i2c";
			reg = <0x00 0x2030000 0x00 0x100>;
			interrupts = <0x00 0xcb 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			clock-names = "fck";
			clocks = <0x07 0xbe 0x00>;
			power-domains = <0x08 0xbe 0x01>;
			status = "disabled";
			phandle = <0x11a>;
		};

		i2c@2040000 {
			compatible = "ti,j721e-i2c\0ti,omap4-i2c";
			reg = <0x00 0x2040000 0x00 0x100>;
			interrupts = <0x00 0xcc 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			clock-names = "fck";
			clocks = <0x07 0xbf 0x00>;
			power-domains = <0x08 0xbf 0x01>;
			status = "disabled";
			phandle = <0x11b>;
		};

		i2c@2050000 {
			compatible = "ti,j721e-i2c\0ti,omap4-i2c";
			reg = <0x00 0x2050000 0x00 0x100>;
			interrupts = <0x00 0xcd 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			clock-names = "fck";
			clocks = <0x07 0xc0 0x00>;
			power-domains = <0x08 0xc0 0x01>;
			status = "disabled";
			phandle = <0x11c>;
		};

		i2c@2060000 {
			compatible = "ti,j721e-i2c\0ti,omap4-i2c";
			reg = <0x00 0x2060000 0x00 0x100>;
			interrupts = <0x00 0xce 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			clock-names = "fck";
			clocks = <0x07 0xc1 0x00>;
			power-domains = <0x08 0xc1 0x01>;
			status = "disabled";
			phandle = <0x11d>;
		};

		video-encoder@4200000 {
			compatible = "img,vxe384";
			reg = <0x00 0x4200000 0x00 0x100000>;
			power-domains = <0x08 0x99 0x01>;
			interrupts = <0x00 0xb5 0x04>;
			phandle = <0x11e>;
		};

		video-decoder@4300000 {
			compatible = "img,d5500-vxd";
			reg = <0x00 0x4300000 0x00 0x100000>;
			power-domains = <0x08 0x90 0x01>;
			interrupts = <0x00 0xb4 0x04>;
			phandle = <0x11f>;
		};

		ufs-wrapper@4e80000 {
			compatible = "ti,j721e-ufs";
			reg = <0x00 0x4e80000 0x00 0x100>;
			power-domains = <0x08 0x115 0x01>;
			clocks = <0x07 0x115 0x01>;
			assigned-clocks = <0x07 0x115 0x01>;
			assigned-clock-parents = <0x07 0x115 0x04>;
			ranges;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			status = "okay";
			phandle = <0x120>;

			ufs@4e84000 {
				compatible = "cdns,ufshc-m31-16nm\0jedec,ufs-2.0";
				reg = <0x00 0x4e84000 0x00 0x10000>;
				interrupts = <0x00 0x11 0x04>;
				freq-table-hz = <0x18cba80 0x18cba80 0x124f800 0x124f800 0x124f800 0x124f800>;
				clocks = <0x07 0x115 0x00 0x07 0x115 0x01 0x07 0x115 0x01>;
				clock-names = "core_clk\0phy_clk\0ref_clk";
				dma-coherent;
				status = "okay";
			};
		};

		dp-bridge@a000000 {
			compatible = "ti,j721e-mhdp8546";
			reg = <0x00 0xa000000 0x00 0x30a00 0x00 0x4f40000 0x00 0x20>;
			reg-names = "mhdptx\0j721e-intg";
			clocks = <0x07 0x97 0x24>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x266 0x04>;
			power-domains = <0x08 0x97 0x01>;
			phys = <0x51>;
			phy-names = "dpphy";
			pinctrl-names = "default";
			pinctrl-0 = <0x52>;
			status = "disabled";
			phandle = <0x121>;

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				phandle = <0x122>;

				port@0 {
					reg = <0x00>;

					endpoint {
						remote-endpoint = <0x53>;
						phandle = <0x56>;
					};
				};

				port@4 {
					reg = <0x04>;

					endpoint {
						remote-endpoint = <0x54>;
						phandle = <0x7d>;
					};
				};
			};
		};

		dsi@48000000 {
			compatible = "ti,j721e-dsi";
			reg = <0x00 0x4800000 0x00 0x100000 0x00 0x4710000 0x00 0x100>;
			clocks = <0x07 0x96 0x01 0x07 0x96 0x05>;
			clock-names = "dsi_p_clk\0dsi_sys_clk";
			power-domains = <0x08 0x96 0x01>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x258 0x04>;
			phys = <0x55>;
			phy-names = "dphy";
			status = "disabled";
			phandle = <0x123>;

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				phandle = <0x124>;
			};
		};

		dss@4a00000 {
			status = "disabled";
			compatible = "ti,j721e-dss";
			reg = <0x00 0x4a00000 0x00 0x10000 0x00 0x4a10000 0x00 0x10000 0x00 0x4b00000 0x00 0x10000 0x00 0x4b10000 0x00 0x10000 0x00 0x4a20000 0x00 0x10000 0x00 0x4a30000 0x00 0x10000 0x00 0x4a50000 0x00 0x10000 0x00 0x4a60000 0x00 0x10000 0x00 0x4a70000 0x00 0x10000 0x00 0x4a90000 0x00 0x10000 0x00 0x4ab0000 0x00 0x10000 0x00 0x4ad0000 0x00 0x10000 0x00 0x4a80000 0x00 0x10000 0x00 0x4aa0000 0x00 0x10000 0x00 0x4ac0000 0x00 0x10000 0x00 0x4ae0000 0x00 0x10000 0x00 0x4af0000 0x00 0x10000>;
			reg-names = "common_m\0common_s0\0common_s1\0common_s2\0vidl1\0vidl2\0vid1\0vid2\0ovr1\0ovr2\0ovr3\0ovr4\0vp1\0vp2\0vp3\0vp4\0wb";
			clocks = <0x07 0x98 0x00 0x07 0x98 0x01 0x07 0x98 0x04 0x07 0x98 0x09 0x07 0x98 0x0d>;
			clock-names = "fck\0vp1\0vp2\0vp3\0vp4";
			power-domains = <0x08 0x98 0x01>;
			interrupts = <0x00 0x25a 0x04 0x00 0x25b 0x04 0x00 0x25c 0x04 0x00 0x25d 0x04>;
			interrupt-names = "common_m\0common_s0\0common_s1\0common_s2";
			assigned-clocks = <0x07 0x98 0x01 0x07 0x98 0x04 0x07 0x98 0x09 0x07 0x98 0x0d>;
			assigned-clock-parents = <0x07 0x98 0x02 0x07 0x98 0x06 0x07 0x98 0x0b 0x07 0x98 0x12>;
			phandle = <0x125>;

			ports {
				phandle = <0x126>;

				port {

					endpoint {
						remote-endpoint = <0x56>;
						phandle = <0x53>;
					};
				};
			};
		};

		mcasp@2b00000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b00000 0x00 0x2000 0x00 0x2b08000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x220 0x04 0x00 0x221 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc400 0x10 0x4400>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xae 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xae 0x01>;
			status = "disabled";
			phandle = <0x127>;
		};

		mcasp@2b10000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b10000 0x00 0x2000 0x00 0x2b18000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x222 0x04 0x00 0x223 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc401 0x10 0x4401>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xaf 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xaf 0x01>;
			status = "disabled";
			phandle = <0x128>;
		};

		mcasp@2b20000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b20000 0x00 0x2000 0x00 0x2b28000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x224 0x04 0x00 0x225 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc402 0x10 0x4402>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb0 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb0 0x01>;
			status = "disabled";
			phandle = <0x129>;
		};

		mcasp@2b30000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b30000 0x00 0x2000 0x00 0x2b38000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x226 0x04 0x00 0x227 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc500 0x10 0x4500>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb1 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb1 0x01>;
			status = "disabled";
			phandle = <0x12a>;
		};

		mcasp@2b40000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b40000 0x00 0x2000 0x00 0x2b48000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x228 0x04 0x00 0x229 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc501 0x10 0x4501>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb2 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb2 0x01>;
			status = "disabled";
			phandle = <0x12b>;
		};

		mcasp@2b50000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b50000 0x00 0x2000 0x00 0x2b58000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x22a 0x04 0x00 0x22b 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc502 0x10 0x4502>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb3 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb3 0x01>;
			status = "disabled";
			phandle = <0x12c>;
		};

		mcasp@2b60000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b60000 0x00 0x2000 0x00 0x2b68000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x22c 0x04 0x00 0x22d 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc503 0x10 0x4503>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb4 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb4 0x01>;
			status = "disabled";
			phandle = <0x12d>;
		};

		mcasp@2b70000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b70000 0x00 0x2000 0x00 0x2b78000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x22e 0x04 0x00 0x22f 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc504 0x10 0x4504>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb5 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb5 0x01>;
			status = "disabled";
			phandle = <0x12e>;
		};

		mcasp@2b80000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b80000 0x00 0x2000 0x00 0x2b88000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x230 0x04 0x00 0x231 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc505 0x10 0x4505>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb6 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb6 0x01>;
			status = "disabled";
			phandle = <0x12f>;
		};

		mcasp@2b90000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b90000 0x00 0x2000 0x00 0x2b98000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x232 0x04 0x00 0x233 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc506 0x10 0x4506>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb7 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb7 0x01>;
			status = "disabled";
			phandle = <0x130>;
		};

		mcasp@2ba0000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2ba0000 0x00 0x2000 0x00 0x2ba8000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x234 0x04 0x00 0x235 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc507 0x10 0x4507>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb8 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb8 0x01>;
			status = "okay";
			#sound-dai-cells = <0x00>;
			pinctrl-names = "default";
			pinctrl-0 = <0x57>;
			op-mode = <0x00>;
			tdm-slots = <0x02>;
			auxclk-fs-ratio = <0x100>;
			serial-dir = <0x01 0x01 0x01 0x01 0x02 0x02 0x02 0x00>;
			tx-num-evt = <0x00>;
			rx-num-evt = <0x00>;
			phandle = <0x131>;
		};

		mcasp@2bb0000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2bb0000 0x00 0x2000 0x00 0x2bb8000 0x00 0x1000>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0x236 0x04 0x00 0x237 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x10 0xc508 0x10 0x4508>;
			dma-names = "tx\0rx";
			clocks = <0x07 0xb9 0x01>;
			clock-names = "fck";
			power-domains = <0x08 0xb9 0x01>;
			status = "disabled";
			phandle = <0x132>;
		};

		watchdog@2200000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x00 0x2200000 0x00 0x100>;
			clocks = <0x07 0xfc 0x01>;
			power-domains = <0x08 0xfc 0x01>;
			assigned-clocks = <0x07 0xfc 0x01>;
			assigned-clock-parents = <0x07 0xfc 0x05>;
			phandle = <0x133>;
		};

		watchdog@2210000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x00 0x2210000 0x00 0x100>;
			clocks = <0x07 0xfd 0x01>;
			power-domains = <0x08 0xfd 0x01>;
			assigned-clocks = <0x07 0xfd 0x01>;
			assigned-clock-parents = <0x07 0xfd 0x05>;
			phandle = <0x134>;
		};

		r5fss@5c00000 {
			compatible = "ti,j721e-r5fss";
			ti,cluster-mode = <0x00>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x5c00000 0x00 0x5c00000 0x20000 0x5d00000 0x00 0x5d00000 0x20000>;
			power-domains = <0x08 0xf3 0x01>;
			phandle = <0x135>;

			r5f@5c00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5c00000 0x8000 0x5c10000 0x8000>;
				reg-names = "atcm\0btcm";
				ti,sci = <0x09>;
				ti,sci-dev-id = <0xf5>;
				ti,sci-proc-ids = <0x06 0xff>;
				resets = <0x1a 0xf5 0x01>;
				firmware-name = "j7-main-r5f0_0-fw";
				ti,atcm-enable = <0x01>;
				ti,btcm-enable = <0x01>;
				ti,loczrama = <0x01>;
				mboxes = <0x58 0x59>;
				memory-region = <0x189 0x18a 0x18b 0x18c>;
				phandle = <0x136>;
			};

			r5f@5d00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5d00000 0x8000 0x5d10000 0x8000>;
				reg-names = "atcm\0btcm";
				ti,sci = <0x09>;
				ti,sci-dev-id = <0xf6>;
				ti,sci-proc-ids = <0x07 0xff>;
				resets = <0x1a 0xf6 0x01>;
				firmware-name = "j7-main-r5f0_1-fw";
				ti,atcm-enable = <0x01>;
				ti,btcm-enable = <0x01>;
				ti,loczrama = <0x01>;
				mboxes = <0x58 0x5c>;
				memory-region = <0x18d 0x18e>;
				phandle = <0x137>;
			};
		};

		r5fss@5e00000 {
			compatible = "ti,j721e-r5fss";
			ti,cluster-mode = <0x00>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x5e00000 0x00 0x5e00000 0x20000 0x5f00000 0x00 0x5f00000 0x20000>;
			power-domains = <0x08 0xf4 0x01>;
			phandle = <0x138>;

			r5f@5e00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5e00000 0x8000 0x5e10000 0x8000>;
				reg-names = "atcm\0btcm";
				ti,sci = <0x09>;
				ti,sci-dev-id = <0xf7>;
				ti,sci-proc-ids = <0x08 0xff>;
				resets = <0x1a 0xf7 0x01>;
				firmware-name = "j7-main-r5f1_0-fw";
				ti,atcm-enable = <0x01>;
				ti,btcm-enable = <0x01>;
				ti,loczrama = <0x01>;
				mboxes = <0x5f 0x60>;
				memory-region = <0x18f 0x190>;
				phandle = <0x139>;
			};

			r5f@5f00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5f00000 0x8000 0x5f10000 0x8000>;
				reg-names = "atcm\0btcm";
				ti,sci = <0x09>;
				ti,sci-dev-id = <0xf8>;
				ti,sci-proc-ids = <0x09 0xff>;
				resets = <0x1a 0xf8 0x01>;
				firmware-name = "j7-main-r5f1_1-fw";
				ti,atcm-enable = <0x01>;
				ti,btcm-enable = <0x01>;
				ti,loczrama = <0x01>;
				mboxes = <0x5f 0x63>;
				memory-region = <0x191 0x192>;
				phandle = <0x13a>;
			};
		};

		dsp@4d80800000 {
			compatible = "ti,j721e-c66-dsp";
			reg = <0x4d 0x80800000 0x00 0x48000 0x4d 0x80e00000 0x00 0x8000 0x4d 0x80f00000 0x00 0x8000>;
			reg-names = "l2sram\0l1pram\0l1dram";
			ti,sci = <0x09>;
			ti,sci-dev-id = <0x8e>;
			ti,sci-proc-ids = <0x03 0xff>;
			resets = <0x1a 0x8e 0x01>;
			firmware-name = "j7-c66_0-fw";
			status = "okay";
			mboxes = <0x66 0x67>;
			memory-region = <0x193 0x194>;
			phandle = <0x13b>;
		};

		dsp@4d81800000 {
			compatible = "ti,j721e-c66-dsp";
			reg = <0x4d 0x81800000 0x00 0x48000 0x4d 0x81e00000 0x00 0x8000 0x4d 0x81f00000 0x00 0x8000>;
			reg-names = "l2sram\0l1pram\0l1dram";
			ti,sci = <0x09>;
			ti,sci-dev-id = <0x8f>;
			ti,sci-proc-ids = <0x04 0xff>;
			resets = <0x1a 0x8f 0x01>;
			firmware-name = "j7-c66_1-fw";
			status = "okay";
			mboxes = <0x66 0x6a>;
			memory-region = <0x195 0x196>;
			phandle = <0x13c>;
		};

		dsp@64800000 {
			compatible = "ti,j721e-c71-dsp";
			reg = <0x00 0x64800000 0x00 0x80000 0x00 0x64e00000 0x00 0xc000>;
			reg-names = "l2sram\0l1dram";
			ti,sci = <0x09>;
			ti,sci-dev-id = <0x0f>;
			ti,sci-proc-ids = <0x30 0xff>;
			resets = <0x1a 0x0f 0x01>;
			firmware-name = "j7-c71_0-fw";
			status = "okay";
			mboxes = <0x6d 0x6e>;
			memory-region = <0x197 0x198>;
			phandle = <0x13d>;
		};

		pinctrl@a40000 {
			compatible = "pinctrl-single";
			reg = <0x00 0xa40000 0x00 0x800>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			#pinctrl-cells = <0x01>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x107ff>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x71>;
			phandle = <0x13e>;

			mcu-cpsw-cpts {
				pinctrl-single,pins = <0x68 0x10011>;
				phandle = <0x71>;
			};
		};

		icssg@b000000 {
			compatible = "ti,j721e-icssg";
			reg = <0x00 0xb000000 0x00 0x80000>;
			power-domains = <0x08 0x77 0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x00 0xb000000 0x100000>;
			phandle = <0x13f>;

			memories@0 {
				reg = <0x00 0x2000 0x2000 0x2000 0x10000 0x10000>;
				reg-names = "dram0\0dram1\0shrdram2";
				phandle = <0x140>;
			};

			cfg@26000 {
				compatible = "ti,pruss-cfg\0syscon";
				reg = <0x26000 0x200>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x26000 0x2000>;
				phandle = <0x141>;

				clocks {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					coreclk-mux@3c {
						reg = <0x3c>;
						#clock-cells = <0x00>;
						clocks = <0x07 0x77 0x18 0x07 0x77 0x01>;
						assigned-clocks = <0x72>;
						assigned-clock-parents = <0x07 0x77 0x01>;
						phandle = <0x72>;
					};

					iepclk-mux@30 {
						reg = <0x30>;
						#clock-cells = <0x00>;
						clocks = <0x07 0x77 0x03 0x72>;
						assigned-clocks = <0x73>;
						assigned-clock-parents = <0x72>;
						phandle = <0x73>;
					};
				};
			};

			mii-rt@32000 {
				compatible = "ti,pruss-mii\0syscon";
				reg = <0x32000 0x100>;
				phandle = <0x142>;
			};

			mii-g-rt@33000 {
				compatible = "ti,pruss-mii-g\0syscon";
				reg = <0x33000 0x1000>;
				phandle = <0x143>;
			};

			interrupt-controller@20000 {
				compatible = "ti,icssg-intc";
				reg = <0x20000 0x2000>;
				interrupt-controller;
				#interrupt-cells = <0x03>;
				interrupts = <0x00 0xfe 0x04 0x00 0xff 0x04 0x00 0x100 0x04 0x00 0x101 0x04 0x00 0x102 0x04 0x00 0x103 0x04 0x00 0x104 0x04 0x00 0x105 0x04>;
				interrupt-names = "host_intr0\0host_intr1\0host_intr2\0host_intr3\0host_intr4\0host_intr5\0host_intr6\0host_intr7";
				phandle = <0x144>;
			};

			pru@34000 {
				compatible = "ti,j721e-pru";
				reg = <0x34000 0x3000 0x22000 0x100 0x22400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-pru0_0-fw";
				phandle = <0x145>;
			};

			rtu@4000 {
				compatible = "ti,j721e-rtu";
				reg = <0x4000 0x2000 0x23000 0x100 0x23400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-rtu0_0-fw";
				phandle = <0x146>;
			};

			txpru@a000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xa000 0x1800 0x25000 0x100 0x25400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-txpru0_0-fw";
				phandle = <0x147>;
			};

			pru@38000 {
				compatible = "ti,j721e-pru";
				reg = <0x38000 0x3000 0x24000 0x100 0x24400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-pru0_1-fw";
				phandle = <0x148>;
			};

			rtu@6000 {
				compatible = "ti,j721e-rtu";
				reg = <0x6000 0x2000 0x23800 0x100 0x23c00 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-rtu0_1-fw";
				phandle = <0x149>;
			};

			txpru@c000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xc000 0x1800 0x25800 0x100 0x25c00 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-txpru0_1-fw";
				phandle = <0x14a>;
			};

			mdio@32400 {
				compatible = "ti,davinci_mdio";
				reg = <0x32400 0x100>;
				clocks = <0x07 0x77 0x01>;
				clock-names = "fck";
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				bus_freq = <0xf4240>;
				status = "disabled";
				phandle = <0x14b>;
			};
		};

		icssg@b100000 {
			compatible = "ti,j721e-icssg";
			reg = <0x00 0xb100000 0x00 0x80000>;
			power-domains = <0x08 0x78 0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x00 0xb100000 0x100000>;
			phandle = <0x14c>;

			memories@b100000 {
				reg = <0x00 0x2000 0x2000 0x2000 0x10000 0x10000>;
				reg-names = "dram0\0dram1\0shrdram2";
				phandle = <0x14d>;
			};

			cfg@26000 {
				compatible = "ti,pruss-cfg\0syscon";
				reg = <0x26000 0x200>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x26000 0x2000>;
				phandle = <0x14e>;

				clocks {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					coreclk-mux@3c {
						reg = <0x3c>;
						#clock-cells = <0x00>;
						clocks = <0x07 0x78 0x36 0x07 0x78 0x04>;
						assigned-clocks = <0x74>;
						assigned-clock-parents = <0x07 0x78 0x04>;
						phandle = <0x74>;
					};

					iepclk-mux@30 {
						reg = <0x30>;
						#clock-cells = <0x00>;
						clocks = <0x07 0x78 0x09 0x74>;
						assigned-clocks = <0x75>;
						assigned-clock-parents = <0x74>;
						phandle = <0x75>;
					};
				};
			};

			mii-rt@32000 {
				compatible = "ti,pruss-mii\0syscon";
				reg = <0x32000 0x100>;
				phandle = <0x14f>;
			};

			mii-g-rt@33000 {
				compatible = "ti,pruss-mii-g\0syscon";
				reg = <0x33000 0x1000>;
				phandle = <0x150>;
			};

			interrupt-controller@20000 {
				compatible = "ti,icssg-intc";
				reg = <0x20000 0x2000>;
				interrupt-controller;
				#interrupt-cells = <0x03>;
				interrupts = <0x00 0x106 0x04 0x00 0x107 0x04 0x00 0x108 0x04 0x00 0x109 0x04 0x00 0x10a 0x04 0x00 0x10b 0x04 0x00 0x10c 0x04 0x00 0x10d 0x04>;
				interrupt-names = "host_intr0\0host_intr1\0host_intr2\0host_intr3\0host_intr4\0host_intr5\0host_intr6\0host_intr7";
				phandle = <0x151>;
			};

			pru@34000 {
				compatible = "ti,j721e-pru";
				reg = <0x34000 0x4000 0x22000 0x100 0x22400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-pru1_0-fw";
				phandle = <0x152>;
			};

			rtu@4000 {
				compatible = "ti,j721e-rtu";
				reg = <0x4000 0x2000 0x23000 0x100 0x23400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-rtu1_0-fw";
				phandle = <0x153>;
			};

			txpru@a000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xa000 0x1800 0x25000 0x100 0x25400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-txpru1_0-fw";
				phandle = <0x154>;
			};

			pru@38000 {
				compatible = "ti,j721e-pru";
				reg = <0x38000 0x4000 0x24000 0x100 0x24400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-pru1_1-fw";
				phandle = <0x155>;
			};

			rtu@6000 {
				compatible = "ti,j721e-rtu";
				reg = <0x6000 0x2000 0x23800 0x100 0x23c00 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-rtu1_1-fw";
				phandle = <0x156>;
			};

			txpru@c000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xc000 0x1800 0x25800 0x100 0x25c00 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "j7-txpru1_1-fw";
				phandle = <0x157>;
			};

			mdio@32400 {
				compatible = "ti,davinci_mdio";
				reg = <0x32400 0x100>;
				clocks = <0x07 0x78 0x04>;
				clock-names = "fck";
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				bus_freq = <0xf4240>;
				status = "disabled";
				phandle = <0x158>;
			};
		};

		gpu@4e20000000 {
			compatible = "ti,j721e-pvr\0img,pvr-ge8430";
			reg = <0x4e 0x20000000 0x00 0x80000>;
			interrupts = <0x00 0x18 0x04>;
			power-domains = <0x08 0x7d 0x01 0x08 0x7e 0x01>;
			power-domain-names = "firmware\0dust";
			clocks = <0x07 0x7d 0x00>;
			assigned-clocks = <0x07 0x7d 0x00>;
			assigned-clock-rates = <0x2cb41780>;
			clock-names = "core";
			phandle = <0x159>;
		};

		can@2701000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2701000 0x00 0x200 0x00 0x2708000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0x9c 0x01>;
			clocks = <0x07 0x9c 0x00 0x07 0x9c 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x7c 0x04 0x00 0x7d 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x15a>;
		};

		can@2711000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2711000 0x00 0x200 0x00 0x2718000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0x9e 0x01>;
			clocks = <0x07 0x9e 0x00 0x07 0x9e 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x7f 0x04 0x00 0x80 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x15b>;
		};

		can@2721000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2721000 0x00 0x200 0x00 0x2728000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa0 0x01>;
			clocks = <0x07 0xa0 0x00 0x07 0xa0 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x82 0x04 0x00 0x83 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x15c>;
		};

		can@2731000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2731000 0x00 0x200 0x00 0x2738000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa1 0x01>;
			clocks = <0x07 0xa1 0x00 0x07 0xa1 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x85 0x04 0x00 0x86 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x15d>;
		};

		can@2741000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2741000 0x00 0x200 0x00 0x2748000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa2 0x01>;
			clocks = <0x07 0xa2 0x00 0x07 0xa2 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x88 0x04 0x00 0x89 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x15e>;
		};

		can@2751000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2751000 0x00 0x200 0x00 0x2758000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa3 0x01>;
			clocks = <0x07 0xa3 0x00 0x07 0xa3 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x8b 0x04 0x00 0x8c 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x15f>;
		};

		can@2761000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2761000 0x00 0x200 0x00 0x2768000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa4 0x01>;
			clocks = <0x07 0xa4 0x00 0x07 0xa4 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x8e 0x04 0x00 0x8f 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x160>;
		};

		can@2771000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2771000 0x00 0x200 0x00 0x2778000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa5 0x01>;
			clocks = <0x07 0xa5 0x00 0x07 0xa5 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x91 0x04 0x00 0x92 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x161>;
		};

		can@2781000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2781000 0x00 0x200 0x00 0x2788000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa6 0x01>;
			clocks = <0x07 0xa6 0x00 0x07 0xa6 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x240 0x04 0x00 0x241 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x162>;
		};

		can@2791000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x2791000 0x00 0x200 0x00 0x2798000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa7 0x01>;
			clocks = <0x07 0xa7 0x00 0x07 0xa7 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x243 0x04 0x00 0x244 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x163>;
		};

		can@27a1000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x27a1000 0x00 0x200 0x00 0x27a8000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa8 0x01>;
			clocks = <0x07 0xa8 0x00 0x07 0xa8 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x246 0x04 0x00 0x247 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x164>;
		};

		can@27b1000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x27b1000 0x00 0x200 0x00 0x27b8000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xa9 0x01>;
			clocks = <0x07 0xa9 0x00 0x07 0xa9 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x249 0x04 0x00 0x24a 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x165>;
		};

		can@27c1000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x27c1000 0x00 0x200 0x00 0x27c8000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xaa 0x01>;
			clocks = <0x07 0xaa 0x00 0x07 0xaa 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x24c 0x04 0x00 0x24d 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x166>;
		};

		can@27d1000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x27d1000 0x00 0x200 0x00 0x27d8000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x08 0xab 0x01>;
			clocks = <0x07 0xab 0x00 0x07 0xab 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x24f 0x04 0x00 0x250 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x167>;
		};

		spi@2100000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x2100000 0x00 0x400>;
			interrupts = <0x00 0xb8 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x08 0x10a 0x01>;
			clocks = <0x07 0x10a 0x01>;
			status = "disabled";
			phandle = <0x168>;
		};

		spi@2110000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x2110000 0x00 0x400>;
			interrupts = <0x00 0xb9 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x08 0x10b 0x01>;
			clocks = <0x07 0x10b 0x01>;
			status = "disabled";
			phandle = <0x169>;
		};

		spi@2120000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x2120000 0x00 0x400>;
			interrupts = <0x00 0xba 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x08 0x10c 0x01>;
			clocks = <0x07 0x10c 0x01>;
			status = "disabled";
			phandle = <0x16a>;
		};

		spi@2130000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x2130000 0x00 0x400>;
			interrupts = <0x00 0xbb 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x08 0x10d 0x01>;
			clocks = <0x07 0x10d 0x01>;
			status = "okay";
			ti,spi-num-cs = <0x04>;
			pinctrl-names = "default";
			pinctrl-0 = <0x76>;
			phandle = <0x16b>;

			spidev@0 {
				compatible = "ti,spi-evm";
				spi-max-frequency = <0x2faf08>;
				reg = <0x00>;
				spi-cpol = <0x01>;
				spi-cpha = <0x01>;
			};

			spidev@1 {
				compatible = "ti,spi-evm";
				spi-max-frequency = <0x2faf08>;
				reg = <0x01>;
				spi-cpol = <0x00>;
				spi-cpha = <0x01>;
			};

			spidev@2 {
				compatible = "ti,spi-evm";
				spi-max-frequency = <0x2faf08>;
				reg = <0x02>;
				spi-cpol = <0x00>;
				spi-cpha = <0x00>;
			};

			spidev@3 {
				compatible = "ti,spi-evm";
				spi-max-frequency = <0x2faf08>;
				reg = <0x03>;
				spi-cpol = <0x00>;
				spi-cpha = <0x01>;
			};
		};

		spi@2140000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x2140000 0x00 0x400>;
			interrupts = <0x00 0xbc 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x08 0x10e 0x01>;
			clocks = <0x07 0x10e 0x01>;
			status = "disabled";
			phandle = <0x16c>;
		};

		spi@2150000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x2150000 0x00 0x400>;
			interrupts = <0x00 0xbd 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x08 0x10f 0x01>;
			clocks = <0x07 0x10f 0x01>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x77>;
			phandle = <0x16d>;

			spidev@0 {
				compatible = "ti,spi-evm";
				spi-max-frequency = <0x2faf08>;
				reg = <0x00>;
				spi-cpol = <0x01>;
				spi-cpha = <0x01>;
			};
		};

		spi@2160000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x2160000 0x00 0x400>;
			interrupts = <0x00 0xbe 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x08 0x110 0x01>;
			clocks = <0x07 0x110 0x01>;
			status = "disabled";
			phandle = <0x16e>;
		};

		spi@2170000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x2170000 0x00 0x400>;
			interrupts = <0x00 0xbf 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x08 0x111 0x01>;
			clocks = <0x07 0x111 0x01>;
			status = "disabled";
			phandle = <0x16f>;
		};

		esm@700000 {
			compatible = "ti,j721e-esm";
			reg = <0x00 0x700000 0x00 0x1000>;
			ti,esm-pins = <0x158 0x159>;
			phandle = <0x170>;
		};

		phy@4480000 {
			compatible = "ti,j721e-dphy";
			reg = <0x00 0x4480000 0x00 0x1000>;
			clocks = <0x07 0x128 0x01 0x07 0x128 0x03>;
			clock-names = "psm\0pll_ref";
			#phy-cells = <0x00>;
			power-domains = <0x08 0x128 0x01>;
			assigned-clocks = <0x07 0x128 0x03>;
			assigned-clock-parents = <0x07 0x128 0x04>;
			assigned-clock-rates = <0x124f800>;
			status = "disabled";
			phandle = <0x55>;
		};
	};

	thermal-zones {
		phandle = <0x171>;

		wkup-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x78 0x00>;
			phandle = <0x172>;

			trips {

				wkup-crit {
					temperature = <0x1e848>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x173>;
				};
			};
		};

		mpu-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x78 0x01>;
			phandle = <0x174>;

			trips {

				mpu-crit {
					temperature = <0x1e848>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x175>;
				};
			};
		};

		c7x-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x78 0x02>;
			phandle = <0x176>;

			trips {

				c7x-crit {
					temperature = <0x1e848>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x177>;
				};
			};
		};

		gpu-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x78 0x03>;
			phandle = <0x178>;

			trips {

				gpu-crit {
					temperature = <0x1e848>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x179>;
				};
			};
		};

		r5f-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x78 0x04>;
			phandle = <0x17a>;

			trips {

				r5f-crit {
					temperature = <0x1e848>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x17b>;
				};
			};
		};
	};

	clock-cmnrefclk {
		#clock-cells = <0x00>;
		compatible = "fixed-clock";
		clock-frequency = <0x00>;
		phandle = <0x29>;
	};

	clock-cmnrefclk1 {
		#clock-cells = <0x00>;
		compatible = "fixed-clock";
		clock-frequency = <0x5f5e100>;
		phandle = <0x2b>;
	};

	memory@80000000 {
		device_type = "memory";
		bootph-all;
		reg = <0x00 0x80000000 0x00 0x80000000 0x08 0x80000000 0x00 0x80000000>;
	};

	reserved-memory {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		phandle = <0x17c>;

		vision-apps-core-heap-memory-hi@880000000 {
			phandle = <0x19d>;
			no-map;
			reg = <0x08 0x80000000 0x00 0x27000000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-virtual-eth-buffers@e4800000 {
			phandle = <0x18c>;
			no-map;
			reg = <0x00 0xe4800000 0x00 0x1800000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-virtual-eth-queues@e4000000 {
			phandle = <0x18b>;
			no-map;
			reg = <0x00 0xe4000000 0x00 0x800000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-core-heap-memory-lo@d8000000 {
			phandle = <0x19c>;
			no-map;
			reg = <0x00 0xd8000000 0x00 0xc000000>;
			compatible = "shared-dma-pool";
		};

		vision_apps_shared-memories {
			phandle = <0x19b>;
			reg = <0x00 0xb8000000 0x00 0x20000000>;
			compatible = "dma-heap-carveout";
		};

		vision-apps-c71-memory@b2100000 {
			phandle = <0x198>;
			no-map;
			reg = <0x00 0xb2100000 0x00 0x5f00000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-c71-dma-memory@b2000000 {
			phandle = <0x197>;
			no-map;
			reg = <0x00 0xb2000000 0x00 0x100000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-dma-memory@ac000000 {
			phandle = <0x19a>;
			no-map;
			reg = <0x00 0xac000000 0x00 0x6000000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-rtos-ipc-memory-region {
			phandle = <0x199>;
			no-map;
			alignment = <0x1000>;
			reg = <0x00 0xaa000000 0x00 0x2000000>;
		};

		vision-apps-c66-memory@a9100000 {
			phandle = <0x196>;
			no-map;
			reg = <0x00 0xa9100000 0x00 0xf00000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-c66-dma-memory@a9000000 {
			phandle = <0x193>;
			no-map;
			reg = <0x00 0xa9000000 0x00 0x100000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-c66-memory@a8100000 {
			phandle = <0x194>;
			no-map;
			reg = <0x00 0xa8100000 0x00 0xf00000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-c66-dma-memory@a8000000 {
			phandle = <0x195>;
			no-map;
			reg = <0x00 0xa8000000 0x00 0x100000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-memory@a7100000 {
			phandle = <0x192>;
			no-map;
			reg = <0x00 0xa7100000 0x00 0xf00000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-dma-memory@a7000000 {
			phandle = <0x191>;
			no-map;
			reg = <0x00 0xa7000000 0x00 0x100000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-memory@a6100000 {
			phandle = <0x190>;
			no-map;
			reg = <0x00 0xa6100000 0x00 0xf00000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-dma-memory@a6000000 {
			phandle = <0x18f>;
			no-map;
			reg = <0x00 0xa6000000 0x00 0x100000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-memory@a4100000 {
			phandle = <0x18e>;
			no-map;
			reg = <0x00 0xa4100000 0x00 0x1f00000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-dma-memory@a4000000 {
			phandle = <0x18d>;
			no-map;
			reg = <0x00 0xa4000000 0x00 0x100000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-memory@a2100000 {
			phandle = <0x18a>;
			no-map;
			reg = <0x00 0xa2100000 0x00 0x1f00000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-dma-memory@a2000000 {
			phandle = <0x189>;
			no-map;
			reg = <0x00 0xa2000000 0x00 0x100000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-memory@a1100000 {
			phandle = <0x188>;
			no-map;
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-dma-memory@a1000000 {
			phandle = <0x187>;
			no-map;
			reg = <0x00 0xa1000000 0x00 0x100000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-memory@a0100000 {
			phandle = <0x186>;
			no-map;
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			compatible = "shared-dma-pool";
		};

		vision-apps-r5f-dma-memory@a0000000 {
			phandle = <0x185>;
			no-map;
			reg = <0x00 0xa0000000 0x00 0x100000>;
			compatible = "shared-dma-pool";
		};

		r5f-virtual-eth-buffers@ac200000 {
			status = "disabled";
			phandle = <0x184>;
			no-map;
			reg = <0x00 0xac200000 0x00 0x1e00000>;
			compatible = "shared-dma-pool";
		};

		r5f-virtual-eth-queues@ac000000 {
			status = "disabled";
			phandle = <0x183>;
			no-map;
			reg = <0x00 0xac000000 0x00 0x200000>;
			compatible = "shared-dma-pool";
		};

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x00 0x20000000>;
			linux,cma-default;
		};

		optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x1800000>;
			alignment = <0x1000>;
			no-map;
			phandle = <0x17d>;
		};

		r5f-dma-memory@a0000000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
			phandle = <0x1d>;
		};

		r5f-memory@a0100000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
			phandle = <0x1e>;
		};

		r5f-dma-memory@a1000000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1000000 0x00 0x100000>;
			no-map;
			phandle = <0x20>;
		};

		r5f-memory@a1100000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			no-map;
			phandle = <0x21>;
		};

		r5f-dma-memory@a2000000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
			phandle = <0x5a>;
		};

		r5f-memory@a2100000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
			phandle = <0x5b>;
		};

		r5f-dma-memory@a3000000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3000000 0x00 0x100000>;
			no-map;
			phandle = <0x5d>;
		};

		r5f-memory@a3100000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3100000 0x00 0xf00000>;
			no-map;
			phandle = <0x5e>;
		};

		r5f-dma-memory@a4000000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4000000 0x00 0x100000>;
			no-map;
			phandle = <0x61>;
		};

		r5f-memory@a4100000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4100000 0x00 0xf00000>;
			no-map;
			phandle = <0x62>;
		};

		r5f-dma-memory@a5000000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa5000000 0x00 0x100000>;
			no-map;
			phandle = <0x64>;
		};

		r5f-memory@a5100000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa5100000 0x00 0xf00000>;
			no-map;
			phandle = <0x65>;
		};

		c66-dma-memory@a6000000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa6000000 0x00 0x100000>;
			no-map;
			phandle = <0x6b>;
		};

		c66-memory@a6100000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa6100000 0x00 0xf00000>;
			no-map;
			phandle = <0x69>;
		};

		c66-dma-memory@a7000000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa7000000 0x00 0x100000>;
			no-map;
			phandle = <0x68>;
		};

		c66-memory@a7100000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa7100000 0x00 0xf00000>;
			no-map;
			phandle = <0x6c>;
		};

		c71-dma-memory@a8000000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa8000000 0x00 0x100000>;
			no-map;
			phandle = <0x6f>;
		};

		c71-memory@a8100000 {
			status = "disabled";
			compatible = "shared-dma-pool";
			reg = <0x00 0xa8100000 0x00 0xf00000>;
			no-map;
			phandle = <0x70>;
		};

		ipc-memories@aa000000 {
			status = "disabled";
			reg = <0x00 0xaa000000 0x00 0x1c00000>;
			alignment = <0x1000>;
			no-map;
			phandle = <0x17e>;
		};
	};

	aliases {
		serial0 = "/bus@100000/bus@28380000/serial@42300000";
		serial1 = "/bus@100000/bus@28380000/serial@40a00000";
		serial2 = "/bus@100000/serial@2800000";
		serial7 = "/bus@100000/serial@2850000";
		spi3 = "/bus@100000/spi@2130000";
		spi5 = "/bus@100000/spi@2150000";
		ethernet0 = "/bus@100000/bus@28380000/ethernet@46000000/ethernet-ports/port@1";
		mmc0 = "/bus@100000/mmc@4f80000";
		mmc1 = "/bus@100000/mmc@4fb0000";
	};

	fixedregulator-evm12v0 {
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <0xb71b00>;
		regulator-max-microvolt = <0xb71b00>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x79>;
	};

	fixedregulator-vsys3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		vin-supply = <0x79>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x7a>;
	};

	fixedregulator-vsys5v0 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0x79>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x17f>;
	};

	fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <0x7a>;
		phandle = <0x180>;
	};

	gpio-regulator-tps659411 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <0x7b>;
		regulator-name = "vdd_sd_dv";
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x325aa0>;
		regulator-boot-on;
		vin-supply = <0x7a>;
		gpios = <0x19 0x6f 0x00>;
		states = <0x1b7740 0x00 0x325aa0 0x01>;
		phandle = <0x181>;
	};

	regulator-dp-pwr {
		compatible = "regulator-fixed";
		regulator-name = "dp-pwr";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		enable-active-high;
		phandle = <0x7c>;
	};

	connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <0x7c>;
		phandle = <0x182>;

		port {

			endpoint {
				remote-endpoint = <0x7d>;
				phandle = <0x54>;
			};
		};
	};

	pps_gpio {
		status = "okay";
		compatible = "pps-gpio";
		gpios = <0x40 0x0d 0x00>;
	};

	__symbols__ {
		vision_apps_core_heaps_hi = "/reserved-memory/vision-apps-core-heap-memory-hi@880000000";
		vision_apps_main_r5fss0_core0_shared_memory_bufpool_region = "/reserved-memory/vision-apps-r5f-virtual-eth-buffers@e4800000";
		vision_apps_main_r5fss0_core0_shared_memory_queue_region = "/reserved-memory/vision-apps-r5f-virtual-eth-queues@e4000000";
		vision_apps_core_heaps_lo = "/reserved-memory/vision-apps-core-heap-memory-lo@d8000000";
		vision_apps_shared_region = "/reserved-memory/vision_apps_shared-memories";
		vision_apps_c71_0_memory_region = "/reserved-memory/vision-apps-c71-memory@b2100000";
		vision_apps_c71_0_dma_memory_region = "/reserved-memory/vision-apps-c71-dma-memory@b2000000";
		vision_apps_memory_region = "/reserved-memory/vision-apps-dma-memory@ac000000";
		vision_apps_rtos_ipc_memory_region = "/reserved-memory/vision-apps-rtos-ipc-memory-region";
		vision_apps_c66_1_memory_region = "/reserved-memory/vision-apps-c66-memory@a9100000";
		vision_apps_c66_0_dma_memory_region = "/reserved-memory/vision-apps-c66-dma-memory@a9000000";
		vision_apps_c66_0_memory_region = "/reserved-memory/vision-apps-c66-memory@a8100000";
		vision_apps_c66_1_dma_memory_region = "/reserved-memory/vision-apps-c66-dma-memory@a8000000";
		vision_apps_main_r5fss1_core1_memory_region = "/reserved-memory/vision-apps-r5f-memory@a7100000";
		vision_apps_main_r5fss1_core1_dma_memory_region = "/reserved-memory/vision-apps-r5f-dma-memory@a7000000";
		vision_apps_main_r5fss1_core0_memory_region = "/reserved-memory/vision-apps-r5f-memory@a6100000";
		vision_apps_main_r5fss1_core0_dma_memory_region = "/reserved-memory/vision-apps-r5f-dma-memory@a6000000";
		vision_apps_main_r5fss0_core1_memory_region = "/reserved-memory/vision-apps-r5f-memory@a4100000";
		vision_apps_main_r5fss0_core1_dma_memory_region = "/reserved-memory/vision-apps-r5f-dma-memory@a4000000";
		vision_apps_main_r5fss0_core0_memory_region = "/reserved-memory/vision-apps-r5f-memory@a2100000";
		vision_apps_main_r5fss0_core0_dma_memory_region = "/reserved-memory/vision-apps-r5f-dma-memory@a2000000";
		vision_apps_mcu_r5fss0_core1_memory_region = "/reserved-memory/vision-apps-r5f-memory@a1100000";
		vision_apps_mcu_r5fss0_core1_dma_memory_region = "/reserved-memory/vision-apps-r5f-dma-memory@a1000000";
		vision_apps_mcu_r5fss0_core0_memory_region = "/reserved-memory/vision-apps-r5f-memory@a0100000";
		vision_apps_mcu_r5fss0_core0_dma_memory_region = "/reserved-memory/vision-apps-r5f-dma-memory@a0000000";
		main_r5fss0_core0_shared_memory_bufpool_region = "/reserved-memory/r5f-virtual-eth-buffers@ac200000";
		main_r5fss0_core0_shared_memory_queue_region = "/reserved-memory/r5f-virtual-eth-queues@ac000000";
		cluster0 = "/cpus/cpu-map/cluster0";
		cpu0 = "/cpus/cpu@0";
		cpu1 = "/cpus/cpu@1";
		L2_0 = "/l2-cache0";
		msmc_l3 = "/l3-cache0";
		psci = "/firmware/psci";
		a72_timer0 = "/timer-cl0-cpu0";
		pmu = "/pmu";
		cbass_main = "/bus@100000";
		cbass_mcu_wakeup = "/bus@100000/bus@28380000";
		dmsc = "/bus@100000/bus@28380000/system-controller@44083000";
		k3_pds = "/bus@100000/bus@28380000/system-controller@44083000/power-controller";
		k3_clks = "/bus@100000/bus@28380000/system-controller@44083000/clock-controller";
		k3_reset = "/bus@100000/bus@28380000/system-controller@44083000/reset-controller";
		mcu_conf = "/bus@100000/bus@28380000/syscon@40f00000";
		phy_gmii_sel = "/bus@100000/bus@28380000/syscon@40f00000/phy@4040";
		wkup_conf = "/bus@100000/bus@28380000/bus@43000000";
		chipid = "/bus@100000/bus@28380000/bus@43000000/chipid@14";
		wkup_pmx0 = "/bus@100000/bus@28380000/pinctrl@4301c000";
		wkup_i2c0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/wkup-i2c0-default-pins";
		mcu_fss0_ospi0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu_fss0_ospi0-default-pins";
		mcu_fss0_hpb0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-fss0-hpb0-default-pins";
		mcu_cpsw_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-cpsw-default-pins";
		mcu_mdio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mdio1-default-pins";
		wkup_gpio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/wkup-gpio-default-pins";
		mcu_rgmii1_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-rgmii1-default-pins";
		mcu_timerio_input = "/bus@100000/bus@28380000/pinctrl@40f04200";
		mcu_timerio_output = "/bus@100000/bus@28380000/pinctrl@40f04280";
		mcu_ram = "/bus@100000/bus@28380000/sram@41c00000";
		mcu_timer0 = "/bus@100000/bus@28380000/timer@40400000";
		mcu_timer1 = "/bus@100000/bus@28380000/timer@40410000";
		mcu_timer2 = "/bus@100000/bus@28380000/timer@40420000";
		mcu_timer3 = "/bus@100000/bus@28380000/timer@40430000";
		mcu_timer4 = "/bus@100000/bus@28380000/timer@40440000";
		mcu_timer5 = "/bus@100000/bus@28380000/timer@40450000";
		mcu_timer6 = "/bus@100000/bus@28380000/timer@40460000";
		mcu_timer7 = "/bus@100000/bus@28380000/timer@40470000";
		mcu_timer8 = "/bus@100000/bus@28380000/timer@40480000";
		mcu_timer9 = "/bus@100000/bus@28380000/timer@40490000";
		wkup_uart0 = "/bus@100000/bus@28380000/serial@42300000";
		mcu_uart0 = "/bus@100000/bus@28380000/serial@40a00000";
		wkup_gpio_intr = "/bus@100000/bus@28380000/interrupt-controller@42200000";
		wkup_gpio0 = "/bus@100000/bus@28380000/gpio@42110000";
		wkup_gpio1 = "/bus@100000/bus@28380000/gpio@42100000";
		mcu_i2c0 = "/bus@100000/bus@28380000/i2c@40b00000";
		mcu_i2c1 = "/bus@100000/bus@28380000/i2c@40b10000";
		wkup_i2c0 = "/bus@100000/bus@28380000/i2c@42120000";
		fss = "/bus@100000/bus@28380000/bus@47000000";
		hbmc_mux = "/bus@100000/bus@28380000/bus@47000000/mux-controller@47000004";
		hbmc = "/bus@100000/bus@28380000/bus@47000000/hyperbus@47034000";
		ospi0 = "/bus@100000/bus@28380000/bus@47000000/spi@47040000";
		ospi1 = "/bus@100000/bus@28380000/bus@47000000/spi@47050000";
		tscadc0 = "/bus@100000/bus@28380000/tscadc@40200000";
		tscadc1 = "/bus@100000/bus@28380000/tscadc@40210000";
		mcu_navss = "/bus@100000/bus@28380000/bus@28380000";
		mcu_ringacc = "/bus@100000/bus@28380000/bus@28380000/ringacc@2b800000";
		mcu_udmap = "/bus@100000/bus@28380000/bus@28380000/dma-controller@285c0000";
		secure_proxy_mcu = "/bus@100000/bus@28380000/mailbox@2a480000";
		mcu_cpsw = "/bus@100000/bus@28380000/ethernet@46000000";
		cpsw_port1 = "/bus@100000/bus@28380000/ethernet@46000000/ethernet-ports/port@1";
		davinci_mdio = "/bus@100000/bus@28380000/ethernet@46000000/mdio@f00";
		phy2 = "/bus@100000/bus@28380000/ethernet@46000000/mdio@f00/ethernet-phy@2";
		mcu_r5fss0 = "/bus@100000/bus@28380000/r5fss@41000000";
		mcu_r5fss0_core0 = "/bus@100000/bus@28380000/r5fss@41000000/r5f@41000000";
		mcu_r5fss0_core1 = "/bus@100000/bus@28380000/r5fss@41000000/r5f@41400000";
		mcu_mcan0 = "/bus@100000/bus@28380000/can@40528000";
		mcu_mcan1 = "/bus@100000/bus@28380000/can@40568000";
		mcu_spi0 = "/bus@100000/bus@28380000/spi@40300000";
		mcu_spi1 = "/bus@100000/bus@28380000/spi@40310000";
		mcu_spi2 = "/bus@100000/bus@28380000/spi@40320000";
		wkup_vtm0 = "/bus@100000/bus@28380000/temperature-sensor@42040000";
		mcu_esm = "/bus@100000/bus@28380000/esm@40800000";
		msmc_ram = "/bus@100000/sram@70000000";
		scm_conf = "/bus@100000/scm-conf@100000";
		serdes_ln_ctrl = "/bus@100000/scm-conf@100000/mux-controller@4080";
		cpsw0_phy_gmii_sel = "/bus@100000/scm-conf@100000/phy@4044";
		usb_serdes_mux = "/bus@100000/scm-conf@100000/mux-controller@4000";
		ehrpwm_tbclk = "/bus@100000/scm-conf@100000/clock-controller@4140";
		main_ehrpwm0 = "/bus@100000/pwm@3000000";
		main_ehrpwm1 = "/bus@100000/pwm@3010000";
		main_ehrpwm2 = "/bus@100000/pwm@3020000";
		main_ehrpwm3 = "/bus@100000/pwm@3030000";
		main_ehrpwm4 = "/bus@100000/pwm@3040000";
		main_ehrpwm5 = "/bus@100000/pwm@3050000";
		gic500 = "/bus@100000/interrupt-controller@1800000";
		gic_its = "/bus@100000/interrupt-controller@1800000/msi-controller@1820000";
		main_gpio_intr = "/bus@100000/interrupt-controller@a00000";
		main_navss = "/bus@100000/bus@30000000";
		main_navss_intr = "/bus@100000/bus@30000000/interrupt-controller@310e0000";
		main_udmass_inta = "/bus@100000/bus@30000000/interrupt-controller@33d00000";
		secure_proxy_main = "/bus@100000/bus@30000000/mailbox@32c00000";
		smmu0 = "/bus@100000/bus@30000000/iommu@36600000";
		hwspinlock = "/bus@100000/bus@30000000/spinlock@30e00000";
		mailbox0_cluster0 = "/bus@100000/bus@30000000/mailbox@31f80000";
		mbox_mcu_r5fss0_core0 = "/bus@100000/bus@30000000/mailbox@31f80000/mbox-mcu-r5fss0-core0";
		mbox_mcu_r5fss0_core1 = "/bus@100000/bus@30000000/mailbox@31f80000/mbox-mcu-r5fss0-core1";
		mailbox0_cluster1 = "/bus@100000/bus@30000000/mailbox@31f81000";
		mbox_main_r5fss0_core0 = "/bus@100000/bus@30000000/mailbox@31f81000/mbox-main-r5fss0-core0";
		mbox_main_r5fss0_core1 = "/bus@100000/bus@30000000/mailbox@31f81000/mbox-main-r5fss0-core1";
		mailbox0_cluster2 = "/bus@100000/bus@30000000/mailbox@31f82000";
		mbox_main_r5fss1_core0 = "/bus@100000/bus@30000000/mailbox@31f82000/mbox-main-r5fss1-core0";
		mbox_main_r5fss1_core1 = "/bus@100000/bus@30000000/mailbox@31f82000/mbox-main-r5fss1-core1";
		mailbox0_cluster3 = "/bus@100000/bus@30000000/mailbox@31f83000";
		mbox_c66_0 = "/bus@100000/bus@30000000/mailbox@31f83000/mbox-c66-0";
		mbox_c66_1 = "/bus@100000/bus@30000000/mailbox@31f83000/mbox-c66-1";
		mailbox0_cluster4 = "/bus@100000/bus@30000000/mailbox@31f84000";
		mbox_c71_0 = "/bus@100000/bus@30000000/mailbox@31f84000/mbox-c71-0";
		mailbox0_cluster5 = "/bus@100000/bus@30000000/mailbox@31f85000";
		mailbox0_cluster6 = "/bus@100000/bus@30000000/mailbox@31f86000";
		mailbox0_cluster7 = "/bus@100000/bus@30000000/mailbox@31f87000";
		mailbox0_cluster8 = "/bus@100000/bus@30000000/mailbox@31f88000";
		mailbox0_cluster9 = "/bus@100000/bus@30000000/mailbox@31f89000";
		mailbox0_cluster10 = "/bus@100000/bus@30000000/mailbox@31f8a000";
		mailbox0_cluster11 = "/bus@100000/bus@30000000/mailbox@31f8b000";
		main_ringacc = "/bus@100000/bus@30000000/ringacc@3c000000";
		main_udmap = "/bus@100000/bus@30000000/dma-controller@31150000";
		cpsw0 = "/bus@100000/ethernet@c000000";
		cpsw0_port1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
		cpsw0_port2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
		cpsw0_port3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
		cpsw0_port4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
		cpsw0_port5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
		cpsw0_port6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
		cpsw0_port7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
		cpsw0_port8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
		cpsw9g_mdio = "/bus@100000/ethernet@c000000/mdio@f00";
		main_crypto = "/bus@100000/crypto@4e00000";
		rng = "/bus@100000/crypto@4e00000/rng@4e10000";
		main_pmx0 = "/bus@100000/pinctrl@11c000";
		main_uart0_pins_default = "/bus@100000/pinctrl@11c000/main-uart0-default-pins";
		main_mmc1_pins_default = "/bus@100000/pinctrl@11c000/main-mmc1-default-pins";
		vdd_sd_dv_alt_pins_default = "/bus@100000/pinctrl@11c000/vdd-sd-dv-alt-default-pins";
		dp0_pins_default = "/bus@100000/pinctrl@11c000/dp0-default-pins";
		mcasp10_pins_default = "/bus@100000/pinctrl@11c000/mcasp10-default-pins";
		main_gpio0_pins_default = "/bus@100000/pinctrl@11c000/main-gpio0-default-pins";
		main_gpio1_pins_default = "/bus@100000/pinctrl@11c000/main-gpio1-default-pins";
		main_mcasp1_pins_default = "/bus@100000/pinctrl@11c000/main-mcasp1-default-pins";
		main_mmcsd1_pins_default = "/bus@100000/pinctrl@11c000/main-mmcsd1-default-pins";
		main_pcie3_pins_default = "/bus@100000/pinctrl@11c000/main-pcie3-default-pins";
		main_spi3_pins_default = "/bus@100000/pinctrl@11c000/main-spi3-default-pins";
		main_spi5_pins_default = "/bus@100000/pinctrl@11c000/main_spi5-default-pins";
		main_system0_pins_default = "/bus@100000/pinctrl@11c000/main-system0-default-pins";
		main_uart5_pins_default = "/bus@100000/pinctrl@11c000/main-uart5-default-pins";
		main_timerio_input = "/bus@100000/pinctrl@104200";
		main_timerio_output = "/bus@100000/pinctrl@104280";
		ti_csi2rx0 = "/bus@100000/ticsi2rx@4500000";
		cdns_csi2rx0 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000";
		csi0_port0 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@0";
		csi0_port1 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@1";
		csi0_port2 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@2";
		csi0_port3 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@3";
		csi0_port4 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@4";
		ti_csi2rx1 = "/bus@100000/ticsi2rx@4510000";
		cdns_csi2rx1 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000";
		csi1_port0 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@0";
		csi1_port1 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@1";
		csi1_port2 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@2";
		csi1_port3 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@3";
		csi1_port4 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@4";
		dphy0 = "/bus@100000/phy@4580000";
		dphy1 = "/bus@100000/phy@4590000";
		serdes_wiz0 = "/bus@100000/wiz@5000000";
		wiz0_pll0_refclk = "/bus@100000/wiz@5000000/pll0-refclk";
		wiz0_pll1_refclk = "/bus@100000/wiz@5000000/pll1-refclk";
		wiz0_refclk_dig = "/bus@100000/wiz@5000000/refclk-dig";
		wiz0_cmn_refclk_dig_div = "/bus@100000/wiz@5000000/cmn-refclk-dig-div";
		wiz0_cmn_refclk1_dig_div = "/bus@100000/wiz@5000000/cmn-refclk1-dig-div";
		serdes0 = "/bus@100000/wiz@5000000/serdes@5000000";
		serdes0_pcie_link = "/bus@100000/wiz@5000000/serdes@5000000/phy@0";
		serdes_wiz1 = "/bus@100000/wiz@5010000";
		wiz1_pll0_refclk = "/bus@100000/wiz@5010000/pll0-refclk";
		wiz1_pll1_refclk = "/bus@100000/wiz@5010000/pll1-refclk";
		wiz1_refclk_dig = "/bus@100000/wiz@5010000/refclk-dig";
		wiz1_cmn_refclk_dig_div = "/bus@100000/wiz@5010000/cmn-refclk-dig-div";
		wiz1_cmn_refclk1_dig_div = "/bus@100000/wiz@5010000/cmn-refclk1-dig-div";
		serdes1 = "/bus@100000/wiz@5010000/serdes@5010000";
		serdes1_sgmii_link = "/bus@100000/wiz@5010000/serdes@5010000/phy@0";
		serdes_wiz2 = "/bus@100000/wiz@5020000";
		wiz2_pll0_refclk = "/bus@100000/wiz@5020000/pll0-refclk";
		wiz2_pll1_refclk = "/bus@100000/wiz@5020000/pll1-refclk";
		wiz2_refclk_dig = "/bus@100000/wiz@5020000/refclk-dig";
		wiz2_cmn_refclk_dig_div = "/bus@100000/wiz@5020000/cmn-refclk-dig-div";
		wiz2_cmn_refclk1_dig_div = "/bus@100000/wiz@5020000/cmn-refclk1-dig-div";
		serdes2 = "/bus@100000/wiz@5020000/serdes@5020000";
		serdes2_pcie_link = "/bus@100000/wiz@5020000/serdes@5020000/phy@0";
		serdes_wiz3 = "/bus@100000/wiz@5030000";
		wiz3_pll0_refclk = "/bus@100000/wiz@5030000/pll0-refclk";
		wiz3_pll1_refclk = "/bus@100000/wiz@5030000/pll1-refclk";
		wiz3_refclk_dig = "/bus@100000/wiz@5030000/refclk-dig";
		wiz3_cmn_refclk_dig_div = "/bus@100000/wiz@5030000/cmn-refclk-dig-div";
		wiz3_cmn_refclk1_dig_div = "/bus@100000/wiz@5030000/cmn-refclk1-dig-div";
		serdes3 = "/bus@100000/wiz@5030000/serdes@5030000";
		serdes3_usb_link = "/bus@100000/wiz@5030000/serdes@5030000/phy@0";
		pcie0_rc = "/bus@100000/pcie@2900000";
		pcie1_rc = "/bus@100000/pcie@2910000";
		pcie2_rc = "/bus@100000/pcie@2920000";
		pcie3_rc = "/bus@100000/pcie@2930000";
		serdes_wiz4 = "/bus@100000/wiz@5050000";
		serdes4 = "/bus@100000/wiz@5050000/serdes@5050000";
		torrent_phy_dp = "/bus@100000/wiz@5050000/serdes@5050000/phy@0";
		main_timer0 = "/bus@100000/timer@2400000";
		main_timer1 = "/bus@100000/timer@2410000";
		main_timer2 = "/bus@100000/timer@2420000";
		main_timer3 = "/bus@100000/timer@2430000";
		main_timer4 = "/bus@100000/timer@2440000";
		main_timer5 = "/bus@100000/timer@2450000";
		main_timer6 = "/bus@100000/timer@2460000";
		main_timer7 = "/bus@100000/timer@2470000";
		main_timer8 = "/bus@100000/timer@2480000";
		main_timer9 = "/bus@100000/timer@2490000";
		main_timer10 = "/bus@100000/timer@24a0000";
		main_timer11 = "/bus@100000/timer@24b0000";
		main_timer12 = "/bus@100000/timer@24c0000";
		main_timer13 = "/bus@100000/timer@24d0000";
		main_timer14 = "/bus@100000/timer@24e0000";
		main_timer15 = "/bus@100000/timer@24f0000";
		main_timer16 = "/bus@100000/timer@2500000";
		main_timer17 = "/bus@100000/timer@2510000";
		main_timer18 = "/bus@100000/timer@2520000";
		main_timer19 = "/bus@100000/timer@2530000";
		main_uart0 = "/bus@100000/serial@2800000";
		main_uart1 = "/bus@100000/serial@2810000";
		main_uart2 = "/bus@100000/serial@2820000";
		main_uart3 = "/bus@100000/serial@2830000";
		main_uart4 = "/bus@100000/serial@2840000";
		main_uart5 = "/bus@100000/serial@2850000";
		main_uart6 = "/bus@100000/serial@2860000";
		main_uart7 = "/bus@100000/serial@2870000";
		main_uart8 = "/bus@100000/serial@2880000";
		main_uart9 = "/bus@100000/serial@2890000";
		main_gpio0 = "/bus@100000/gpio@600000";
		main_gpio1 = "/bus@100000/gpio@601000";
		main_gpio2 = "/bus@100000/gpio@610000";
		main_gpio3 = "/bus@100000/gpio@611000";
		main_gpio4 = "/bus@100000/gpio@620000";
		main_gpio5 = "/bus@100000/gpio@621000";
		main_gpio6 = "/bus@100000/gpio@630000";
		main_gpio7 = "/bus@100000/gpio@631000";
		main_sdhci0 = "/bus@100000/mmc@4f80000";
		main_sdhci1 = "/bus@100000/mmc@4fb0000";
		main_sdhci2 = "/bus@100000/mmc@4f98000";
		usbss0 = "/bus@100000/cdns-usb@4104000";
		usb0 = "/bus@100000/cdns-usb@4104000/usb@6000000";
		usbss1 = "/bus@100000/cdns-usb@4114000";
		usb1 = "/bus@100000/cdns-usb@4114000/usb@6400000";
		main_i2c0 = "/bus@100000/i2c@2000000";
		main_i2c1 = "/bus@100000/i2c@2010000";
		main_i2c2 = "/bus@100000/i2c@2020000";
		main_i2c3 = "/bus@100000/i2c@2030000";
		main_i2c4 = "/bus@100000/i2c@2040000";
		main_i2c5 = "/bus@100000/i2c@2050000";
		main_i2c6 = "/bus@100000/i2c@2060000";
		vxe384 = "/bus@100000/video-encoder@4200000";
		d5520 = "/bus@100000/video-decoder@4300000";
		ufs_wrapper = "/bus@100000/ufs-wrapper@4e80000";
		mhdp = "/bus@100000/dp-bridge@a000000";
		dp0_ports = "/bus@100000/dp-bridge@a000000/ports";
		dp0_in = "/bus@100000/dp-bridge@a000000/ports/port@0/endpoint";
		dp0_out = "/bus@100000/dp-bridge@a000000/ports/port@4/endpoint";
		dsi0 = "/bus@100000/dsi@48000000";
		dsi0_ports = "/bus@100000/dsi@48000000/ports";
		dss = "/bus@100000/dss@4a00000";
		dss_ports = "/bus@100000/dss@4a00000/ports";
		dpi0_out = "/bus@100000/dss@4a00000/ports/port/endpoint";
		mcasp0 = "/bus@100000/mcasp@2b00000";
		mcasp1 = "/bus@100000/mcasp@2b10000";
		mcasp2 = "/bus@100000/mcasp@2b20000";
		mcasp3 = "/bus@100000/mcasp@2b30000";
		mcasp4 = "/bus@100000/mcasp@2b40000";
		mcasp5 = "/bus@100000/mcasp@2b50000";
		mcasp6 = "/bus@100000/mcasp@2b60000";
		mcasp7 = "/bus@100000/mcasp@2b70000";
		mcasp8 = "/bus@100000/mcasp@2b80000";
		mcasp9 = "/bus@100000/mcasp@2b90000";
		mcasp10 = "/bus@100000/mcasp@2ba0000";
		mcasp11 = "/bus@100000/mcasp@2bb0000";
		watchdog0 = "/bus@100000/watchdog@2200000";
		watchdog1 = "/bus@100000/watchdog@2210000";
		main_r5fss0 = "/bus@100000/r5fss@5c00000";
		main_r5fss0_core0 = "/bus@100000/r5fss@5c00000/r5f@5c00000";
		main_r5fss0_core1 = "/bus@100000/r5fss@5c00000/r5f@5d00000";
		main_r5fss1 = "/bus@100000/r5fss@5e00000";
		main_r5fss1_core0 = "/bus@100000/r5fss@5e00000/r5f@5e00000";
		main_r5fss1_core1 = "/bus@100000/r5fss@5e00000/r5f@5f00000";
		c66_0 = "/bus@100000/dsp@4d80800000";
		c66_1 = "/bus@100000/dsp@4d81800000";
		c71_0 = "/bus@100000/dsp@64800000";
		timesync_router = "/bus@100000/pinctrl@a40000";
		mcu_cpsw_cpts = "/bus@100000/pinctrl@a40000/mcu-cpsw-cpts";
		icssg0 = "/bus@100000/icssg@b000000";
		icssg0_mem = "/bus@100000/icssg@b000000/memories@0";
		icssg0_cfg = "/bus@100000/icssg@b000000/cfg@26000";
		icssg0_coreclk_mux = "/bus@100000/icssg@b000000/cfg@26000/clocks/coreclk-mux@3c";
		icssg0_iepclk_mux = "/bus@100000/icssg@b000000/cfg@26000/clocks/iepclk-mux@30";
		icssg0_mii_rt = "/bus@100000/icssg@b000000/mii-rt@32000";
		icssg0_mii_g_rt = "/bus@100000/icssg@b000000/mii-g-rt@33000";
		icssg0_intc = "/bus@100000/icssg@b000000/interrupt-controller@20000";
		pru0_0 = "/bus@100000/icssg@b000000/pru@34000";
		rtu0_0 = "/bus@100000/icssg@b000000/rtu@4000";
		tx_pru0_0 = "/bus@100000/icssg@b000000/txpru@a000";
		pru0_1 = "/bus@100000/icssg@b000000/pru@38000";
		rtu0_1 = "/bus@100000/icssg@b000000/rtu@6000";
		tx_pru0_1 = "/bus@100000/icssg@b000000/txpru@c000";
		icssg0_mdio = "/bus@100000/icssg@b000000/mdio@32400";
		icssg1 = "/bus@100000/icssg@b100000";
		icssg1_mem = "/bus@100000/icssg@b100000/memories@b100000";
		icssg1_cfg = "/bus@100000/icssg@b100000/cfg@26000";
		icssg1_coreclk_mux = "/bus@100000/icssg@b100000/cfg@26000/clocks/coreclk-mux@3c";
		icssg1_iepclk_mux = "/bus@100000/icssg@b100000/cfg@26000/clocks/iepclk-mux@30";
		icssg1_mii_rt = "/bus@100000/icssg@b100000/mii-rt@32000";
		icssg1_mii_g_rt = "/bus@100000/icssg@b100000/mii-g-rt@33000";
		icssg1_intc = "/bus@100000/icssg@b100000/interrupt-controller@20000";
		pru1_0 = "/bus@100000/icssg@b100000/pru@34000";
		rtu1_0 = "/bus@100000/icssg@b100000/rtu@4000";
		tx_pru1_0 = "/bus@100000/icssg@b100000/txpru@a000";
		pru1_1 = "/bus@100000/icssg@b100000/pru@38000";
		rtu1_1 = "/bus@100000/icssg@b100000/rtu@6000";
		tx_pru1_1 = "/bus@100000/icssg@b100000/txpru@c000";
		icssg1_mdio = "/bus@100000/icssg@b100000/mdio@32400";
		gpu = "/bus@100000/gpu@4e20000000";
		main_mcan0 = "/bus@100000/can@2701000";
		main_mcan1 = "/bus@100000/can@2711000";
		main_mcan2 = "/bus@100000/can@2721000";
		main_mcan3 = "/bus@100000/can@2731000";
		main_mcan4 = "/bus@100000/can@2741000";
		main_mcan5 = "/bus@100000/can@2751000";
		main_mcan6 = "/bus@100000/can@2761000";
		main_mcan7 = "/bus@100000/can@2771000";
		main_mcan8 = "/bus@100000/can@2781000";
		main_mcan9 = "/bus@100000/can@2791000";
		main_mcan10 = "/bus@100000/can@27a1000";
		main_mcan11 = "/bus@100000/can@27b1000";
		main_mcan12 = "/bus@100000/can@27c1000";
		main_mcan13 = "/bus@100000/can@27d1000";
		main_spi0 = "/bus@100000/spi@2100000";
		main_spi1 = "/bus@100000/spi@2110000";
		main_spi2 = "/bus@100000/spi@2120000";
		main_spi3 = "/bus@100000/spi@2130000";
		main_spi4 = "/bus@100000/spi@2140000";
		main_spi5 = "/bus@100000/spi@2150000";
		main_spi6 = "/bus@100000/spi@2160000";
		main_spi7 = "/bus@100000/spi@2170000";
		main_esm = "/bus@100000/esm@700000";
		dphy2 = "/bus@100000/phy@4480000";
		thermal_zones = "/thermal-zones";
		wkup_thermal = "/thermal-zones/wkup-thermal";
		wkup_crit = "/thermal-zones/wkup-thermal/trips/wkup-crit";
		mpu_thermal = "/thermal-zones/mpu-thermal";
		mpu_crit = "/thermal-zones/mpu-thermal/trips/mpu-crit";
		c7x_thermal = "/thermal-zones/c7x-thermal";
		c7x_crit = "/thermal-zones/c7x-thermal/trips/c7x-crit";
		gpu_thermal = "/thermal-zones/gpu-thermal";
		gpu_crit = "/thermal-zones/gpu-thermal/trips/gpu-crit";
		r5f_thermal = "/thermal-zones/r5f-thermal";
		r5f_crit = "/thermal-zones/r5f-thermal/trips/r5f-crit";
		cmn_refclk = "/clock-cmnrefclk";
		cmn_refclk1 = "/clock-cmnrefclk1";
		reserved_memory = "/reserved-memory";
		secure_ddr = "/reserved-memory/optee@9e800000";
		mcu_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a0000000";
		mcu_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a0100000";
		mcu_r5fss0_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a1000000";
		mcu_r5fss0_core1_memory_region = "/reserved-memory/r5f-memory@a1100000";
		main_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a2000000";
		main_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a2100000";
		main_r5fss0_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a3000000";
		main_r5fss0_core1_memory_region = "/reserved-memory/r5f-memory@a3100000";
		main_r5fss1_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a4000000";
		main_r5fss1_core0_memory_region = "/reserved-memory/r5f-memory@a4100000";
		main_r5fss1_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a5000000";
		main_r5fss1_core1_memory_region = "/reserved-memory/r5f-memory@a5100000";
		c66_1_dma_memory_region = "/reserved-memory/c66-dma-memory@a6000000";
		c66_0_memory_region = "/reserved-memory/c66-memory@a6100000";
		c66_0_dma_memory_region = "/reserved-memory/c66-dma-memory@a7000000";
		c66_1_memory_region = "/reserved-memory/c66-memory@a7100000";
		c71_0_dma_memory_region = "/reserved-memory/c71-dma-memory@a8000000";
		c71_0_memory_region = "/reserved-memory/c71-memory@a8100000";
		rtos_ipc_memory_region = "/reserved-memory/ipc-memories@aa000000";
		evm_12v0 = "/fixedregulator-evm12v0";
		vsys_3v3 = "/fixedregulator-vsys3v3";
		vsys_5v0 = "/fixedregulator-vsys5v0";
		vdd_mmc1 = "/fixedregulator-sd";
		vdd_sd_dv_alt = "/gpio-regulator-tps659411";
		dp_pwr_3v3 = "/regulator-dp-pwr";
		dp0 = "/connector";
		dp_connector_in = "/connector/port/endpoint";
	};
};

Hi,

Can you check with fresh build and SerDes configuration.
probe of c000000.ethernet failed with error-110 is due to SerDes phy power on failed. It can happen only when serdes reset property is not proper.

Best Regards,
Sudheer

What do you mean by 'fresh build'?
I checked out/evm entry/targetfs/boot/DTB/ti/k3 j721e - common - proc - board. dtb , SerDes - 1 configuration and a comment on my same fdt.
I checked my k3-j721e-common-proc-board.dts and k3-j721e-main.dtsi files,
I used SerDes1's Lane0 and used the configuration you requested 'resets = <&serdes_wiz1 1>; '.

[ 4.739969] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
[ 4.746745] phy phy-5010000.serdes.10: phy poweron failed --> -110
[ 4.753230] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110

The CMN ready timeout is seen in the log of SerDes. Is this related to the reset error?

Can you share this file with me? drivers/phy/cadence/phy-cadence-sierra.c

Hi,

zs xu said:

[ 4.739969] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
[ 4.746745] phy phy-5010000.serdes.10: phy poweron failed --> -110
[ 4.753230] am65-cpsw-nuss: probe of c000000.ethernet failed with error -110

zs xu said:

The CMN ready timeout is seen in the log of SerDes. Is this related to the reset error?

No, It is related to PLL lock issue of SerDes.

zs xu said:

Can you share this file with me? drivers/phy/cadence/phy-cadence-sierra.c

https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/phy/cadence/phy-cadence-sierra.c?h=linux-6.1.y

Can you please share SerDes clock information using k3conf tool.

# k3conf dump clock 293

Best Regards,
Sudheer

root@j721e-evm:~# dmesg | grep cdns-sierra-phy
[    2.822576] cdns-sierra-phy 5000000.serdes: Timeout waiting for PHY status ready
[    3.007569] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[    4.732046] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~# k3conf dump clock 293
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|
|-----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                             | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------------------------------------------|
|   293     |     0    | DEV_SERDES_16G1_CORE_REF1_CLK                                          | CLK_STATE_READY | 100000000       |
|   293     |     1    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
|   293     |     2    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   293     |     3    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153       |
|   293     |     4    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   293     |     5    | DEV_SERDES_16G1_CLK                                                    | CLK_STATE_READY | 125000000       |
|   293     |     6    | DEV_SERDES_16G1_IP1_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     7    | DEV_SERDES_16G1_IP2_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     8    | DEV_SERDES_16G1_IP4_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     9    | DEV_SERDES_16G1_IP4_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    10    | DEV_SERDES_16G1_IP3_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    11    | DEV_SERDES_16G1_IP2_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    12    | DEV_SERDES_16G1_IP1_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    13    | DEV_SERDES_16G1_CORE_REF_CLK                                           | CLK_STATE_READY | 100000000       |
|   293     |    14    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | CLK_STATE_READY | 19200000        |
|   293     |    15    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | CLK_STATE_READY | 0               |
|   293     |    16    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | CLK_STATE_READY | 153846153       |
|   293     |    17    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | CLK_STATE_READY | 100000000       |
|   293     |    18    | DEV_SERDES_16G1_IP2_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    19    | DEV_SERDES_16G1_IP1_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    20    | DEV_SERDES_16G1_IP4_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    21    | DEV_SERDES_16G1_IP3_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    22    | DEV_SERDES_16G1_IP3_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    23    | DEV_SERDES_16G1_IP1_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    24    | DEV_SERDES_16G1_IP2_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    25    | DEV_SERDES_16G1_IP2_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    26    | DEV_SERDES_16G1_REF_DER_OUT_CLK                                        | CLK_STATE_READY | 0               |
|   293     |    27    | DEV_SERDES_16G1_IP1_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    28    | DEV_SERDES_16G1_IP3_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    29    | DEV_SERDES_16G1_IP1_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    30    | DEV_SERDES_16G1_IP1_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    31    | DEV_SERDES_16G1_IP4_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    32    | DEV_SERDES_16G1_IP3_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    33    | DEV_SERDES_16G1_IP4_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    34    | DEV_SERDES_16G1_IP3_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    35    | DEV_SERDES_16G1_IP4_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    36    | DEV_SERDES_16G1_IP2_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    37    | DEV_SERDES_16G1_IP2_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    38    | DEV_SERDES_16G1_IP1_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    39    | DEV_SERDES_16G1_REF_OUT_CLK                                            | CLK_STATE_READY | 0               |
|   293     |    40    | DEV_SERDES_16G1_REF1_OUT_CLK                                           | CLK_STATE_READY | 0               |
|   293     |    41    | DEV_SERDES_16G1_IP4_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    42    | DEV_SERDES_16G1_IP1_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    43    | DEV_SERDES_16G1_IP1_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    44    | DEV_SERDES_16G1_IP4_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    45    | DEV_SERDES_16G1_IP4_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    46    | DEV_SERDES_16G1_IP2_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    47    | DEV_SERDES_16G1_IP2_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    48    | DEV_SERDES_16G1_IP4_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    49    | DEV_SERDES_16G1_IP2_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    50    | DEV_SERDES_16G1_IP2_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    51    | DEV_SERDES_16G1_IP1_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    52    | DEV_SERDES_16G1_IP2_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    53    | DEV_SERDES_16G1_IP4_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    54    | DEV_SERDES_16G1_IP1_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    55    | DEV_SERDES_16G1_IP4_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    60    | DEV_SERDES_16G1_CMN_REFCLK1_M                                          | CLK_STATE_READY | 0               |
|   293     |    67    | DEV_SERDES_16G1_CMN_REFCLK1_P                                          | CLK_STATE_READY | 0               |
|-----------------------------------------------------------------------------------------------------------------------------------|
root@j721e-evm:~#

Hi,

Clock data looks file.

Can you please confirm? are you referencing SerDes node from CPSW Port nodes?

Can you please share following register dump.

CTRLMMR registers of SerDes:

 
SerDes register:

Note: Add base address of SerDes to above address offset to access registers i.e. "SerDes base address  + Address offset above"

Best Regards,
Sudheer

root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep cdns-sierra-phy
[    2.822295] cdns-sierra-phy 5000000.serdes: Timeout waiting for PHY status ready
[    3.007544] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[    4.731827] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x00104090
/dev/mem opened.
Memory mapped at address 0xffffaee1b000.
Read at address  0x00104090 (0xffffaee1b090): 0x00000003
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x00108410
/dev/mem opened.
Memory mapped at address 0xffff91c70000.
Read at address  0x00108410 (0xffff91c70410): 0x00000003
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x05010408
/dev/mem opened.
Memory mapped at address 0xffff85927000.
Read at address  0x05010408 (0xffff85927408): 0x9A000000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x0501040c
/dev/mem opened.
Memory mapped at address 0xffff82a60000.
Read at address  0x0501040C (0xffff82a6040c): 0x92000000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x05010480
/dev/mem opened.
Memory mapped at address 0xffffa6988000.
Read at address  0x05010480 (0xffffa6988480): 0x70800000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x0501048c
/dev/mem opened.
Memory mapped at address 0xffff965b5000.
Read at address  0x0501048C (0xffff965b548c): 0x00000002
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x0501e000
/dev/mem opened.
Memory mapped at address 0xffffbb76f000.
Read at address  0x0501E000 (0xffffbb76f000): 0x00003010
root@j721e-evm:~#
root@j721e-evm:~# k3conf dump clock 293
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                             | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------------------------------------------|
|   293     |     0    | DEV_SERDES_16G1_CORE_REF1_CLK                                          | CLK_STATE_READY | 100000000       |
|   293     |     1    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
|   293     |     2    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   293     |     3    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153       |
|   293     |     4    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   293     |     5    | DEV_SERDES_16G1_CLK                                                    | CLK_STATE_READY | 125000000       |
|   293     |     6    | DEV_SERDES_16G1_IP1_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     7    | DEV_SERDES_16G1_IP2_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     8    | DEV_SERDES_16G1_IP4_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     9    | DEV_SERDES_16G1_IP4_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    10    | DEV_SERDES_16G1_IP3_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    11    | DEV_SERDES_16G1_IP2_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    12    | DEV_SERDES_16G1_IP1_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    13    | DEV_SERDES_16G1_CORE_REF_CLK                                           | CLK_STATE_READY | 100000000       |
|   293     |    14    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | CLK_STATE_READY | 19200000        |
|   293     |    15    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | CLK_STATE_READY | 0               |
|   293     |    16    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | CLK_STATE_READY | 153846153       |
|   293     |    17    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | CLK_STATE_READY | 100000000       |
|   293     |    18    | DEV_SERDES_16G1_IP2_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    19    | DEV_SERDES_16G1_IP1_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    20    | DEV_SERDES_16G1_IP4_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    21    | DEV_SERDES_16G1_IP3_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    22    | DEV_SERDES_16G1_IP3_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    23    | DEV_SERDES_16G1_IP1_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    24    | DEV_SERDES_16G1_IP2_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    25    | DEV_SERDES_16G1_IP2_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    26    | DEV_SERDES_16G1_REF_DER_OUT_CLK                                        | CLK_STATE_READY | 0               |
|   293     |    27    | DEV_SERDES_16G1_IP1_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    28    | DEV_SERDES_16G1_IP3_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    29    | DEV_SERDES_16G1_IP1_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    30    | DEV_SERDES_16G1_IP1_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    31    | DEV_SERDES_16G1_IP4_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    32    | DEV_SERDES_16G1_IP3_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    33    | DEV_SERDES_16G1_IP4_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    34    | DEV_SERDES_16G1_IP3_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    35    | DEV_SERDES_16G1_IP4_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    36    | DEV_SERDES_16G1_IP2_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    37    | DEV_SERDES_16G1_IP2_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    38    | DEV_SERDES_16G1_IP1_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    39    | DEV_SERDES_16G1_REF_OUT_CLK                                            | CLK_STATE_READY | 0               |
|   293     |    40    | DEV_SERDES_16G1_REF1_OUT_CLK                                           | CLK_STATE_READY | 0               |
|   293     |    41    | DEV_SERDES_16G1_IP4_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    42    | DEV_SERDES_16G1_IP1_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    43    | DEV_SERDES_16G1_IP1_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    44    | DEV_SERDES_16G1_IP4_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    45    | DEV_SERDES_16G1_IP4_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    46    | DEV_SERDES_16G1_IP2_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    47    | DEV_SERDES_16G1_IP2_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    48    | DEV_SERDES_16G1_IP4_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    49    | DEV_SERDES_16G1_IP2_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    50    | DEV_SERDES_16G1_IP2_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    51    | DEV_SERDES_16G1_IP1_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    52    | DEV_SERDES_16G1_IP2_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    53    | DEV_SERDES_16G1_IP4_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    54    | DEV_SERDES_16G1_IP1_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    55    | DEV_SERDES_16G1_IP4_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    60    | DEV_SERDES_16G1_CMN_REFCLK1_M                                          | CLK_STATE_READY | 0               |
|   293     |    67    | DEV_SERDES_16G1_CMN_REFCLK1_P                                          | CLK_STATE_READY | 0               |
|-----------------------------------------------------------------------------------------------------------------------------------|

root@j721e-evm:~#

Hi,

From the register dump, SerDes Lane0 is not used.
root@j721e-evm:~# devmem2 0x00104090
/dev/mem opened.
Memory mapped at address 0xffffaee1b000.
Read at address  0x00104090 (0xffffaee1b090): 0x00000003

0 ->  Q/SGMII Lane3 (Port-3 of CPSW)
1 ->  PCIe0 lane0
2/3 -? IP not used

Please check serdes_ln_ctrl configuration and use proper values.
You suppose to use {J721E_SERDES1_LANE0_QSGMII_LANE3, J721E_SERDES1_LANE1_QSGMII_LANE4} for using CPSW Port-3 & Port-4.

Refer to TRM & SDK/board-support/ti-linux-kernel-6.6.32+git-ti/include/dt-bindings/mux/ti-serdes.h for SerDes lane configuration.


Please check once with above changes.

Best Regards,
Sudheer

My current configuration is as follows:

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_QSGMII_LANE1>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
		      <J721E_SERDES1_LANE0_QSGMII_LANE3>, <J721E_SERDES1_LANE1_QSGMII_LANE4>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

log:

root@j721e-evm:~# dmesg | grep cdns-sierra-phy
[    2.813728] cdns-sierra-phy 5000000.serdes: Timeout waiting for PHY status ready
[    2.998722] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[    4.712734] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x00104090
/dev/mem opened.
Memory mapped at address 0xffff9e63d000.
Read at address  0x00104090 (0xffff9e63d090): 0x00000000
root@j721e-evm:~#

Hi,

Can you please check whether below changes are present in your cadence file or not? is not please integrate these changes.
3542.0001-phy-cadence-Sierra-Add-Single-link-SGMII-PHY-configu.patch

Best Regards,
Sudheer

The patch was already included in the first comment when I raised the issue,
and this is the file after I inserted the patch.
board-support/ti-linux-kernel-6.6.32+git-ti/drivers/phy/cadence/phy-cadence-sierra.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Cadence Sierra PHY Driver
 *
 * Copyright (c) 2018 Cadence Design Systems
 * Author: Alan Douglas <adouglas@cadence.com>
 *
 */
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-cadence.h>

#define NUM_SSC_MODE		3
#define NUM_PHY_TYPE		5

/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET			0x0
#define SIERRA_MACRO_ID_REG				0x0
#define SIERRA_CMN_PLLLC_GEN_PREG			0x42
#define SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG		0x43
#define SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG		0x45
#define SIERRA_CMN_PLLLC_INIT_PREG			0x46
#define SIERRA_CMN_PLLLC_ITERTMR_PREG			0x47
#define SIERRA_CMN_PLLLC_MODE_PREG			0x48
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG		0x49
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG		0x4A
#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG		0x4B
#define SIERRA_CMN_PLLLC_LOCKSEARCH_PREG		0x4C
#define SIERRA_CMN_PLLLC_CLK1_PREG			0x4D
#define SIERRA_CMN_PLLLC_CLK0_PREG			0x4E
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG		0x4F
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG		0x50
#define SIERRA_CMN_PLLLC_DSMCORR_PREG			0x51
#define SIERRA_CMN_PLLLC_SS_PREG			0x52
#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG		0x53
#define SIERRA_CMN_PLLLC_SSTWOPT_PREG			0x54
#define SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG		0x5D
#define SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG		0x5E
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG	0x62
#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG		0x63
#define SIERRA_SDOSCCAL_CLK_CNT_PREG			0x6E
#define SIERRA_CMN_REFRCV_PREG				0x98
#define SIERRA_CMN_RESCAL_CTRLA_PREG			0xA0
#define SIERRA_CMN_REFRCV1_PREG				0xB8
#define SIERRA_CMN_PLLLC1_GEN_PREG			0xC2
#define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG		0xC3
#define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG		0xC5
#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG		0xCA
#define SIERRA_CMN_PLLLC1_CLK0_PREG			0xCE
#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG		0xD0
#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG	0xE2

#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\
				((0x4000 << (block_offset)) + \
				 (((ln) << 9) << (reg_offset)))

#define SIERRA_DET_STANDEC_A_PREG			0x000
#define SIERRA_DET_STANDEC_B_PREG			0x001
#define SIERRA_DET_STANDEC_C_PREG			0x002
#define SIERRA_DET_STANDEC_D_PREG			0x003
#define SIERRA_DET_STANDEC_E_PREG			0x004
#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG		0x008
#define SIERRA_PSM_A0IN_TMR_PREG			0x009
#define SIERRA_PSM_A3IN_TMR_PREG			0x00C
#define SIERRA_PSM_DIAG_PREG				0x015
#define SIERRA_PSC_LN_A3_PREG				0x023
#define SIERRA_PSC_LN_A4_PREG				0x024
#define SIERRA_PSC_LN_IDLE_PREG				0x026
#define SIERRA_PSC_TX_A0_PREG				0x028
#define SIERRA_PSC_TX_A1_PREG				0x029
#define SIERRA_PSC_TX_A2_PREG				0x02A
#define SIERRA_PSC_TX_A3_PREG				0x02B
#define SIERRA_PSC_RX_A0_PREG				0x030
#define SIERRA_PSC_RX_A1_PREG				0x031
#define SIERRA_PSC_RX_A2_PREG				0x032
#define SIERRA_PSC_RX_A3_PREG				0x033
#define SIERRA_PLLCTRL_FBDIV_MODE01_PREG		0x039
#define SIERRA_PLLCTRL_SUBRATE_PREG			0x03A
#define SIERRA_PLLCTRL_GEN_A_PREG			0x03B
#define SIERRA_PLLCTRL_GEN_D_PREG			0x03E
#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG			0x03F
#define SIERRA_PLLCTRL_STATUS_PREG			0x044
#define SIERRA_CLKPATH_BIASTRIM_PREG			0x04B
#define SIERRA_DFE_BIASTRIM_PREG			0x04C
#define SIERRA_DRVCTRL_ATTEN_PREG			0x06A
#define SIERRA_DRVCTRL_BOOST_PREG			0x06F
#define SIERRA_LANE_TX_RECEIVER_DETECT_PREG		0x071
#define SIERRA_TX_RCVDET_OVRD_PREG			0x072
#define SIERRA_CLKPATHCTRL_TMR_PREG			0x081
#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG		0x085
#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG		0x086
#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG		0x087
#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG		0x088
#define SIERRA_CREQ_DCBIASATTEN_OVR_PREG		0x08C
#define SIERRA_CREQ_CCLKDET_MODE01_PREG			0x08E
#define SIERRA_RX_CTLE_CAL_PREG				0x08F
#define SIERRA_RX_CTLE_MAINTENANCE_PREG			0x091
#define SIERRA_CREQ_FSMCLK_SEL_PREG			0x092
#define SIERRA_CREQ_EQ_CTRL_PREG			0x093
#define SIERRA_CREQ_SPARE_PREG				0x096
#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG		0x097
#define SIERRA_CTLELUT_CTRL_PREG			0x098
#define SIERRA_DEQ_BLK_TAU_CTRL1_PREG			0x0AC
#define SIERRA_DEQ_BLK_TAU_CTRL4_PREG			0x0AF
#define SIERRA_DFE_ECMP_RATESEL_PREG			0x0C0
#define SIERRA_DFE_SMP_RATESEL_PREG			0x0C1
#define SIERRA_DEQ_PHALIGN_CTRL				0x0C4
#define SIERRA_DEQ_CONCUR_CTRL1_PREG			0x0C8
#define SIERRA_DEQ_CONCUR_CTRL2_PREG			0x0C9
#define SIERRA_DEQ_EPIPWR_CTRL2_PREG			0x0CD
#define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG		0x0CE
#define SIERRA_DEQ_ERRCMP_CTRL_PREG			0x0D0
#define SIERRA_DEQ_OFFSET_CTRL_PREG			0x0D8
#define SIERRA_DEQ_GAIN_CTRL_PREG			0x0E0
#define SIERRA_DEQ_VGATUNE_CTRL_PREG			0x0E1
#define SIERRA_DEQ_GLUT0				0x0E8
#define SIERRA_DEQ_GLUT1				0x0E9
#define SIERRA_DEQ_GLUT2				0x0EA
#define SIERRA_DEQ_GLUT3				0x0EB
#define SIERRA_DEQ_GLUT4				0x0EC
#define SIERRA_DEQ_GLUT5				0x0ED
#define SIERRA_DEQ_GLUT6				0x0EE
#define SIERRA_DEQ_GLUT7				0x0EF
#define SIERRA_DEQ_GLUT8				0x0F0
#define SIERRA_DEQ_GLUT9				0x0F1
#define SIERRA_DEQ_GLUT10				0x0F2
#define SIERRA_DEQ_GLUT11				0x0F3
#define SIERRA_DEQ_GLUT12				0x0F4
#define SIERRA_DEQ_GLUT13				0x0F5
#define SIERRA_DEQ_GLUT14				0x0F6
#define SIERRA_DEQ_GLUT15				0x0F7
#define SIERRA_DEQ_GLUT16				0x0F8
#define SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG		0x0F9
#define SIERRA_TAU_EN_CEPH2TO0_PREG			0x0FB
#define SIERRA_TAU_EN_CEPH5TO3_PREG			0x0FC
#define SIERRA_DEQ_ALUT0				0x108
#define SIERRA_DEQ_ALUT1				0x109
#define SIERRA_DEQ_ALUT2				0x10A
#define SIERRA_DEQ_ALUT3				0x10B
#define SIERRA_DEQ_ALUT4				0x10C
#define SIERRA_DEQ_ALUT5				0x10D
#define SIERRA_DEQ_ALUT6				0x10E
#define SIERRA_DEQ_ALUT7				0x10F
#define SIERRA_DEQ_ALUT8				0x110
#define SIERRA_DEQ_ALUT9				0x111
#define SIERRA_DEQ_ALUT10				0x112
#define SIERRA_DEQ_ALUT11				0x113
#define SIERRA_DEQ_ALUT12				0x114
#define SIERRA_DEQ_ALUT13				0x115
#define SIERRA_OEPH_EN_CTRL_PREG			0x124
#define SIERRA_DEQ_DFETAP_CTRL_PREG			0x128
#define SIERRA_DEQ_DFETAP0				0x129
#define SIERRA_DEQ_DFETAP1				0x12B
#define SIERRA_DEQ_DFETAP2				0x12D
#define SIERRA_DEQ_DFETAP3				0x12F
#define SIERRA_DEQ_DFETAP4				0x131
#define SIERRA_DFE_EN_1010_IGNORE_PREG			0x134
#define SIERRA_DEQ_PRECUR_PREG				0x138
#define SIERRA_DEQ_POSTCUR_PREG				0x140
#define SIERRA_DEQ_POSTCUR_DECR_PREG			0x142
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150
#define SIERRA_DEQ_TAU_CTRL2_PREG			0x151
#define SIERRA_DEQ_TAU_CTRL3_PREG			0x152
#define SIERRA_DEQ_OPENEYE_CTRL_PREG			0x158
#define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG		0x159
#define SIERRA_DEQ_PICTRL_PREG				0x161
#define SIERRA_CPICAL_TMRVAL_MODE1_PREG			0x170
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG			0x171
#define SIERRA_CPICAL_PICNT_MODE1_PREG			0x174
#define SIERRA_CPI_OUTBUF_RATESEL_PREG			0x17C
#define SIERRA_CPI_RESBIAS_BIN_PREG			0x17E
#define SIERRA_CPI_TRIM_PREG				0x17F
#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG		0x183
#define SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG		0x184
#define SIERRA_EPI_CTRL_PREG				0x187
#define SIERRA_LFPSDET_SUPPORT_PREG			0x188
#define SIERRA_LFPSFILT_NS_PREG				0x18A
#define SIERRA_LFPSFILT_RD_PREG				0x18B
#define SIERRA_LFPSFILT_MP_PREG				0x18C
#define SIERRA_SIGDET_SUPPORT_PREG			0x190
#define SIERRA_SDFILT_H2L_A_PREG			0x191
#define SIERRA_SDFILT_L2H_PREG				0x193
#define SIERRA_RXBUFFER_CTLECTRL_PREG			0x19E
#define SIERRA_RXBUFFER_RCDFECTRL_PREG			0x19F
#define SIERRA_RXBUFFER_DFECTRL_PREG			0x1A0
#define SIERRA_LN_SPARE_REG_PREG			0x1B0
#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG		0x14F
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150

/* PHY PCS common registers */
#define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset)	\
				     (0xc000 << (block_offset))
#define SIERRA_PHY_PIPE_CMN_CTRL1			0x0
#define SIERRA_PHY_PLL_CFG				0xe

/* PHY PCS lane registers */
#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\
				       ((0xD000 << (block_offset)) +	\
				       (((ln) << 8) << (reg_offset)))

#define SIERRA_PHY_ISO_LINK_CTRL			0xB

/* PHY PMA common registers */
#define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset)	\
				     (0xE000 << (block_offset))
#define SIERRA_PHY_PMA_CMN_CTRL				0x000

/* PHY PMA lane registers */
#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\
				       ((0xF000 << (block_offset)) +	\
				       (((ln) << 8) << (reg_offset)))

#define SIERRA_PHY_PMA_XCVR_CTRL			0x000

#define SIERRA_MACRO_ID					0x00007364
#define SIERRA_MAX_LANES				16
#define PLL_LOCK_TIME					100000

#define CDNS_SIERRA_OUTPUT_CLOCKS			3
#define CDNS_SIERRA_INPUT_CLOCKS			3
enum cdns_sierra_clock_input {
	PHY_CLK,
	CMN_REFCLK_DIG_DIV,
	CMN_REFCLK1_DIG_DIV,
};

#define SIERRA_NUM_CMN_PLLC				2
#define SIERRA_NUM_CMN_PLLC_PARENTS			2

static const struct reg_field macro_id_type =
				REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
				REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
static const struct reg_field pma_cmn_ready =
				REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
static const struct reg_field pllctrl_lock =
				REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
static const struct reg_field phy_iso_link_ctrl_1 =
				REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);
static const struct reg_field cmn_plllc_clk1outdiv_preg =
				REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6);
static const struct reg_field cmn_plllc_clk1_en_preg =
				REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12);

static const char * const clk_names[] = {
	[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
	[CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
	[CDNS_SIERRA_DERIVED_REFCLK] = "refclk_der",
};

enum cdns_sierra_cmn_plllc {
	CMN_PLLLC,
	CMN_PLLLC1,
};

struct cdns_sierra_pll_mux_reg_fields {
	struct reg_field	pfdclk_sel_preg;
	struct reg_field	plllc1en_field;
	struct reg_field	termen_field;
};

static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = {
	[CMN_PLLLC] = {
		.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
		.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
		.termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
	},
	[CMN_PLLLC1] = {
		.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
		.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
		.termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
	},
};

struct cdns_sierra_pll_mux {
	struct clk_hw		hw;
	struct regmap_field	*pfdclk_sel_preg;
	struct regmap_field	*plllc1en_field;
	struct regmap_field	*termen_field;
	struct clk_init_data	clk_data;
};

#define to_cdns_sierra_pll_mux(_hw)	\
			container_of(_hw, struct cdns_sierra_pll_mux, hw)

#define PLL0_REFCLK_NAME "pll0_refclk"
#define PLL1_REFCLK_NAME "pll1_refclk"

static const struct clk_parent_data pll_mux_parent_data[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
	[CMN_PLLLC] = {
		{ .fw_name = PLL0_REFCLK_NAME },
		{ .fw_name = PLL1_REFCLK_NAME }
	},
	[CMN_PLLLC1] = {
		{ .fw_name = PLL1_REFCLK_NAME },
		{ .fw_name = PLL0_REFCLK_NAME }
	},
};

static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
	[CMN_PLLLC] = { 0, 1 },
	[CMN_PLLLC1] = { 1, 0 },
};

struct cdns_sierra_derived_refclk {
	struct clk_hw           hw;
	struct regmap_field     *cmn_plllc_clk1outdiv_preg;
	struct regmap_field     *cmn_plllc_clk1_en_preg;
	struct clk_init_data	clk_data;
};

#define to_cdns_sierra_derived_refclk(_hw)	\
			container_of(_hw, struct cdns_sierra_derived_refclk, hw)

enum cdns_sierra_phy_type {
	TYPE_NONE,
	TYPE_PCIE,
	TYPE_USB,
	TYPE_SGMII,
	TYPE_QSGMII
};

enum cdns_sierra_ssc_mode {
	NO_SSC,
	EXTERNAL_SSC,
	INTERNAL_SSC
};

struct cdns_sierra_inst {
	struct phy *phy;
	enum cdns_sierra_phy_type phy_type;
	u32 num_lanes;
	u32 mlane;
	struct reset_control *lnk_rst;
	enum cdns_sierra_ssc_mode ssc_mode;
};

struct cdns_reg_pairs {
	u16 val;
	u32 off;
};

struct cdns_sierra_vals {
	const struct cdns_reg_pairs *reg_pairs;
	u32 num_regs;
};

struct cdns_sierra_data {
	u32 id_value;
	u8 block_offset_shift;
	u8 reg_offset_shift;
	struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
					     [NUM_SSC_MODE];
	struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
						[NUM_SSC_MODE];
	struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
					     [NUM_SSC_MODE];
	struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
					    [NUM_SSC_MODE];
};

struct cdns_regmap_cdb_context {
	struct device *dev;
	void __iomem *base;
	u8 reg_offset_shift;
};

struct cdns_sierra_phy {
	struct device *dev;
	const struct cdns_sierra_data *init_data;
	struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
	struct reset_control *phy_rst;
	struct reset_control *apb_rst;
	struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
	struct regmap *regmap_phy_pcs_common_cdb;
	struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
	struct regmap *regmap_phy_pma_common_cdb;
	struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES];
	struct regmap *regmap_common_cdb;
	struct regmap_field *macro_id_type;
	struct regmap_field *phy_pll_cfg_1;
	struct regmap_field *pma_cmn_ready;
	struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
	struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES];
	struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
	struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
	struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
	struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
	int nsubnodes;
	u32 num_lanes;
	bool autoconf;
	int already_configured;
	struct clk *pll_clks[SIERRA_NUM_CMN_PLLC];
	struct clk_hw_onecell_data clk_data;
};

static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
{
	struct cdns_regmap_cdb_context *ctx = context;
	u32 offset = reg << ctx->reg_offset_shift;

	writew(val, ctx->base + offset);

	return 0;
}

static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
{
	struct cdns_regmap_cdb_context *ctx = context;
	u32 offset = reg << ctx->reg_offset_shift;

	*val = readw(ctx->base + offset);
	return 0;
}

#define SIERRA_LANE_CDB_REGMAP_CONF(n) \
{ \
	.name = "sierra_lane" n "_cdb", \
	.reg_stride = 1, \
	.fast_io = true, \
	.reg_write = cdns_regmap_write, \
	.reg_read = cdns_regmap_read, \
}

static const struct regmap_config cdns_sierra_lane_cdb_config[] = {
	SIERRA_LANE_CDB_REGMAP_CONF("0"),
	SIERRA_LANE_CDB_REGMAP_CONF("1"),
	SIERRA_LANE_CDB_REGMAP_CONF("2"),
	SIERRA_LANE_CDB_REGMAP_CONF("3"),
	SIERRA_LANE_CDB_REGMAP_CONF("4"),
	SIERRA_LANE_CDB_REGMAP_CONF("5"),
	SIERRA_LANE_CDB_REGMAP_CONF("6"),
	SIERRA_LANE_CDB_REGMAP_CONF("7"),
	SIERRA_LANE_CDB_REGMAP_CONF("8"),
	SIERRA_LANE_CDB_REGMAP_CONF("9"),
	SIERRA_LANE_CDB_REGMAP_CONF("10"),
	SIERRA_LANE_CDB_REGMAP_CONF("11"),
	SIERRA_LANE_CDB_REGMAP_CONF("12"),
	SIERRA_LANE_CDB_REGMAP_CONF("13"),
	SIERRA_LANE_CDB_REGMAP_CONF("14"),
	SIERRA_LANE_CDB_REGMAP_CONF("15"),
};

static const struct regmap_config cdns_sierra_common_cdb_config = {
	.name = "sierra_common_cdb",
	.reg_stride = 1,
	.fast_io = true,
	.reg_write = cdns_regmap_write,
	.reg_read = cdns_regmap_read,
};

static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = {
	.name = "sierra_phy_pcs_cmn_cdb",
	.reg_stride = 1,
	.fast_io = true,
	.reg_write = cdns_regmap_write,
	.reg_read = cdns_regmap_read,
};

#define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
{ \
	.name = "sierra_phy_pcs_lane" n "_cdb", \
	.reg_stride = 1, \
	.fast_io = true, \
	.reg_write = cdns_regmap_write, \
	.reg_read = cdns_regmap_read, \
}

static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = {
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("4"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("5"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("6"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("7"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("8"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("9"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("10"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("11"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("12"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("13"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("14"),
	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("15"),
};

static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = {
	.name = "sierra_phy_pma_cmn_cdb",
	.reg_stride = 1,
	.fast_io = true,
	.reg_write = cdns_regmap_write,
	.reg_read = cdns_regmap_read,
};

#define SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF(n) \
{ \
	.name = "sierra_phy_pma_lane" n "_cdb", \
	.reg_stride = 1, \
	.fast_io = true, \
	.reg_write = cdns_regmap_write, \
	.reg_read = cdns_regmap_read, \
}

static const struct regmap_config cdns_sierra_phy_pma_lane_cdb_config[] = {
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("0"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("1"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("2"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("3"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("4"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("5"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("6"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("7"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("8"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("9"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("10"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("11"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("12"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("13"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("14"),
	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("15"),
};

static int cdns_sierra_phy_init(struct phy *gphy)
{
	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
	struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);
	const struct cdns_sierra_data *init_data = phy->init_data;
	struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
	enum cdns_sierra_phy_type phy_type = ins->phy_type;
	enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
	struct cdns_sierra_vals *phy_pma_ln_vals;
	const struct cdns_reg_pairs *reg_pairs;
	struct cdns_sierra_vals *pcs_cmn_vals;
	struct regmap *regmap;
	u32 num_regs;
	int i, j;

	/* Initialise the PHY registers, unless auto configured */
	if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1)
		return 0;

	clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
	clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);

	 /* Spread spectrum generation is not required or supported for SGMII */
	if (phy_type == TYPE_SGMII)
		ssc = NO_SSC;

	/* PHY PCS common registers configurations */
	pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
	if (pcs_cmn_vals) {
		reg_pairs = pcs_cmn_vals->reg_pairs;
		num_regs = pcs_cmn_vals->num_regs;
		regmap = phy->regmap_phy_pcs_common_cdb;
		for (i = 0; i < num_regs; i++)
			regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
	}

	/* PHY PMA lane registers configurations */
	phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc];
	if (phy_pma_ln_vals) {
		reg_pairs = phy_pma_ln_vals->reg_pairs;
		num_regs = phy_pma_ln_vals->num_regs;
		for (i = 0; i < ins->num_lanes; i++) {
			regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane];
			for (j = 0; j < num_regs; j++)
				regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
		}
	}

	/* PMA common registers configurations */
	pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
	if (pma_cmn_vals) {
		reg_pairs = pma_cmn_vals->reg_pairs;
		num_regs = pma_cmn_vals->num_regs;
		regmap = phy->regmap_common_cdb;
		for (i = 0; i < num_regs; i++)
			regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
	}

	/* PMA lane registers configurations */
	pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
	if (pma_ln_vals) {
		reg_pairs = pma_ln_vals->reg_pairs;
		num_regs = pma_ln_vals->num_regs;
		for (i = 0; i < ins->num_lanes; i++) {
			regmap = phy->regmap_lane_cdb[i + ins->mlane];
			for (j = 0; j < num_regs; j++)
				regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
		}
	}

	return 0;
}

static int cdns_sierra_phy_on(struct phy *gphy)
{
	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
	struct device *dev = sp->dev;
	u32 val;
	int ret;

	if (sp->nsubnodes == 1) {
		/* Take the PHY out of reset */
		ret = reset_control_deassert(sp->phy_rst);
		if (ret) {
			dev_err(dev, "Failed to take the PHY out of reset\n");
			return ret;
		}
	}

	/* Take the PHY lane group out of reset */
	ret = reset_control_deassert(ins->lnk_rst);
	if (ret) {
		dev_err(dev, "Failed to take the PHY lane out of reset\n");
		return ret;
	}

	if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) {
		ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane],
						     val, !val, 1000, PLL_LOCK_TIME);
		if (ret) {
			dev_err(dev, "Timeout waiting for PHY status ready\n");
			return ret;
		}
	}

	/*
	 * Wait for cmn_ready assertion
	 * PHY_PMA_CMN_CTRL[0] == 1
	 */
	ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val,
					     1000, PLL_LOCK_TIME);
	if (ret) {
		dev_err(dev, "Timeout waiting for CMN ready\n");
		return ret;
	}

	ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
					     val, val, 1000, PLL_LOCK_TIME);
	if (ret < 0)
		dev_err(dev, "PLL lock of lane failed\n");

	return ret;
}

static int cdns_sierra_phy_off(struct phy *gphy)
{
	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);

	return reset_control_assert(ins->lnk_rst);
}

static int cdns_sierra_phy_reset(struct phy *gphy)
{
	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);

	reset_control_assert(sp->phy_rst);
	reset_control_deassert(sp->phy_rst);
	return 0;
};

static const struct phy_ops ops = {
	.init		= cdns_sierra_phy_init,
	.power_on	= cdns_sierra_phy_on,
	.power_off	= cdns_sierra_phy_off,
	.reset		= cdns_sierra_phy_reset,
	.owner		= THIS_MODULE,
};

static int cdns_sierra_noop_phy_on(struct phy *gphy)
{
	usleep_range(5000, 10000);

	return 0;
}

static const struct phy_ops noop_ops = {
	.power_on	= cdns_sierra_noop_phy_on,
	.owner		= THIS_MODULE,
};

static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)
{
	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
	struct regmap_field *plllc1en_field = mux->plllc1en_field;
	struct regmap_field *termen_field = mux->termen_field;
	struct regmap_field *field = mux->pfdclk_sel_preg;
	unsigned int val;
	int index;

	regmap_field_read(field, &val);

	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) {
		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val);
		if (index == 1) {
			regmap_field_write(plllc1en_field, 1);
			regmap_field_write(termen_field, 1);
		}
	} else {
		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val);
	}

	return index;
}

static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index)
{
	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
	struct regmap_field *plllc1en_field = mux->plllc1en_field;
	struct regmap_field *termen_field = mux->termen_field;
	struct regmap_field *field = mux->pfdclk_sel_preg;
	int val, ret;

	ret = regmap_field_write(plllc1en_field, 0);
	ret |= regmap_field_write(termen_field, 0);
	if (index == 1) {
		ret |= regmap_field_write(plllc1en_field, 1);
		ret |= regmap_field_write(termen_field, 1);
	}

	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1]))
		val = cdns_sierra_pll_mux_table[CMN_PLLLC1][index];
	else
		val = cdns_sierra_pll_mux_table[CMN_PLLLC][index];

	ret |= regmap_field_write(field, val);

	return ret;
}

static const struct clk_ops cdns_sierra_pll_mux_ops = {
	.determine_rate = __clk_mux_determine_rate,
	.set_parent = cdns_sierra_pll_mux_set_parent,
	.get_parent = cdns_sierra_pll_mux_get_parent,
};

static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp,
					struct regmap_field *pfdclk1_sel_field,
					struct regmap_field *plllc1en_field,
					struct regmap_field *termen_field,
					int clk_index)
{
	struct cdns_sierra_pll_mux *mux;
	struct device *dev = sp->dev;
	struct clk_init_data *init;
	char clk_name[100];
	int ret;

	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
	if (!mux)
		return -ENOMEM;

	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]);

	init = &mux->clk_data;

	init->ops = &cdns_sierra_pll_mux_ops;
	init->flags = CLK_SET_RATE_NO_REPARENT;
	init->parent_data = pll_mux_parent_data[clk_index];
	init->num_parents = SIERRA_NUM_CMN_PLLC_PARENTS;
	init->name = clk_name;

	mux->pfdclk_sel_preg = pfdclk1_sel_field;
	mux->plllc1en_field = plllc1en_field;
	mux->termen_field = termen_field;
	mux->hw.init = init;

	ret = devm_clk_hw_register(dev, &mux->hw);
	if (ret)
		return ret;

	sp->clk_data.hws[clk_index] = &mux->hw;

	sp->pll_clks[clk_index] = devm_clk_hw_get_clk(dev, &mux->hw,
						      clk_names[clk_index]);

	return 0;
}

static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp)
{
	struct regmap_field *pfdclk1_sel_field;
	struct regmap_field *plllc1en_field;
	struct regmap_field *termen_field;
	struct device *dev = sp->dev;
	int ret = 0, i, clk_index;

	clk_index = CDNS_SIERRA_PLL_CMNLC;
	for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) {
		pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i];
		plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i];
		termen_field = sp->cmn_refrcv_refclk_termen_preg[i];

		ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field,
						   termen_field, clk_index);
		if (ret) {
			dev_err(dev, "Fail to register cmn plllc mux\n");
			return ret;
		}
	}

	return 0;
}

static int cdns_sierra_derived_refclk_enable(struct clk_hw *hw)
{
	struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);

	regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0x1);

	/* Programming to get 100Mhz clock output in ref_der_clk_out 5GHz VCO/50 = 100MHz */
	regmap_field_write(derived_refclk->cmn_plllc_clk1outdiv_preg, 0x2E);

	return 0;
}

static void cdns_sierra_derived_refclk_disable(struct clk_hw *hw)
{
	struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);

	regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0);
}

static int cdns_sierra_derived_refclk_is_enabled(struct clk_hw *hw)
{
	struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);
	int val;

	regmap_field_read(derived_refclk->cmn_plllc_clk1_en_preg, &val);

	return !!val;
}

static const struct clk_ops cdns_sierra_derived_refclk_ops = {
	.enable = cdns_sierra_derived_refclk_enable,
	.disable = cdns_sierra_derived_refclk_disable,
	.is_enabled = cdns_sierra_derived_refclk_is_enabled,
};

static int cdns_sierra_derived_refclk_register(struct cdns_sierra_phy *sp)
{
	struct cdns_sierra_derived_refclk *derived_refclk;
	struct device *dev = sp->dev;
	struct regmap_field *field;
	struct clk_init_data *init;
	struct regmap *regmap;
	char clk_name[100];
	int ret;

	derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
	if (!derived_refclk)
		return -ENOMEM;

	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
		 clk_names[CDNS_SIERRA_DERIVED_REFCLK]);

	init = &derived_refclk->clk_data;

	init->ops = &cdns_sierra_derived_refclk_ops;
	init->flags = 0;
	init->name = clk_name;

	regmap = sp->regmap_common_cdb;

	field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1outdiv_preg);
	if (IS_ERR(field)) {
		dev_err(dev, "cmn_plllc_clk1outdiv_preg reg field init failed\n");
		return PTR_ERR(field);
	}
	derived_refclk->cmn_plllc_clk1outdiv_preg = field;

	field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1_en_preg);
	if (IS_ERR(field)) {
		dev_err(dev, "cmn_plllc_clk1_en_preg reg field init failed\n");
		return PTR_ERR(field);
	}
	derived_refclk->cmn_plllc_clk1_en_preg = field;

	derived_refclk->hw.init = init;

	ret = devm_clk_hw_register(dev, &derived_refclk->hw);
	if (ret)
		return ret;

	sp->clk_data.hws[CDNS_SIERRA_DERIVED_REFCLK] = &derived_refclk->hw;

	return 0;
}

static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp)
{
	struct device *dev = sp->dev;
	struct device_node *node = dev->of_node;

	of_clk_del_provider(node);
}

static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp)
{
	struct device *dev = sp->dev;
	struct device_node *node = dev->of_node;
	int ret;

	ret = cdns_sierra_phy_register_pll_mux(sp);
	if (ret) {
		dev_err(dev, "Failed to pll mux clocks\n");
		return ret;
	}

	ret = cdns_sierra_derived_refclk_register(sp);
	if (ret) {
		dev_err(dev, "Failed to register derived refclk\n");
		return ret;
	}

	sp->clk_data.num = CDNS_SIERRA_OUTPUT_CLOCKS;
	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
				     &sp->clk_data);
	if (ret)
		dev_err(dev, "Failed to add clock provider: %s\n", node->name);

	return ret;
}

static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
				    struct device_node *child)
{
	u32 phy_type;

	if (of_property_read_u32(child, "reg", &inst->mlane))
		return -EINVAL;

	if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
		return -EINVAL;

	if (of_property_read_u32(child, "cdns,phy-type", &phy_type))
		return -EINVAL;

	switch (phy_type) {
	case PHY_TYPE_PCIE:
		inst->phy_type = TYPE_PCIE;
		break;
	case PHY_TYPE_USB3:
		inst->phy_type = TYPE_USB;
		break;
	case PHY_TYPE_SGMII:
		inst->phy_type = TYPE_SGMII;
		break;
	case PHY_TYPE_QSGMII:
		inst->phy_type = TYPE_QSGMII;
		break;
	default:
		return -EINVAL;
	}

	inst->ssc_mode = EXTERNAL_SSC;
	of_property_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode);

	return 0;
}

static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
				       u32 block_offset, u8 reg_offset_shift,
				       const struct regmap_config *config)
{
	struct cdns_regmap_cdb_context *ctx;

	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return ERR_PTR(-ENOMEM);

	ctx->dev = dev;
	ctx->base = base + block_offset;
	ctx->reg_offset_shift = reg_offset_shift;

	return devm_regmap_init(dev, NULL, ctx, config);
}

static int cdns_regfield_init(struct cdns_sierra_phy *sp)
{
	struct device *dev = sp->dev;
	struct regmap_field *field;
	struct reg_field reg_field;
	struct regmap *regmap;
	int i;

	regmap = sp->regmap_common_cdb;
	field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
	if (IS_ERR(field)) {
		dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
		return PTR_ERR(field);
	}
	sp->macro_id_type = field;

	for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) {
		reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg;
		field = devm_regmap_field_alloc(dev, regmap, reg_field);
		if (IS_ERR(field)) {
			dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i);
			return PTR_ERR(field);
		}
		sp->cmn_plllc_pfdclk1_sel_preg[i] = field;

		reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field;
		field = devm_regmap_field_alloc(dev, regmap, reg_field);
		if (IS_ERR(field)) {
			dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i);
			return PTR_ERR(field);
		}
		sp->cmn_refrcv_refclk_plllc1en_preg[i] = field;

		reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field;
		field = devm_regmap_field_alloc(dev, regmap, reg_field);
		if (IS_ERR(field)) {
			dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i);
			return PTR_ERR(field);
		}
		sp->cmn_refrcv_refclk_termen_preg[i] = field;
	}

	regmap = sp->regmap_phy_pcs_common_cdb;
	field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
	if (IS_ERR(field)) {
		dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
		return PTR_ERR(field);
	}
	sp->phy_pll_cfg_1 = field;

	regmap = sp->regmap_phy_pma_common_cdb;
	field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready);
	if (IS_ERR(field)) {
		dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n");
		return PTR_ERR(field);
	}
	sp->pma_cmn_ready = field;

	for (i = 0; i < SIERRA_MAX_LANES; i++) {
		regmap = sp->regmap_lane_cdb[i];
		field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
		if (IS_ERR(field)) {
			dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
			return PTR_ERR(field);
		}
		sp->pllctrl_lock[i] = field;
	}

	for (i = 0; i < SIERRA_MAX_LANES; i++) {
		regmap = sp->regmap_phy_pcs_lane_cdb[i];
		field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1);
		if (IS_ERR(field)) {
			dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i);
			return PTR_ERR(field);
		}
		sp->phy_iso_link_ctrl_1[i] = field;
	}

	return 0;
}

static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
				   void __iomem *base, u8 block_offset_shift,
				   u8 reg_offset_shift)
{
	struct device *dev = sp->dev;
	struct regmap *regmap;
	u32 block_offset;
	int i;

	for (i = 0; i < SIERRA_MAX_LANES; i++) {
		block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift,
						      reg_offset_shift);
		regmap = cdns_regmap_init(dev, base, block_offset,
					  reg_offset_shift,
					  &cdns_sierra_lane_cdb_config[i]);
		if (IS_ERR(regmap)) {
			dev_err(dev, "Failed to init lane CDB regmap\n");
			return PTR_ERR(regmap);
		}
		sp->regmap_lane_cdb[i] = regmap;
	}

	regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
				  reg_offset_shift,
				  &cdns_sierra_common_cdb_config);
	if (IS_ERR(regmap)) {
		dev_err(dev, "Failed to init common CDB regmap\n");
		return PTR_ERR(regmap);
	}
	sp->regmap_common_cdb = regmap;

	block_offset = SIERRA_PHY_PCS_COMMON_OFFSET(block_offset_shift);
	regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
				  &cdns_sierra_phy_pcs_cmn_cdb_config);
	if (IS_ERR(regmap)) {
		dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
		return PTR_ERR(regmap);
	}
	sp->regmap_phy_pcs_common_cdb = regmap;

	for (i = 0; i < SIERRA_MAX_LANES; i++) {
		block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
							      reg_offset_shift);
		regmap = cdns_regmap_init(dev, base, block_offset,
					  reg_offset_shift,
					  &cdns_sierra_phy_pcs_lane_cdb_config[i]);
		if (IS_ERR(regmap)) {
			dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
			return PTR_ERR(regmap);
		}
		sp->regmap_phy_pcs_lane_cdb[i] = regmap;
	}

	block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift);
	regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
				  &cdns_sierra_phy_pma_cmn_cdb_config);
	if (IS_ERR(regmap)) {
		dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
		return PTR_ERR(regmap);
	}
	sp->regmap_phy_pma_common_cdb = regmap;

	for (i = 0; i < SIERRA_MAX_LANES; i++) {
		block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, block_offset_shift,
							      reg_offset_shift);
		regmap = cdns_regmap_init(dev, base, block_offset,
					  reg_offset_shift,
					  &cdns_sierra_phy_pma_lane_cdb_config[i]);
		if (IS_ERR(regmap)) {
			dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n");
			return PTR_ERR(regmap);
		}
		sp->regmap_phy_pma_lane_cdb[i] = regmap;
	}

	return 0;
}

static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
				      struct device *dev)
{
	struct clk *clk;
	int ret;

	clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
	if (IS_ERR(clk)) {
		dev_err(dev, "cmn_refclk_dig_div clock not found\n");
		ret = PTR_ERR(clk);
		return ret;
	}
	sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;

	clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
	if (IS_ERR(clk)) {
		dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
		ret = PTR_ERR(clk);
		return ret;
	}
	sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;

	return 0;
}

static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp)
{
	struct device *dev = sp->dev;
	struct clk *clk;
	int ret;

	clk = devm_clk_get_optional(dev, "phy_clk");
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get clock phy_clk\n");
		return PTR_ERR(clk);
	}
	sp->input_clks[PHY_CLK] = clk;

	ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
	if (ret)
		return ret;

	return 0;
}

static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)
{
	int ret;

	ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]);
	if (ret)
		return ret;

	ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]);
	if (ret)
		goto err_pll_cmnlc1;

	return 0;

err_pll_cmnlc1:
	clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]);

	return ret;
}

static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)
{
	clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]);
	clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]);
	if (!sp->already_configured)
		clk_disable_unprepare(sp->input_clks[PHY_CLK]);
}

static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
				      struct device *dev)
{
	struct reset_control *rst;

	rst = devm_reset_control_get_exclusive(dev, "sierra_reset");
	if (IS_ERR(rst)) {
		dev_err(dev, "failed to get reset\n");
		return PTR_ERR(rst);
	}
	sp->phy_rst = rst;

	rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb");
	if (IS_ERR(rst)) {
		dev_err(dev, "failed to get apb reset\n");
		return PTR_ERR(rst);
	}
	sp->apb_rst = rst;

	return 0;
}

static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)
{
	const struct cdns_sierra_data *init_data = sp->init_data;
	struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
	enum cdns_sierra_phy_type phy_t1, phy_t2;
	struct cdns_sierra_vals *phy_pma_ln_vals;
	const struct cdns_reg_pairs *reg_pairs;
	struct cdns_sierra_vals *pcs_cmn_vals;
	int i, j, node, mlane, num_lanes, ret;
	enum cdns_sierra_ssc_mode ssc;
	struct regmap *regmap;
	u32 num_regs;

	/* Maximum 2 links (subnodes) are supported */
	if (sp->nsubnodes != 2)
		return -EINVAL;

	clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
	clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);

	/* PHY configured to use both PLL LC and LC1 */
	regmap_field_write(sp->phy_pll_cfg_1, 0x1);

	phy_t1 = sp->phys[0].phy_type;
	phy_t2 = sp->phys[1].phy_type;

	/*
	 * PHY configuration for multi-link operation is done in two steps.
	 * e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes.
	 * Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe
	 * and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below.
	 *
	 * [1] For first step, phy_t1 = TYPE_PCIE and phy_t2 = TYPE_QSGMII
	 *     So the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc].
	 *     This will configure PHY registers associated for PCIe (i.e. first protocol)
	 *     involving PLLLC registers and registers for first 2 lanes of PHY.
	 * [2] In second step, the variables phy_t1 and phy_t2 are swapped. So now,
	 *     phy_t1 = TYPE_QSGMII and phy_t2 = TYPE_PCIE. And the register values are selected as
	 *     [TYPE_QSGMII][TYPE_PCIE][ssc].
	 *     This will configure PHY registers associated for QSGMII (i.e. second protocol)
	 *     involving PLLLC1 registers and registers for other 2 lanes of PHY.
	 *
	 * This completes the PHY configuration for multilink operation. This approach enables
	 * dividing the large number of PHY register configurations into protocol specific
	 * smaller groups.
	 */
	for (node = 0; node < sp->nsubnodes; node++) {
		if (node == 1) {
			/*
			 * If first link with phy_t1 is configured, then configure the PHY for
			 * second link with phy_t2. Get the array values as [phy_t2][phy_t1][ssc].
			 */
			swap(phy_t1, phy_t2);
		}

		mlane = sp->phys[node].mlane;
		ssc = sp->phys[node].ssc_mode;
		num_lanes = sp->phys[node].num_lanes;

		/* PHY PCS common registers configurations */
		pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
		if (pcs_cmn_vals) {
			reg_pairs = pcs_cmn_vals->reg_pairs;
			num_regs = pcs_cmn_vals->num_regs;
			regmap = sp->regmap_phy_pcs_common_cdb;
			for (i = 0; i < num_regs; i++)
				regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
		}

		/* PHY PMA lane registers configurations */
		phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc];
		if (phy_pma_ln_vals) {
			reg_pairs = phy_pma_ln_vals->reg_pairs;
			num_regs = phy_pma_ln_vals->num_regs;
			for (i = 0; i < num_lanes; i++) {
				regmap = sp->regmap_phy_pma_lane_cdb[i + mlane];
				for (j = 0; j < num_regs; j++)
					regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
			}
		}

		/* PMA common registers configurations */
		pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc];
		if (pma_cmn_vals) {
			reg_pairs = pma_cmn_vals->reg_pairs;
			num_regs = pma_cmn_vals->num_regs;
			regmap = sp->regmap_common_cdb;
			for (i = 0; i < num_regs; i++)
				regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
		}

		/* PMA lane registers configurations */
		pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc];
		if (pma_ln_vals) {
			reg_pairs = pma_ln_vals->reg_pairs;
			num_regs = pma_ln_vals->num_regs;
			for (i = 0; i < num_lanes; i++) {
				regmap = sp->regmap_lane_cdb[i + mlane];
				for (j = 0; j < num_regs; j++)
					regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
			}
		}

		if (phy_t1 == TYPE_SGMII || phy_t1 == TYPE_QSGMII)
			reset_control_deassert(sp->phys[node].lnk_rst);
	}

	/* Take the PHY out of reset */
	ret = reset_control_deassert(sp->phy_rst);
	if (ret)
		return ret;

	return 0;
}

static int cdns_sierra_phy_probe(struct platform_device *pdev)
{
	struct cdns_sierra_phy *sp;
	struct phy_provider *phy_provider;
	struct device *dev = &pdev->dev;
	const struct cdns_sierra_data *data;
	unsigned int id_value;
	int ret, node = 0;
	void __iomem *base;
	struct device_node *dn = dev->of_node, *child;

	if (of_get_child_count(dn) == 0)
		return -ENODEV;

	/* Get init data for this PHY */
	data = of_device_get_match_data(dev);
	if (!data)
		return -EINVAL;

	sp = devm_kzalloc(dev, struct_size(sp, clk_data.hws,
					   CDNS_SIERRA_OUTPUT_CLOCKS),
			  GFP_KERNEL);
	if (!sp)
		return -ENOMEM;
	dev_set_drvdata(dev, sp);
	sp->dev = dev;
	sp->init_data = data;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base)) {
		dev_err(dev, "missing \"reg\"\n");
		return PTR_ERR(base);
	}

	ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift,
				      data->reg_offset_shift);
	if (ret)
		return ret;

	ret = cdns_regfield_init(sp);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, sp);

	ret = cdns_sierra_phy_get_clocks(sp, dev);
	if (ret)
		return ret;

	ret = cdns_sierra_clk_register(sp);
	if (ret)
		return ret;

	ret = cdns_sierra_phy_enable_clocks(sp);
	if (ret)
		goto unregister_clk;

	regmap_field_read(sp->pma_cmn_ready, &sp->already_configured);

	if (!sp->already_configured) {
		ret = cdns_sierra_phy_clk(sp);
		if (ret)
			goto clk_disable;

		ret = cdns_sierra_phy_get_resets(sp, dev);
		if (ret)
			goto clk_disable;

		/* Enable APB */
		reset_control_deassert(sp->apb_rst);
	}

	/* Check that PHY is present */
	regmap_field_read(sp->macro_id_type, &id_value);
	if  (sp->init_data->id_value != id_value) {
		ret = -EINVAL;
		goto ctrl_assert;
	}

	sp->autoconf = of_property_read_bool(dn, "cdns,autoconf");

	for_each_available_child_of_node(dn, child) {
		struct phy *gphy;

		if (!(of_node_name_eq(child, "phy") ||
		      of_node_name_eq(child, "link")))
			continue;

		sp->phys[node].lnk_rst =
			of_reset_control_array_get_exclusive(child);

		if (IS_ERR(sp->phys[node].lnk_rst)) {
			dev_err(dev, "failed to get reset %s\n",
				child->full_name);
			ret = PTR_ERR(sp->phys[node].lnk_rst);
			of_node_put(child);
			goto put_control;
		}

		if (!sp->autoconf) {
			ret = cdns_sierra_get_optional(&sp->phys[node], child);
			if (ret) {
				dev_err(dev, "missing property in node %s\n",
					child->name);
				of_node_put(child);
				reset_control_put(sp->phys[node].lnk_rst);
				goto put_control;
			}
		}

		sp->num_lanes += sp->phys[node].num_lanes;

		if (!sp->already_configured)
			gphy = devm_phy_create(dev, child, &ops);
		else
			gphy = devm_phy_create(dev, child, &noop_ops);
		if (IS_ERR(gphy)) {
			ret = PTR_ERR(gphy);
			of_node_put(child);
			reset_control_put(sp->phys[node].lnk_rst);
			goto put_control;
		}
		sp->phys[node].phy = gphy;
		phy_set_drvdata(gphy, &sp->phys[node]);

		node++;
	}
	sp->nsubnodes = node;

	if (sp->num_lanes > SIERRA_MAX_LANES) {
		ret = -EINVAL;
		dev_err(dev, "Invalid lane configuration\n");
		goto put_control;
	}

	/* If more than one subnode, configure the PHY as multilink */
	if (!sp->already_configured && !sp->autoconf && sp->nsubnodes > 1) {
		ret = cdns_sierra_phy_configure_multilink(sp);
		if (ret)
			goto put_control;
	}

	pm_runtime_enable(dev);
	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	if (IS_ERR(phy_provider)) {
		ret = PTR_ERR(phy_provider);
		goto put_control;
	}

	return 0;

put_control:
	while (--node >= 0)
		reset_control_put(sp->phys[node].lnk_rst);
ctrl_assert:
	if (!sp->already_configured)
		reset_control_assert(sp->apb_rst);
clk_disable:
	cdns_sierra_phy_disable_clocks(sp);
unregister_clk:
	cdns_sierra_clk_unregister(sp);
	return ret;
}

static void cdns_sierra_phy_remove(struct platform_device *pdev)
{
	struct cdns_sierra_phy *phy = platform_get_drvdata(pdev);
	int i;

	reset_control_assert(phy->phy_rst);
	reset_control_assert(phy->apb_rst);
	pm_runtime_disable(&pdev->dev);

	cdns_sierra_phy_disable_clocks(phy);
	/*
	 * The device level resets will be put automatically.
	 * Need to put the subnode resets here though.
	 */
	for (i = 0; i < phy->nsubnodes; i++) {
		reset_control_assert(phy->phys[i].lnk_rst);
		reset_control_put(phy->phys[i].lnk_rst);
	}

	cdns_sierra_clk_unregister(phy);
}

/* Single link SGMII, refclk 100MHz, no ssc, opt1, no_bw_cal, GE1 links using plllc */
static const struct cdns_reg_pairs sl_sgmii_100_no_ssc_plllc_opt1_cmn_regs[] = {
	{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
	{0x0800, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
};

static const struct cdns_reg_pairs sl_sgmii_100_no_ssc_plllc_opt1_ln_regs[] = {
	{0x688E, SIERRA_DET_STANDEC_D_PREG},
	{0x0FFE, SIERRA_PSC_RX_A0_PREG},
	{0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},
	{0x0106, SIERRA_PLLCTRL_GEN_D_PREG},
	{0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
	{0x9702, SIERRA_DRVCTRL_BOOST_PREG},
	{0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},
	{0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},
	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
	{0x0002, SIERRA_DEQ_PHALIGN_CTRL},
	{0x0186, SIERRA_DEQ_GLUT0},
	{0x0186, SIERRA_DEQ_GLUT1},
	{0x0186, SIERRA_DEQ_GLUT2},
	{0x0186, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x0861, SIERRA_DEQ_ALUT0},
	{0x07E0, SIERRA_DEQ_ALUT1},
	{0x079E, SIERRA_DEQ_ALUT2},
	{0x071D, SIERRA_DEQ_ALUT3},
	{0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
	{0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0033, SIERRA_DEQ_PICTRL_PREG},
	{0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},
	{0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
	{0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
};

static struct cdns_sierra_vals sl_sgmii_100_no_ssc_plllc_opt1_cmn_vals = {
	.reg_pairs = sl_sgmii_100_no_ssc_plllc_opt1_cmn_regs,
	.num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_plllc_opt1_cmn_regs),
};

static struct cdns_sierra_vals sl_sgmii_100_no_ssc_plllc_opt1_ln_vals = {
	.reg_pairs = sl_sgmii_100_no_ssc_plllc_opt1_ln_regs,
	.num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_plllc_opt1_ln_regs),
};

/* SGMII PHY PMA lane configuration */
static struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = {
	{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
};

static struct cdns_sierra_vals sgmii_phy_pma_ln_vals = {
	.reg_pairs = sgmii_phy_pma_ln_regs,
	.num_regs = ARRAY_SIZE(sgmii_phy_pma_ln_regs),
};

/* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */
static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[] = {
	{0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},
	{0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
	{0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG},
	{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
	{0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
};

static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = {
	{0x688E, SIERRA_DET_STANDEC_D_PREG},
	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
	{0x0FFE, SIERRA_PSC_RX_A0_PREG},
	{0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},
	{0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},
	{0x0003, SIERRA_PLLCTRL_GEN_A_PREG},
	{0x0106, SIERRA_PLLCTRL_GEN_D_PREG},
	{0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG },
	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
	{0x9702, SIERRA_DRVCTRL_BOOST_PREG},
	{0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},
	{0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},
	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
	{0x0002, SIERRA_DEQ_PHALIGN_CTRL},
	{0x0186, SIERRA_DEQ_GLUT0},
	{0x0186, SIERRA_DEQ_GLUT1},
	{0x0186, SIERRA_DEQ_GLUT2},
	{0x0186, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x0861, SIERRA_DEQ_ALUT0},
	{0x07E0, SIERRA_DEQ_ALUT1},
	{0x079E, SIERRA_DEQ_ALUT2},
	{0x071D, SIERRA_DEQ_ALUT3},
	{0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
	{0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0033, SIERRA_DEQ_PICTRL_PREG},
	{0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},
	{0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
	{0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
};

static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals = {
	.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_cmn_regs,
	.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_cmn_regs),
};

static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals = {
	.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_ln_regs,
	.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_ln_regs),
};

/* QSGMII PHY PMA lane configuration */
static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {
	{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
};

static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = {
	.reg_pairs = qsgmii_phy_pma_ln_regs,
	.num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs),
};

/* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */
static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = {
	{0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
	{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
	{0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
};

static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x0252, SIERRA_DET_STANDEC_E_PREG},
	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
	{0x0FFE, SIERRA_PSC_RX_A0_PREG},
	{0x0011, SIERRA_PLLCTRL_SUBRATE_PREG},
	{0x0001, SIERRA_PLLCTRL_GEN_A_PREG},
	{0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
	{0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
	{0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG},
	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
	{0x8422, SIERRA_CTLELUT_CTRL_PREG},
	{0x4111, SIERRA_DFE_ECMP_RATESEL_PREG},
	{0x4111, SIERRA_DFE_SMP_RATESEL_PREG},
	{0x0002, SIERRA_DEQ_PHALIGN_CTRL},
	{0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG},
	{0x0186, SIERRA_DEQ_GLUT0},
	{0x0186, SIERRA_DEQ_GLUT1},
	{0x0186, SIERRA_DEQ_GLUT2},
	{0x0186, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x0861, SIERRA_DEQ_ALUT0},
	{0x07E0, SIERRA_DEQ_ALUT1},
	{0x079E, SIERRA_DEQ_ALUT2},
	{0x071D, SIERRA_DEQ_ALUT3},
	{0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
	{0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0033, SIERRA_DEQ_PICTRL_PREG},
	{0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
	{0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG},
	{0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
	{0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
};

static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = {
	.reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs,
	.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs),
};

static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = {
	.reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs,
	.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs),
};

/* PCIE PHY PCS common configuration */
static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
	{0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
};

static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
	.reg_pairs = pcie_phy_pcs_cmn_regs,
	.num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
};

/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */
static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = {
	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
};

/*
 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc,
 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
 */
static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
	{0x0004, SIERRA_PSC_LN_A3_PREG},
	{0x0004, SIERRA_PSC_LN_A4_PREG},
	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x0041, SIERRA_DEQ_GLUT0},
	{0x0082, SIERRA_DEQ_GLUT1},
	{0x00C3, SIERRA_DEQ_GLUT2},
	{0x0145, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x09E7, SIERRA_DEQ_ALUT0},
	{0x09A6, SIERRA_DEQ_ALUT1},
	{0x0965, SIERRA_DEQ_ALUT2},
	{0x08E3, SIERRA_DEQ_ALUT3},
	{0x00FA, SIERRA_DEQ_DFETAP0},
	{0x00FA, SIERRA_DEQ_DFETAP1},
	{0x00FA, SIERRA_DEQ_DFETAP2},
	{0x00FA, SIERRA_DEQ_DFETAP3},
	{0x00FA, SIERRA_DEQ_DFETAP4},
	{0x000F, SIERRA_DEQ_PRECUR_PREG},
	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x002B, SIERRA_CPI_TRIM_PREG},
	{0x0003, SIERRA_EPI_CTRL_PREG},
	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
};

static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = {
	.reg_pairs = pcie_100_no_ssc_plllc_cmn_regs,
	.num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs),
};

static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = {
	.reg_pairs = ml_pcie_100_no_ssc_ln_regs,
	.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs),
};

/*
 * TI J721E:
 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc,
 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
 */
static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
	{0x0004, SIERRA_PSC_LN_A3_PREG},
	{0x0004, SIERRA_PSC_LN_A4_PREG},
	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x0041, SIERRA_DEQ_GLUT0},
	{0x0082, SIERRA_DEQ_GLUT1},
	{0x00C3, SIERRA_DEQ_GLUT2},
	{0x0145, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x09E7, SIERRA_DEQ_ALUT0},
	{0x09A6, SIERRA_DEQ_ALUT1},
	{0x0965, SIERRA_DEQ_ALUT2},
	{0x08E3, SIERRA_DEQ_ALUT3},
	{0x00FA, SIERRA_DEQ_DFETAP0},
	{0x00FA, SIERRA_DEQ_DFETAP1},
	{0x00FA, SIERRA_DEQ_DFETAP2},
	{0x00FA, SIERRA_DEQ_DFETAP3},
	{0x00FA, SIERRA_DEQ_DFETAP4},
	{0x000F, SIERRA_DEQ_PRECUR_PREG},
	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x002B, SIERRA_CPI_TRIM_PREG},
	{0x0003, SIERRA_EPI_CTRL_PREG},
	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},
	{0x0002, SIERRA_TX_RCVDET_OVRD_PREG}
};

static struct cdns_sierra_vals ti_ml_pcie_100_no_ssc_ln_vals = {
	.reg_pairs = ti_ml_pcie_100_no_ssc_ln_regs,
	.num_regs = ARRAY_SIZE(ti_ml_pcie_100_no_ssc_ln_regs),
};

/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */
static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = {
	{0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
	{0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
	{0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
	{0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
	{0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
	{0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
	{0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
};

/*
 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc,
 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
 */
static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
	{0x0004, SIERRA_PSC_LN_A3_PREG},
	{0x0004, SIERRA_PSC_LN_A4_PREG},
	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x0041, SIERRA_DEQ_GLUT0},
	{0x0082, SIERRA_DEQ_GLUT1},
	{0x00C3, SIERRA_DEQ_GLUT2},
	{0x0145, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x09E7, SIERRA_DEQ_ALUT0},
	{0x09A6, SIERRA_DEQ_ALUT1},
	{0x0965, SIERRA_DEQ_ALUT2},
	{0x08E3, SIERRA_DEQ_ALUT3},
	{0x00FA, SIERRA_DEQ_DFETAP0},
	{0x00FA, SIERRA_DEQ_DFETAP1},
	{0x00FA, SIERRA_DEQ_DFETAP2},
	{0x00FA, SIERRA_DEQ_DFETAP3},
	{0x00FA, SIERRA_DEQ_DFETAP4},
	{0x000F, SIERRA_DEQ_PRECUR_PREG},
	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x002B, SIERRA_CPI_TRIM_PREG},
	{0x0003, SIERRA_EPI_CTRL_PREG},
	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
};

static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = {
	.reg_pairs = pcie_100_int_ssc_plllc_cmn_regs,
	.num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs),
};

static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = {
	.reg_pairs = ml_pcie_100_int_ssc_ln_regs,
	.num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs),
};

/*
 * TI J721E:
 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc,
 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
 */
static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
	{0x0004, SIERRA_PSC_LN_A3_PREG},
	{0x0004, SIERRA_PSC_LN_A4_PREG},
	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x0041, SIERRA_DEQ_GLUT0},
	{0x0082, SIERRA_DEQ_GLUT1},
	{0x00C3, SIERRA_DEQ_GLUT2},
	{0x0145, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x09E7, SIERRA_DEQ_ALUT0},
	{0x09A6, SIERRA_DEQ_ALUT1},
	{0x0965, SIERRA_DEQ_ALUT2},
	{0x08E3, SIERRA_DEQ_ALUT3},
	{0x00FA, SIERRA_DEQ_DFETAP0},
	{0x00FA, SIERRA_DEQ_DFETAP1},
	{0x00FA, SIERRA_DEQ_DFETAP2},
	{0x00FA, SIERRA_DEQ_DFETAP3},
	{0x00FA, SIERRA_DEQ_DFETAP4},
	{0x000F, SIERRA_DEQ_PRECUR_PREG},
	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x002B, SIERRA_CPI_TRIM_PREG},
	{0x0003, SIERRA_EPI_CTRL_PREG},
	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},
	{0x0002, SIERRA_TX_RCVDET_OVRD_PREG}
};

static struct cdns_sierra_vals ti_ml_pcie_100_int_ssc_ln_vals = {
	.reg_pairs = ti_ml_pcie_100_int_ssc_ln_regs,
	.num_regs = ARRAY_SIZE(ti_ml_pcie_100_int_ssc_ln_regs),
};

/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */
static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = {
	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
	{0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
};

/*
 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc,
 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
 */
static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
	{0x0004, SIERRA_PSC_LN_A3_PREG},
	{0x0004, SIERRA_PSC_LN_A4_PREG},
	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x0041, SIERRA_DEQ_GLUT0},
	{0x0082, SIERRA_DEQ_GLUT1},
	{0x00C3, SIERRA_DEQ_GLUT2},
	{0x0145, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x09E7, SIERRA_DEQ_ALUT0},
	{0x09A6, SIERRA_DEQ_ALUT1},
	{0x0965, SIERRA_DEQ_ALUT2},
	{0x08E3, SIERRA_DEQ_ALUT3},
	{0x00FA, SIERRA_DEQ_DFETAP0},
	{0x00FA, SIERRA_DEQ_DFETAP1},
	{0x00FA, SIERRA_DEQ_DFETAP2},
	{0x00FA, SIERRA_DEQ_DFETAP3},
	{0x00FA, SIERRA_DEQ_DFETAP4},
	{0x000F, SIERRA_DEQ_PRECUR_PREG},
	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x002B, SIERRA_CPI_TRIM_PREG},
	{0x0003, SIERRA_EPI_CTRL_PREG},
	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
};

static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = {
	.reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs,
	.num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs),
};

static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = {
	.reg_pairs = ml_pcie_100_ext_ssc_ln_regs,
	.num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs),
};

/*
 * TI J721E:
 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc,
 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
 */
static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
	{0x0004, SIERRA_PSC_LN_A3_PREG},
	{0x0004, SIERRA_PSC_LN_A4_PREG},
	{0x0004, SIERRA_PSC_LN_IDLE_PREG},
	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x0041, SIERRA_DEQ_GLUT0},
	{0x0082, SIERRA_DEQ_GLUT1},
	{0x00C3, SIERRA_DEQ_GLUT2},
	{0x0145, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x09E7, SIERRA_DEQ_ALUT0},
	{0x09A6, SIERRA_DEQ_ALUT1},
	{0x0965, SIERRA_DEQ_ALUT2},
	{0x08E3, SIERRA_DEQ_ALUT3},
	{0x00FA, SIERRA_DEQ_DFETAP0},
	{0x00FA, SIERRA_DEQ_DFETAP1},
	{0x00FA, SIERRA_DEQ_DFETAP2},
	{0x00FA, SIERRA_DEQ_DFETAP3},
	{0x00FA, SIERRA_DEQ_DFETAP4},
	{0x000F, SIERRA_DEQ_PRECUR_PREG},
	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x002B, SIERRA_CPI_TRIM_PREG},
	{0x0003, SIERRA_EPI_CTRL_PREG},
	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},
	{0x0002, SIERRA_TX_RCVDET_OVRD_PREG}
};

static struct cdns_sierra_vals ti_ml_pcie_100_ext_ssc_ln_vals = {
	.reg_pairs = ti_ml_pcie_100_ext_ssc_ln_regs,
	.num_regs = ARRAY_SIZE(ti_ml_pcie_100_ext_ssc_ln_regs),
};

/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */
static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {
	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
};

/* refclk100MHz_32b_PCIe_ln_no_ssc */
static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x0041, SIERRA_DEQ_GLUT0},
	{0x0082, SIERRA_DEQ_GLUT1},
	{0x00C3, SIERRA_DEQ_GLUT2},
	{0x0145, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x09E7, SIERRA_DEQ_ALUT0},
	{0x09A6, SIERRA_DEQ_ALUT1},
	{0x0965, SIERRA_DEQ_ALUT2},
	{0x08E3, SIERRA_DEQ_ALUT3},
	{0x00FA, SIERRA_DEQ_DFETAP0},
	{0x00FA, SIERRA_DEQ_DFETAP1},
	{0x00FA, SIERRA_DEQ_DFETAP2},
	{0x00FA, SIERRA_DEQ_DFETAP3},
	{0x00FA, SIERRA_DEQ_DFETAP4},
	{0x000F, SIERRA_DEQ_PRECUR_PREG},
	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x002B, SIERRA_CPI_TRIM_PREG},
	{0x0003, SIERRA_EPI_CTRL_PREG},
	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
};

static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = {
	.reg_pairs = cdns_pcie_cmn_regs_no_ssc,
	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc),
};

static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = {
	.reg_pairs = cdns_pcie_ln_regs_no_ssc,
	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc),
};

/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */
static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = {
	{0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
	{0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
	{0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
	{0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
	{0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
	{0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
	{0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
};

/* refclk100MHz_32b_PCIe_ln_int_ssc */
static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x0041, SIERRA_DEQ_GLUT0},
	{0x0082, SIERRA_DEQ_GLUT1},
	{0x00C3, SIERRA_DEQ_GLUT2},
	{0x0145, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x09E7, SIERRA_DEQ_ALUT0},
	{0x09A6, SIERRA_DEQ_ALUT1},
	{0x0965, SIERRA_DEQ_ALUT2},
	{0x08E3, SIERRA_DEQ_ALUT3},
	{0x00FA, SIERRA_DEQ_DFETAP0},
	{0x00FA, SIERRA_DEQ_DFETAP1},
	{0x00FA, SIERRA_DEQ_DFETAP2},
	{0x00FA, SIERRA_DEQ_DFETAP3},
	{0x00FA, SIERRA_DEQ_DFETAP4},
	{0x000F, SIERRA_DEQ_PRECUR_PREG},
	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x002B, SIERRA_CPI_TRIM_PREG},
	{0x0003, SIERRA_EPI_CTRL_PREG},
	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
};

static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = {
	.reg_pairs = cdns_pcie_cmn_regs_int_ssc,
	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc),
};

static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = {
	.reg_pairs = cdns_pcie_ln_regs_int_ssc,
	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc),
};

/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
	{0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
};

/* refclk100MHz_32b_PCIe_ln_ext_ssc */
static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
	{0xFC08, SIERRA_DET_STANDEC_A_PREG},
	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
	{0x1555, SIERRA_DFE_BIASTRIM_PREG},
	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},
	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
	{0x9800, SIERRA_RX_CTLE_CAL_PREG},
	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x0041, SIERRA_DEQ_GLUT0},
	{0x0082, SIERRA_DEQ_GLUT1},
	{0x00C3, SIERRA_DEQ_GLUT2},
	{0x0145, SIERRA_DEQ_GLUT3},
	{0x0186, SIERRA_DEQ_GLUT4},
	{0x09E7, SIERRA_DEQ_ALUT0},
	{0x09A6, SIERRA_DEQ_ALUT1},
	{0x0965, SIERRA_DEQ_ALUT2},
	{0x08E3, SIERRA_DEQ_ALUT3},
	{0x00FA, SIERRA_DEQ_DFETAP0},
	{0x00FA, SIERRA_DEQ_DFETAP1},
	{0x00FA, SIERRA_DEQ_DFETAP2},
	{0x00FA, SIERRA_DEQ_DFETAP3},
	{0x00FA, SIERRA_DEQ_DFETAP4},
	{0x000F, SIERRA_DEQ_PRECUR_PREG},
	{0x0280, SIERRA_DEQ_POSTCUR_PREG},
	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x002B, SIERRA_CPI_TRIM_PREG},
	{0x0003, SIERRA_EPI_CTRL_PREG},
	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
};

static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
	.reg_pairs = cdns_pcie_cmn_regs_ext_ssc,
	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
};

static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = {
	.reg_pairs = cdns_pcie_ln_regs_ext_ssc,
	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
};

/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
	{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
	{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
	{0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
};

/* refclk100MHz_20b_USB_ln_ext_ssc */
static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
	{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
	{0x000F, SIERRA_DET_STANDEC_B_PREG},
	{0x55A5, SIERRA_DET_STANDEC_C_PREG},
	{0x69ad, SIERRA_DET_STANDEC_D_PREG},
	{0x0241, SIERRA_DET_STANDEC_E_PREG},
	{0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
	{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
	{0xCF00, SIERRA_PSM_DIAG_PREG},
	{0x001F, SIERRA_PSC_TX_A0_PREG},
	{0x0007, SIERRA_PSC_TX_A1_PREG},
	{0x0003, SIERRA_PSC_TX_A2_PREG},
	{0x0003, SIERRA_PSC_TX_A3_PREG},
	{0x0FFF, SIERRA_PSC_RX_A0_PREG},
	{0x0003, SIERRA_PSC_RX_A1_PREG},
	{0x0003, SIERRA_PSC_RX_A2_PREG},
	{0x0001, SIERRA_PSC_RX_A3_PREG},
	{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
	{0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
	{0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
	{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
	{0x2512, SIERRA_DFE_BIASTRIM_PREG},
	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
	{0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
	{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
	{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
	{0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
	{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
	{0x0000, SIERRA_CREQ_SPARE_PREG},
	{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
	{0x8452, SIERRA_CTLELUT_CTRL_PREG},
	{0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
	{0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
	{0x0003, SIERRA_DEQ_PHALIGN_CTRL},
	{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
	{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
	{0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
	{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
	{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
	{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
	{0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
	{0x0014, SIERRA_DEQ_GLUT0},
	{0x0014, SIERRA_DEQ_GLUT1},
	{0x0014, SIERRA_DEQ_GLUT2},
	{0x0014, SIERRA_DEQ_GLUT3},
	{0x0014, SIERRA_DEQ_GLUT4},
	{0x0014, SIERRA_DEQ_GLUT5},
	{0x0014, SIERRA_DEQ_GLUT6},
	{0x0014, SIERRA_DEQ_GLUT7},
	{0x0014, SIERRA_DEQ_GLUT8},
	{0x0014, SIERRA_DEQ_GLUT9},
	{0x0014, SIERRA_DEQ_GLUT10},
	{0x0014, SIERRA_DEQ_GLUT11},
	{0x0014, SIERRA_DEQ_GLUT12},
	{0x0014, SIERRA_DEQ_GLUT13},
	{0x0014, SIERRA_DEQ_GLUT14},
	{0x0014, SIERRA_DEQ_GLUT15},
	{0x0014, SIERRA_DEQ_GLUT16},
	{0x0BAE, SIERRA_DEQ_ALUT0},
	{0x0AEB, SIERRA_DEQ_ALUT1},
	{0x0A28, SIERRA_DEQ_ALUT2},
	{0x0965, SIERRA_DEQ_ALUT3},
	{0x08A2, SIERRA_DEQ_ALUT4},
	{0x07DF, SIERRA_DEQ_ALUT5},
	{0x071C, SIERRA_DEQ_ALUT6},
	{0x0659, SIERRA_DEQ_ALUT7},
	{0x0596, SIERRA_DEQ_ALUT8},
	{0x0514, SIERRA_DEQ_ALUT9},
	{0x0492, SIERRA_DEQ_ALUT10},
	{0x0410, SIERRA_DEQ_ALUT11},
	{0x038E, SIERRA_DEQ_ALUT12},
	{0x030C, SIERRA_DEQ_ALUT13},
	{0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
	{0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
	{0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
	{0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0033, SIERRA_DEQ_PICTRL_PREG},
	{0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
	{0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
	{0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
	{0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
	{0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
	{0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
	{0x000F, SIERRA_LFPSFILT_NS_PREG},
	{0x0009, SIERRA_LFPSFILT_RD_PREG},
	{0x0001, SIERRA_LFPSFILT_MP_PREG},
	{0x6013, SIERRA_SIGDET_SUPPORT_PREG},
	{0x8013, SIERRA_SDFILT_H2L_A_PREG},
	{0x8009, SIERRA_SDFILT_L2H_PREG},
	{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
	{0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
	{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
};

static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = {
	.reg_pairs = cdns_usb_cmn_regs_ext_ssc,
	.num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
};

static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = {
	.reg_pairs = cdns_usb_ln_regs_ext_ssc,
	.num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
};

/* SGMII PHY common configuration */
static const struct cdns_reg_pairs sgmii_pma_cmn_vals[] = {
	{0x0180, SIERRA_SDOSCCAL_CLK_CNT_PREG},
	{0x6000, SIERRA_CMN_REFRCV_PREG},
	{0x0031, SIERRA_CMN_RESCAL_CTRLA_PREG},
	{0x001C, SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG},
	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
	{0x0000, SIERRA_CMN_PLLLC_LOCKSEARCH_PREG},
	{0x8103, SIERRA_CMN_PLLLC_CLK0_PREG},
	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
	{0x0027, SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG},
	{0x0062, SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG},
	{0x0800, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
	{0x0000, SIERRA_CMN_PLLLC_INIT_PREG},
	{0x0000, SIERRA_CMN_PLLLC_ITERTMR_PREG},
	{0x0020, SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG},
	{0x0013, SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG},
	{0x0013, SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG},
};

static struct cdns_sierra_vals sgmii_cmn_vals = {
	.reg_pairs = sgmii_pma_cmn_vals,
	.num_regs = ARRAY_SIZE(sgmii_pma_cmn_vals),
};

/* SGMII PHY lane configuration */
static const struct cdns_reg_pairs sgmii_ln_regs[] = {
	{0x691E, SIERRA_DET_STANDEC_D_PREG},
	{0x0FFE, SIERRA_PSC_RX_A0_PREG},
	{0x0104, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},
	{0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},
	{0x0106, SIERRA_PLLCTRL_GEN_D_PREG},
	{0x5234, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
	{0x00AB, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
	{0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},
	{0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},
	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
	{0x6320, SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG},
	{0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},
	{0x15A2, SIERRA_LN_SPARE_REG_PREG},
	{0x7900, SIERRA_DEQ_BLK_TAU_CTRL1_PREG},
	{0x2202, SIERRA_DEQ_BLK_TAU_CTRL4_PREG},
	{0x2206, SIERRA_DEQ_TAU_CTRL2_PREG},
	{0x0005, SIERRA_LANE_TX_RECEIVER_DETECT_PREG},
	{0x8001, SIERRA_CREQ_SPARE_PREG},
	{0x0000, SIERRA_DEQ_CONCUR_CTRL1_PREG},
	{0xD004, SIERRA_DEQ_CONCUR_CTRL2_PREG},
	{0x0101, SIERRA_DEQ_GLUT9},
	{0x0101, SIERRA_DEQ_GLUT10},
	{0x0101, SIERRA_DEQ_GLUT11},
	{0x0101, SIERRA_DEQ_GLUT12},
	{0x0000, SIERRA_DEQ_GLUT13},
	{0x0000, SIERRA_DEQ_GLUT16},
	{0x0000, SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG},
	{0x0000, SIERRA_TAU_EN_CEPH2TO0_PREG},
	{0x0003, SIERRA_TAU_EN_CEPH5TO3_PREG},
	{0x0101, SIERRA_DEQ_ALUT8},
	{0x0101, SIERRA_DEQ_ALUT9},
	{0x0100, SIERRA_DEQ_ALUT10},
	{0x0000, SIERRA_OEPH_EN_CTRL_PREG},
	{0x5425, SIERRA_DEQ_OPENEYE_CTRL_PREG},
	{0x7458, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
	{0x321F, SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG},
};

static struct cdns_sierra_vals sgmii_pma_ln_vals = {
	.reg_pairs = sgmii_ln_regs,
	.num_regs = ARRAY_SIZE(sgmii_ln_regs),
};

static const struct cdns_sierra_data cdns_map_sierra = {
	.id_value = SIERRA_MACRO_ID,
	.block_offset_shift = 0x2,
	.reg_offset_shift = 0x2,
	.pcs_cmn_vals = {
		[TYPE_PCIE] = {
			[TYPE_NONE] = {
				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
			},
			[TYPE_SGMII] = {
				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
			},
			[TYPE_QSGMII] = {
				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
			},
		},
	},
	.pma_cmn_vals = {
		[TYPE_PCIE] = {
			[TYPE_NONE] = {
				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
			},
			[TYPE_SGMII] = {
				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
			},
			[TYPE_QSGMII] = {
				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
			},
		},
		[TYPE_USB] = {
			[TYPE_NONE] = {
				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
			},
		},
		[TYPE_SGMII] = {
			[TYPE_NONE] = {
				[NO_SSC] = &sl_sgmii_100_no_ssc_plllc_opt1_cmn_vals,
			},
			[TYPE_PCIE] = {
				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
			},
		},
		[TYPE_QSGMII] = {
			[TYPE_PCIE] = {
				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
			},
		},
	},
	.pma_ln_vals = {
		[TYPE_PCIE] = {
			[TYPE_NONE] = {
				[NO_SSC] = &pcie_100_no_ssc_ln_vals,
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
			},
			[TYPE_SGMII] = {
				[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
				[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
				[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
			},
			[TYPE_QSGMII] = {
				[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
				[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
				[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
			},
		},
		[TYPE_USB] = {
			[TYPE_NONE] = {
				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
			},
		},
		[TYPE_SGMII] = {
			[TYPE_NONE] = {
				[NO_SSC] = &sl_sgmii_100_no_ssc_plllc_opt1_ln_vals,
			},
			[TYPE_PCIE] = {
				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
			},
		},
		[TYPE_QSGMII] = {
			[TYPE_PCIE] = {
				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
			},
		},
	},
};

static const struct cdns_sierra_data cdns_ti_map_sierra = {
	.id_value = SIERRA_MACRO_ID,
	.block_offset_shift = 0x0,
	.reg_offset_shift = 0x1,
	.pcs_cmn_vals = {
		[TYPE_PCIE] = {
			[TYPE_NONE] = {
				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
			},
			[TYPE_SGMII] = {
				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
			},
			[TYPE_QSGMII] = {
				[NO_SSC] = &pcie_phy_pcs_cmn_vals,
				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
			},
		},
	},
	.phy_pma_ln_vals = {
		[TYPE_SGMII] = {
			[TYPE_NONE] = {
				[NO_SSC] = &sgmii_phy_pma_ln_vals,
			},
			[TYPE_PCIE] = {
				[NO_SSC] = &sgmii_phy_pma_ln_vals,
				[EXTERNAL_SSC] = &sgmii_phy_pma_ln_vals,
				[INTERNAL_SSC] = &sgmii_phy_pma_ln_vals,
			},
		},
		[TYPE_QSGMII] = {
			[TYPE_PCIE] = {
				[NO_SSC] = &qsgmii_phy_pma_ln_vals,
				[EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
				[INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
			},
		},
	},
	.pma_cmn_vals = {
		[TYPE_PCIE] = {
			[TYPE_NONE] = {
				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
			},
			[TYPE_SGMII] = {
				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
			},
			[TYPE_QSGMII] = {
				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
			},
		},
		[TYPE_USB] = {
			[TYPE_NONE] = {
				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
			},
		},
		[TYPE_SGMII] = {
			[TYPE_NONE] = {
				[NO_SSC] = &sl_sgmii_100_no_ssc_plllc_opt1_cmn_vals,
			},
			[TYPE_PCIE] = {
				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
			},
		},
		[TYPE_QSGMII] = {
			[TYPE_PCIE] = {
				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
			},
		},
	},
	.pma_ln_vals = {
		[TYPE_PCIE] = {
			[TYPE_NONE] = {
				[NO_SSC] = &pcie_100_no_ssc_ln_vals,
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
			},
			[TYPE_SGMII] = {
				[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,
				[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
				[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,
			},
			[TYPE_QSGMII] = {
				[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,
				[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
				[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,
			},
		},
		[TYPE_USB] = {
			[TYPE_NONE] = {
				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
			},
		},
		[TYPE_SGMII] = {
			[TYPE_NONE] = {
				[NO_SSC] = &sl_sgmii_100_no_ssc_plllc_opt1_ln_vals,
			},
			[TYPE_PCIE] = {
				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
			},
		},
		[TYPE_QSGMII] = {
			[TYPE_PCIE] = {
				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
			},
		},
	},
};

static const struct of_device_id cdns_sierra_id_table[] = {
	{
		.compatible = "cdns,sierra-phy-t0",
		.data = &cdns_map_sierra,
	},
	{
		.compatible = "ti,sierra-phy-t0",
		.data = &cdns_ti_map_sierra,
	},
	{}
};
MODULE_DEVICE_TABLE(of, cdns_sierra_id_table);

static struct platform_driver cdns_sierra_driver = {
	.probe		= cdns_sierra_phy_probe,
	.remove_new	= cdns_sierra_phy_remove,
	.driver		= {
		.name	= "cdns-sierra-phy",
		.of_match_table = cdns_sierra_id_table,
	},
};
module_platform_driver(cdns_sierra_driver);

MODULE_ALIAS("platform:cdns_sierra");
MODULE_AUTHOR("Cadence Design Systems");
MODULE_DESCRIPTION("CDNS sierra phy driver");
MODULE_LICENSE("GPL v2");

Hi,

As patch is integrated and device tree SerDes is enabled, It suppose to work.

Can you please share device tree files and above requested register dump after lane control changes as suggested above.

Best Regards,
Sudheer

I found that the dts configuration does not apply to the register, so I set 0x00104090 to 0 in the driver code,
You can see from the log that the register was set successfully before waiting for the CMN, and devmem2 can read it correctly.

root@j721e-evm:~# dmesg | grep serdes
[    2.181498] cdns-sierra-phy 5000000.serdes: Timeout waiting for PHY status ready
[    2.188886] phy phy-5000000.serdes.9: phy poweron failed --> -110
[    2.341523] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[    2.348908] phy phy-5020000.serdes.11: phy poweron failed --> -110
[    2.527377] mv88q2220 46000f00.mdio:02: [serdes] Reg 0x00104090 set 0x00000000
[    2.534584] mv88q2220 46000f00.mdio:02: [serdes] Reg 0x00104094 set 0x00000000
[    3.387418] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
[    3.394197] phy phy-5010000.serdes.10: phy poweron failed --> -110
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x01004090
/dev/mem opened.
Memory mapped at address 0xffff96892000.
Read at address  0x01004090 (0xffff96892090): 0x00000000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x01004094
/dev/mem opened.
Memory mapped at address 0xffffb5a3a000.
Read at address  0x01004094 (0xffffb5a3a094): 0x00000000
root@j721e-evm:~#
root@j721e-evm:~# k3conf dump clock 293
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                             | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------------------------------------------|
|   293     |     0    | DEV_SERDES_16G1_CORE_REF1_CLK                                          | CLK_STATE_READY | 100000000       |
|   293     |     1    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
|   293     |     2    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   293     |     3    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153       |
|   293     |     4    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   293     |     5    | DEV_SERDES_16G1_CLK                                                    | CLK_STATE_READY | 125000000       |
|   293     |     6    | DEV_SERDES_16G1_IP1_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     7    | DEV_SERDES_16G1_IP2_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     8    | DEV_SERDES_16G1_IP4_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     9    | DEV_SERDES_16G1_IP4_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    10    | DEV_SERDES_16G1_IP3_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    11    | DEV_SERDES_16G1_IP2_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    12    | DEV_SERDES_16G1_IP1_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    13    | DEV_SERDES_16G1_CORE_REF_CLK                                           | CLK_STATE_READY | 100000000       |
|   293     |    14    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | CLK_STATE_READY | 19200000        |
|   293     |    15    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | CLK_STATE_READY | 0               |
|   293     |    16    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | CLK_STATE_READY | 153846153       |
|   293     |    17    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | CLK_STATE_READY | 100000000       |
|   293     |    18    | DEV_SERDES_16G1_IP2_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    19    | DEV_SERDES_16G1_IP1_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    20    | DEV_SERDES_16G1_IP4_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    21    | DEV_SERDES_16G1_IP3_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    22    | DEV_SERDES_16G1_IP3_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    23    | DEV_SERDES_16G1_IP1_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    24    | DEV_SERDES_16G1_IP2_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    25    | DEV_SERDES_16G1_IP2_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    26    | DEV_SERDES_16G1_REF_DER_OUT_CLK                                        | CLK_STATE_READY | 0               |
|   293     |    27    | DEV_SERDES_16G1_IP1_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    28    | DEV_SERDES_16G1_IP3_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    29    | DEV_SERDES_16G1_IP1_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    30    | DEV_SERDES_16G1_IP1_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    31    | DEV_SERDES_16G1_IP4_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    32    | DEV_SERDES_16G1_IP3_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    33    | DEV_SERDES_16G1_IP4_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    34    | DEV_SERDES_16G1_IP3_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    35    | DEV_SERDES_16G1_IP4_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    36    | DEV_SERDES_16G1_IP2_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    37    | DEV_SERDES_16G1_IP2_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    38    | DEV_SERDES_16G1_IP1_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    39    | DEV_SERDES_16G1_REF_OUT_CLK                                            | CLK_STATE_READY | 0               |
|   293     |    40    | DEV_SERDES_16G1_REF1_OUT_CLK                                           | CLK_STATE_READY | 0               |
|   293     |    41    | DEV_SERDES_16G1_IP4_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    42    | DEV_SERDES_16G1_IP1_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    43    | DEV_SERDES_16G1_IP1_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    44    | DEV_SERDES_16G1_IP4_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    45    | DEV_SERDES_16G1_IP4_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    46    | DEV_SERDES_16G1_IP2_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    47    | DEV_SERDES_16G1_IP2_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    48    | DEV_SERDES_16G1_IP4_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    49    | DEV_SERDES_16G1_IP2_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    50    | DEV_SERDES_16G1_IP2_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    51    | DEV_SERDES_16G1_IP1_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    52    | DEV_SERDES_16G1_IP2_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    53    | DEV_SERDES_16G1_IP4_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    54    | DEV_SERDES_16G1_IP1_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    55    | DEV_SERDES_16G1_IP4_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    60    | DEV_SERDES_16G1_CMN_REFCLK1_M                                          | CLK_STATE_READY | 0               |
|   293     |    67    | DEV_SERDES_16G1_CMN_REFCLK1_P                                          | CLK_STATE_READY | 0               |
|-----------------------------------------------------------------------------------------------------------------------------------|

root@j721e-evm:~#
root@j721e-evm:~#

Hi,

zs xu said:

I found that the dts configuration does not apply to the register, so I set 0x00104090 to 0 in the driver code,

It should apply from device tree, by the time SerDes driver load It should be enabled for SGMII.

Please check and update serdes_ln_ctrl from u-boot as well as Linux.

Please check any where it was overwritten in dtsi files or overlay files and update properly as needed.

Best Regards,
Sudheer

Doredla Sudheer Kumar said:

Please check any where it was overwritten in dtsi files or overlay files and update properly as needed.

What does 'overlay files' mean? What do I need to do?

Hi,

zs xu said:

Doredla Sudheer Kumar said:

Please check any where it was overwritten in dtsi files or overlay files and update properly as needed.

What does 'overlay files' mean? What do I need to do?

I mean device tree overlay file (.dtso: overlay source file, dtbo: overlay binary file).
Native Linux driver is enabled using dtbo (k3-j721e-evm-quad-port-eth-exp.dtso) added to u-boot overlays.

SerDes lane control what ever you are setting is not reflected means, some where it will be over written.
Please check the overlay files if you have applied any.

Best Regards,
Sudheer

I modified the serdes_ln_ctrl of k3-j721e-evm-ethfw. dtso, which is valid in the register.
I configured '3' SGMII.
log to see CMN Timeout and register values and k3conf information.
How can this problem be solved? What other information do you need?

root@j721e-evm:~# dmesg | grep cdns-sierra-phy
[    2.180506] cdns-sierra-phy 5000000.serdes: Timeout waiting for PHY status ready
[    2.341018] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[    3.377038] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x00104080
/dev/mem opened.
Memory mapped at address 0xffffa2e88000.
Read at address  0x00104080 (0xffffa2e88080): 0x00000000
root@j721e-evm:~# devmem2 0x00104084
/dev/mem opened.
Memory mapped at address 0xffff88b92000.
Read at address  0x00104084 (0xffff88b92084): 0x00000000
root@j721e-evm:~# devmem2 0x00104090
/dev/mem opened.
Memory mapped at address 0xffffaa50a000.
Read at address  0x00104090 (0xffffaa50a090): 0x00000003
root@j721e-evm:~# devmem2 0x00104094
/dev/mem opened.
Memory mapped at address 0xffffbc543000.
Read at address  0x00104094 (0xffffbc543094): 0x00000003
root@j721e-evm:~#
root@j721e-evm:~# k3conf dump clock 293
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                             | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------------------------------------------|
|   293     |     0    | DEV_SERDES_16G1_CORE_REF1_CLK                                          | CLK_STATE_READY | 100000000       |
|   293     |     1    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
|   293     |     2    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   293     |     3    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153       |
|   293     |     4    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   293     |     5    | DEV_SERDES_16G1_CLK                                                    | CLK_STATE_READY | 125000000       |
|   293     |     6    | DEV_SERDES_16G1_IP1_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     7    | DEV_SERDES_16G1_IP2_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     8    | DEV_SERDES_16G1_IP4_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     9    | DEV_SERDES_16G1_IP4_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    10    | DEV_SERDES_16G1_IP3_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    11    | DEV_SERDES_16G1_IP2_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    12    | DEV_SERDES_16G1_IP1_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    13    | DEV_SERDES_16G1_CORE_REF_CLK                                           | CLK_STATE_READY | 100000000       |
|   293     |    14    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | CLK_STATE_READY | 19200000        |
|   293     |    15    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | CLK_STATE_READY | 0               |
|   293     |    16    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | CLK_STATE_READY | 153846153       |
|   293     |    17    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | CLK_STATE_READY | 100000000       |
|   293     |    18    | DEV_SERDES_16G1_IP2_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    19    | DEV_SERDES_16G1_IP1_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    20    | DEV_SERDES_16G1_IP4_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    21    | DEV_SERDES_16G1_IP3_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    22    | DEV_SERDES_16G1_IP3_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    23    | DEV_SERDES_16G1_IP1_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    24    | DEV_SERDES_16G1_IP2_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    25    | DEV_SERDES_16G1_IP2_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    26    | DEV_SERDES_16G1_REF_DER_OUT_CLK                                        | CLK_STATE_READY | 0               |
|   293     |    27    | DEV_SERDES_16G1_IP1_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    28    | DEV_SERDES_16G1_IP3_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    29    | DEV_SERDES_16G1_IP1_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    30    | DEV_SERDES_16G1_IP1_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    31    | DEV_SERDES_16G1_IP4_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    32    | DEV_SERDES_16G1_IP3_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    33    | DEV_SERDES_16G1_IP4_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    34    | DEV_SERDES_16G1_IP3_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    35    | DEV_SERDES_16G1_IP4_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    36    | DEV_SERDES_16G1_IP2_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    37    | DEV_SERDES_16G1_IP2_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    38    | DEV_SERDES_16G1_IP1_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    39    | DEV_SERDES_16G1_REF_OUT_CLK                                            | CLK_STATE_READY | 0               |
|   293     |    40    | DEV_SERDES_16G1_REF1_OUT_CLK                                           | CLK_STATE_READY | 0               |
|   293     |    41    | DEV_SERDES_16G1_IP4_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    42    | DEV_SERDES_16G1_IP1_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    43    | DEV_SERDES_16G1_IP1_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    44    | DEV_SERDES_16G1_IP4_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    45    | DEV_SERDES_16G1_IP4_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    46    | DEV_SERDES_16G1_IP2_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    47    | DEV_SERDES_16G1_IP2_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    48    | DEV_SERDES_16G1_IP4_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    49    | DEV_SERDES_16G1_IP2_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    50    | DEV_SERDES_16G1_IP2_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    51    | DEV_SERDES_16G1_IP1_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    52    | DEV_SERDES_16G1_IP2_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    53    | DEV_SERDES_16G1_IP4_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    54    | DEV_SERDES_16G1_IP1_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    55    | DEV_SERDES_16G1_IP4_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    60    | DEV_SERDES_16G1_CMN_REFCLK1_M                                          | CLK_STATE_READY | 0               |
|   293     |    67    | DEV_SERDES_16G1_CMN_REFCLK1_P                                          | CLK_STATE_READY | 0               |
|-----------------------------------------------------------------------------------------------------------------------------------|

root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x00108410
/dev/mem opened.
Memory mapped at address 0xffff93bfa000.
Read at address  0x00108410 (0xffff93bfa410): 0x00000003
root@j721e-evm:~# devmem2 0x05010408
/dev/mem opened.
Memory mapped at address 0xffffa6531000.
Read at address  0x05010408 (0xffffa6531408): 0x9A000000
root@j721e-evm:~# devmem2 0x0501040c
/dev/mem opened.
Memory mapped at address 0xffffa8f22000.
Read at address  0x0501040C (0xffffa8f2240c): 0x92000000
root@j721e-evm:~# devmem2 0x05010480
/dev/mem opened.
Memory mapped at address 0xffff84ea1000.
Read at address  0x05010480 (0xffff84ea1480): 0x70800000
root@j721e-evm:~# devmem2 0x0501048c
/dev/mem opened.
Memory mapped at address 0xffffa771b000.
Read at address  0x0501048C (0xffffa771b48c): 0x00000002
root@j721e-evm:~# devmem2 0x0501e000
/dev/mem opened.
Memory mapped at address 0xffffb3cf6000.
Read at address  0x0501E000 (0xffffb3cf6000): 0x00003010
root@j721e-evm:~#

Hi,

From the register dump, I can still see SerDes1 Lanes are not enabled and SerDes0 Lanes are configured for SGMII Port-1, Port-2.
Memory mapped at address 0xffffaa50a000.
Read at address  0x00104090 (0xffffaa50a090): 0x00000003
root@j721e-evm:~# devmem2 0x00104094
/dev/mem opened.
Memory mapped at address 0xffffbc543000.
Read at address  0x00104094 (0xffffbc543094): 0x00000003

Above values should be 0s for enabling SGMII-3, SGMII-4.

Doredla Sudheer Kumar said:

Please check serdes_ln_ctrl configuration and use proper values.
You suppose to use {J721E_SERDES1_LANE0_QSGMII_LANE3, J721E_SERDES1_LANE1_QSGMII_LANE4} for using CPSW Port-3 & Port-4.

Refer to TRM & SDK/board-support/ti-linux-kernel-6.6.32+git-ti/include/dt-bindings/mux/ti-serdes.h for SerDes lane configuration.

Can you please update the SerDes lane configuration as above from u-boot and Linux.

Best Regards,
Sudheer

I modified the serdes_ln_ctrl of k3-j721e-evm-ethfw. dtso, which is valid in the register.
I configured '0' QSGMII.
log to see CMN Timeout and register values and k3conf information.
How can this problem be solved? What other information do you need?

root@j721e-evm:~# dmesg | grep cdns-sierra-phy
[    2.179331] cdns-sierra-phy 5000000.serdes: Timeout waiting for PHY status ready
[    2.339766] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[    3.372775] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x00104080
/dev/mem opened.
Memory mapped at address 0xffffaccfe000.
Read at address  0x00104080 (0xffffaccfe080): 0x00000000
root@j721e-evm:~# devmem2 0x00104084
/dev/mem opened.
Memory mapped at address 0xffffb5f67000.
Read at address  0x00104084 (0xffffb5f67084): 0x00000000
root@j721e-evm:~# devmem2 0x00104090
/dev/mem opened.
Memory mapped at address 0xffff9156d000.
Read at address  0x00104090 (0xffff9156d090): 0x00000000
root@j721e-evm:~# devmem2 0x00104094
/dev/mem opened.
Memory mapped at address 0xffff8bada000.
Read at address  0x00104094 (0xffff8bada094): 0x00000000
root@j721e-evm:~#
root@j721e-evm:~# k3conf dump clock 293
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                             | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------------------------------------------|
|   293     |     0    | DEV_SERDES_16G1_CORE_REF1_CLK                                          | CLK_STATE_READY | 100000000       |
|   293     |     1    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
|   293     |     2    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   293     |     3    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153       |
|   293     |     4    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   293     |     5    | DEV_SERDES_16G1_CLK                                                    | CLK_STATE_READY | 125000000       |
|   293     |     6    | DEV_SERDES_16G1_IP1_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     7    | DEV_SERDES_16G1_IP2_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     8    | DEV_SERDES_16G1_IP4_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     9    | DEV_SERDES_16G1_IP4_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    10    | DEV_SERDES_16G1_IP3_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    11    | DEV_SERDES_16G1_IP2_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    12    | DEV_SERDES_16G1_IP1_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    13    | DEV_SERDES_16G1_CORE_REF_CLK                                           | CLK_STATE_READY | 100000000       |
|   293     |    14    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | CLK_STATE_READY | 19200000        |
|   293     |    15    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | CLK_STATE_READY | 0               |
|   293     |    16    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | CLK_STATE_READY | 153846153       |
|   293     |    17    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | CLK_STATE_READY | 100000000       |
|   293     |    18    | DEV_SERDES_16G1_IP2_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    19    | DEV_SERDES_16G1_IP1_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    20    | DEV_SERDES_16G1_IP4_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    21    | DEV_SERDES_16G1_IP3_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    22    | DEV_SERDES_16G1_IP3_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    23    | DEV_SERDES_16G1_IP1_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    24    | DEV_SERDES_16G1_IP2_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    25    | DEV_SERDES_16G1_IP2_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    26    | DEV_SERDES_16G1_REF_DER_OUT_CLK                                        | CLK_STATE_READY | 0               |
|   293     |    27    | DEV_SERDES_16G1_IP1_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    28    | DEV_SERDES_16G1_IP3_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    29    | DEV_SERDES_16G1_IP1_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    30    | DEV_SERDES_16G1_IP1_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    31    | DEV_SERDES_16G1_IP4_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    32    | DEV_SERDES_16G1_IP3_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    33    | DEV_SERDES_16G1_IP4_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    34    | DEV_SERDES_16G1_IP3_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    35    | DEV_SERDES_16G1_IP4_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    36    | DEV_SERDES_16G1_IP2_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    37    | DEV_SERDES_16G1_IP2_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    38    | DEV_SERDES_16G1_IP1_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    39    | DEV_SERDES_16G1_REF_OUT_CLK                                            | CLK_STATE_READY | 0               |
|   293     |    40    | DEV_SERDES_16G1_REF1_OUT_CLK                                           | CLK_STATE_READY | 0               |
|   293     |    41    | DEV_SERDES_16G1_IP4_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    42    | DEV_SERDES_16G1_IP1_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    43    | DEV_SERDES_16G1_IP1_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    44    | DEV_SERDES_16G1_IP4_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    45    | DEV_SERDES_16G1_IP4_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    46    | DEV_SERDES_16G1_IP2_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    47    | DEV_SERDES_16G1_IP2_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    48    | DEV_SERDES_16G1_IP4_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    49    | DEV_SERDES_16G1_IP2_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    50    | DEV_SERDES_16G1_IP2_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    51    | DEV_SERDES_16G1_IP1_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    52    | DEV_SERDES_16G1_IP2_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    53    | DEV_SERDES_16G1_IP4_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    54    | DEV_SERDES_16G1_IP1_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    55    | DEV_SERDES_16G1_IP4_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    60    | DEV_SERDES_16G1_CMN_REFCLK1_M                                          | CLK_STATE_READY | 0               |
|   293     |    67    | DEV_SERDES_16G1_CMN_REFCLK1_P                                          | CLK_STATE_READY | 0               |
|-----------------------------------------------------------------------------------------------------------------------------------|

root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x00108410
/dev/mem opened.
Memory mapped at address 0xffffacaaf000.
Read at address  0x00108410 (0xffffacaaf410): 0x00000003
root@j721e-evm:~# devmem2 0x05010408
/dev/mem opened.
Memory mapped at address 0xffffb9439000.
Read at address  0x05010408 (0xffffb9439408): 0x9A000000
root@j721e-evm:~# devmem2 0x0501040c
/dev/mem opened.
Memory mapped at address 0xffff8daa0000.
Read at address  0x0501040C (0xffff8daa040c): 0x92000000
root@j721e-evm:~# devmem2 0x05010480
/dev/mem opened.
Memory mapped at address 0xffffb95c7000.
Read at address  0x05010480 (0xffffb95c7480): 0x70800000
root@j721e-evm:~# devmem2 0x0501048c
/dev/mem opened.
Memory mapped at address 0xffffb98d5000.
Read at address  0x0501048C (0xffffb98d548c): 0x00000002
root@j721e-evm:~# devmem2 0x0501e000
/dev/mem opened.
Memory mapped at address 0xffff8a64c000.
Read at address  0x0501E000 (0xffff8a64c000): 0x00003010
root@j721e-evm:~#

Hi,

Let us check PLL locking on our side and update you with changes.

Best Regards,
Sudheer

Hi,

I have enabled SerDes1 node from device tree, and able to confirm PLL is locked.

Please find the changes in dtso for enabling SerDes1:



After making above changes in SDK, I have rebuild "linux-dtbs" and copied the updated dtbo to root directory of SD card ( I am using SD Boot mode)

Also, refer to the logs:

root@j721e-evm:~#  k3conf dump clock 293
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.1.6--v10.01.06 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|---------------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                             | Status              | Clock Frequency |
|---------------------------------------------------------------------------------------------------------------------------------------|
|   293     |     0    | DEV_SERDES_16G1_CORE_REF1_CLK                                          | CLK_STATE_READY     | 100000000       |
|   293     |     1    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY     | 19200000        |
|   293     |     2    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY     | 0               |
|   293     |     3    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY     | 153846153       |
|   293     |     4    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY     | 100000000       |
|   293     |     5    | DEV_SERDES_16G1_CLK                                                    | CLK_STATE_READY     | 125000000       |
|   293     |     6    | DEV_SERDES_16G1_IP1_LN0_TXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |     7    | DEV_SERDES_16G1_IP2_LN1_TXCLK                                          | CLK_STATE_NOT_READY | 0               |
|   293     |     8    | DEV_SERDES_16G1_IP4_LN1_TXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |     9    | DEV_SERDES_16G1_IP4_LN0_TXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    10    | DEV_SERDES_16G1_IP3_LN1_TXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    11    | DEV_SERDES_16G1_IP2_LN0_TXCLK                                          | CLK_STATE_NOT_READY | 0               |
|   293     |    12    | DEV_SERDES_16G1_IP1_LN1_TXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    13    | DEV_SERDES_16G1_CORE_REF_CLK                                           | CLK_STATE_READY     | 100000000       |
|   293     |    14    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | CLK_STATE_READY     | 19200000        |
|   293     |    15    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | CLK_STATE_READY     | 0               |
|   293     |    16    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | CLK_STATE_READY     | 153846153       |
|   293     |    17    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | CLK_STATE_READY     | 100000000       |
|   293     |    18    | DEV_SERDES_16G1_IP2_LN0_TXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    19    | DEV_SERDES_16G1_IP1_LN1_REFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    20    | DEV_SERDES_16G1_IP4_LN1_RXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    21    | DEV_SERDES_16G1_IP3_LN1_TXMCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    22    | DEV_SERDES_16G1_IP3_LN1_TXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    23    | DEV_SERDES_16G1_IP1_LN0_RXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    24    | DEV_SERDES_16G1_IP2_LN1_REFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    25    | DEV_SERDES_16G1_IP2_LN1_TXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    26    | DEV_SERDES_16G1_REF_DER_OUT_CLK                                        | CLK_STATE_READY     | 0               |
|   293     |    27    | DEV_SERDES_16G1_IP1_LN0_TXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    28    | DEV_SERDES_16G1_IP3_LN1_RXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    29    | DEV_SERDES_16G1_IP1_LN1_TXMCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    30    | DEV_SERDES_16G1_IP1_LN1_RXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    31    | DEV_SERDES_16G1_IP4_LN1_REFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    32    | DEV_SERDES_16G1_IP3_LN1_RXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    33    | DEV_SERDES_16G1_IP4_LN1_TXMCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    34    | DEV_SERDES_16G1_IP3_LN1_REFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    35    | DEV_SERDES_16G1_IP4_LN0_REFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    36    | DEV_SERDES_16G1_IP2_LN1_RXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    37    | DEV_SERDES_16G1_IP2_LN0_RXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    38    | DEV_SERDES_16G1_IP1_LN0_RXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    39    | DEV_SERDES_16G1_REF_OUT_CLK                                            | CLK_STATE_READY     | 0               |
|   293     |    40    | DEV_SERDES_16G1_REF1_OUT_CLK                                           | CLK_STATE_READY     | 0               |
|   293     |    41    | DEV_SERDES_16G1_IP4_LN1_RXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    42    | DEV_SERDES_16G1_IP1_LN0_REFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    43    | DEV_SERDES_16G1_IP1_LN0_TXMCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    44    | DEV_SERDES_16G1_IP4_LN0_TXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    45    | DEV_SERDES_16G1_IP4_LN0_RXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    46    | DEV_SERDES_16G1_IP2_LN1_RXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    47    | DEV_SERDES_16G1_IP2_LN1_TXMCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    48    | DEV_SERDES_16G1_IP4_LN0_RXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    49    | DEV_SERDES_16G1_IP2_LN0_REFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    50    | DEV_SERDES_16G1_IP2_LN0_TXMCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    51    | DEV_SERDES_16G1_IP1_LN1_TXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    52    | DEV_SERDES_16G1_IP2_LN0_RXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    53    | DEV_SERDES_16G1_IP4_LN0_TXMCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    54    | DEV_SERDES_16G1_IP1_LN1_RXCLK                                          | CLK_STATE_READY     | 0               |
|   293     |    55    | DEV_SERDES_16G1_IP4_LN1_TXFCLK                                         | CLK_STATE_READY     | 0               |
|   293     |    60    | DEV_SERDES_16G1_CMN_REFCLK1_M                                          | CLK_STATE_READY     | 0               |
|   293     |    67    | DEV_SERDES_16G1_CMN_REFCLK1_P                                          | CLK_STATE_READY     | 0               |
|---------------------------------------------------------------------------------------------------------------------------------------|

root@j721e-evm:~# devmem2 0x00108410
/dev/mem opened.
Memory mapped at address 0xffff92a65000.
Read at address  0x00108410 (0xffff92a65410): 0x00000003
root@j721e-evm:~# devmem2 0x05010408
/dev/mem opened.
Memory mapped at address 0xffffa6060000.
Read at address  0x05010408 (0xffffa6060408): 0x9A000000
root@j721e-evm:~# devmem2 0x0501040C
/dev/mem opened.
Memory mapped at address 0xffffa7ac2000.
Read at address  0x0501040C (0xffffa7ac240c): 0x92000000
root@j721e-evm:~# devmem2 0x05010480
/dev/mem opened.
Memory mapped at address 0xffff845b7000.
Read at address  0x05010480 (0xffff845b7480): 0x70000000
root@j721e-evm:~# devmem2 0x0501048C
/dev/mem opened.
Memory mapped at address 0xffff90fcc000.
Read at address  0x0501048C (0xffff90fcc48c): 0x00000003
root@j721e-evm:~# devmem2 0x0501e000
/dev/mem opened.
Memory mapped at address 0xffffa6c5d000.
Read at address  0x0501E000 (0xffffa6c5d000): 0x00002435
root@j721e-evm:~# devmem2 0x0500e000  

In your case I can observe both plls are disabled from PHY_CMN_CTL register (0x0501E000)

PLL locking is not related to Interface selection, it will be based on clock mapping in device tree.

Best Regards,
Sudheer

Modify the device tree according to your requirements. I can see that all Clock states are already CLK_STATE_READY.
However, the value of 0x0501e000 remains 0x00003010.

root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep cdns-sierra-phy
[    2.178998] cdns-sierra-phy 5000000.serdes: Timeout waiting for PHY status ready
[    2.338685] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[    3.372702] cdns-sierra-phy 5010000.serdes: Timeout waiting for CMN ready
root@j721e-evm:~#
root@j721e-evm:~# k3conf dump clock 293
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                             | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------------------------------------------|
|   293     |     0    | DEV_SERDES_16G1_CORE_REF1_CLK                                          | CLK_STATE_READY | 100000000       |
|   293     |     1    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
|   293     |     2    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   293     |     3    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153       |
|   293     |     4    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   293     |     5    | DEV_SERDES_16G1_CLK                                                    | CLK_STATE_READY | 125000000       |
|   293     |     6    | DEV_SERDES_16G1_IP1_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     7    | DEV_SERDES_16G1_IP2_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     8    | DEV_SERDES_16G1_IP4_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     9    | DEV_SERDES_16G1_IP4_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    10    | DEV_SERDES_16G1_IP3_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    11    | DEV_SERDES_16G1_IP2_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    12    | DEV_SERDES_16G1_IP1_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    13    | DEV_SERDES_16G1_CORE_REF_CLK                                           | CLK_STATE_READY | 100000000       |
|   293     |    14    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | CLK_STATE_READY | 19200000        |
|   293     |    15    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | CLK_STATE_READY | 0               |
|   293     |    16    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | CLK_STATE_READY | 153846153       |
|   293     |    17    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | CLK_STATE_READY | 100000000       |
|   293     |    18    | DEV_SERDES_16G1_IP2_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    19    | DEV_SERDES_16G1_IP1_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    20    | DEV_SERDES_16G1_IP4_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    21    | DEV_SERDES_16G1_IP3_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    22    | DEV_SERDES_16G1_IP3_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    23    | DEV_SERDES_16G1_IP1_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    24    | DEV_SERDES_16G1_IP2_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    25    | DEV_SERDES_16G1_IP2_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    26    | DEV_SERDES_16G1_REF_DER_OUT_CLK                                        | CLK_STATE_READY | 0               |
|   293     |    27    | DEV_SERDES_16G1_IP1_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    28    | DEV_SERDES_16G1_IP3_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    29    | DEV_SERDES_16G1_IP1_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    30    | DEV_SERDES_16G1_IP1_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    31    | DEV_SERDES_16G1_IP4_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    32    | DEV_SERDES_16G1_IP3_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    33    | DEV_SERDES_16G1_IP4_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    34    | DEV_SERDES_16G1_IP3_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    35    | DEV_SERDES_16G1_IP4_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    36    | DEV_SERDES_16G1_IP2_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    37    | DEV_SERDES_16G1_IP2_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    38    | DEV_SERDES_16G1_IP1_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    39    | DEV_SERDES_16G1_REF_OUT_CLK                                            | CLK_STATE_READY | 0               |
|   293     |    40    | DEV_SERDES_16G1_REF1_OUT_CLK                                           | CLK_STATE_READY | 0               |
|   293     |    41    | DEV_SERDES_16G1_IP4_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    42    | DEV_SERDES_16G1_IP1_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    43    | DEV_SERDES_16G1_IP1_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    44    | DEV_SERDES_16G1_IP4_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    45    | DEV_SERDES_16G1_IP4_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    46    | DEV_SERDES_16G1_IP2_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    47    | DEV_SERDES_16G1_IP2_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    48    | DEV_SERDES_16G1_IP4_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    49    | DEV_SERDES_16G1_IP2_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    50    | DEV_SERDES_16G1_IP2_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    51    | DEV_SERDES_16G1_IP1_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    52    | DEV_SERDES_16G1_IP2_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    53    | DEV_SERDES_16G1_IP4_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    54    | DEV_SERDES_16G1_IP1_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    55    | DEV_SERDES_16G1_IP4_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    60    | DEV_SERDES_16G1_CMN_REFCLK1_M                                          | CLK_STATE_READY | 0               |
|   293     |    67    | DEV_SERDES_16G1_CMN_REFCLK1_P                                          | CLK_STATE_READY | 0               |
|-----------------------------------------------------------------------------------------------------------------------------------|

root@j721e-evm:~# devmem2 0x00104090
/dev/mem opened.
Memory mapped at address 0xffff99a30000.
Read at address  0x00104090 (0xffff99a30090): 0x00000000
root@j721e-evm:~# devmem2 0x00104094
/dev/mem opened.
Memory mapped at address 0xffffa36e6000.
Read at address  0x00104094 (0xffffa36e6094): 0x00000000
root@j721e-evm:~# devmem2 0x00108410
/dev/mem opened.
Memory mapped at address 0xffff8ee68000.
Read at address  0x00108410 (0xffff8ee68410): 0x00000003
root@j721e-evm:~# devmem2 0x05010408
/dev/mem opened.
Memory mapped at address 0xffffb6a0c000.
Read at address  0x05010408 (0xffffb6a0c408): 0x9A000000
root@j721e-evm:~# devmem2 0x0501040c
/dev/mem opened.
Memory mapped at address 0xffffa267b000.
Read at address  0x0501040C (0xffffa267b40c): 0x92000000
root@j721e-evm:~# devmem2 0x05010480
/dev/mem opened.
Memory mapped at address 0xffff9ea9a000.
Read at address  0x05010480 (0xffff9ea9a480): 0x70800000
root@j721e-evm:~# devmem2 0x0501048c
/dev/mem opened.
Memory mapped at address 0xffff80729000.
Read at address  0x0501048C (0xffff8072948c): 0x00000002
root@j721e-evm:~# devmem2 0x0501e000
/dev/mem opened.
Memory mapped at address 0xffffa96d0000.
Read at address  0x0501E000 (0xffffa96d0000): 0x00003010
root@j721e-evm:~#

Hi,

Can you dump above information without adding links in serdes1 node as I have shared above (no interface selection and no map to CPSW)

Best Regards,
Sudheer

This is the modified detailed log.

root@j721e-evm:~# devmem2 0x00104090
/dev/mem opened.
Memory mapped at address 0xffffa7e83000.
Read at address  0x00104090 (0xffffa7e83090): 0x00000000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x00104094
/dev/mem opened.
Memory mapped at address 0xffffb4f47000.
Read at address  0x00104094 (0xffffb4f47094): 0x00000000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x00108410
/dev/mem opened.
Memory mapped at address 0xffff8aa92000.
Read at address  0x00108410 (0xffff8aa92410): 0x00000003
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x05010408
/dev/mem opened.
Memory mapped at address 0xffffb9de9000.
Read at address  0x05010408 (0xffffb9de9408): 0x9A000000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x0501040C
/dev/mem opened.
Memory mapped at address 0xffffa24fe000.
Read at address  0x0501040C (0xffffa24fe40c): 0x12000000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x05010480
/dev/mem opened.
Memory mapped at address 0xffff93052000.
Read at address  0x05010480 (0xffff93052480): 0x30000000
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x0501048C
/dev/mem opened.
Memory mapped at address 0xffff8510a000.
Read at address  0x0501048C (0xffff8510a48c): 0x00000002
root@j721e-evm:~#
root@j721e-evm:~# devmem2 0x0501e000
/dev/mem opened.
Memory mapped at address 0xffffbb931000.
Read at address  0x0501E000 (0xffffbb931000): 0x00003010
root@j721e-evm:~#
root@j721e-evm:~# ifconfig
eth0: flags=4099<UP,BROADCAST,MULTICAST>  mtu 1500
        ether ec:bf:d0:bb:1e:47  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 18  bytes 2180 (2.1 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 18  bytes 2180 (2.1 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
		
root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep c00000
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 96 MiB
[    0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@ac000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x00000000ac000000..0x00000000b1ffffff (98304 KiB) nomap non-reusable vision-apps-dma-memory@ac000000
[    1.200372] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    1.210547] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.217310] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    2.007377] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA01901, cpsw version 0x6BA80101 Ports: 9 quirks:00000000
[    2.020071] am65-cpsw-nuss c000000.ethernet: /bus@100000/ethernet@c000000/ethernet-ports/port@3 error retrieving port phy: -19
[    9.596939] platform 5c00000.r5f: configured R5F for IPC-only mode
[    9.609557] platform 5c00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a2000000
[    9.627364] remoteproc remoteproc4: 5c00000.r5f is available
[    9.640456] remoteproc remoteproc4: attaching to 5c00000.r5f
[    9.665496] platform 5c00000.r5f: R5F core initialized in IPC-only mode
[    9.730194] remoteproc remoteproc4: remote processor 5c00000.r5f is now attached
[   12.963720] audit: type=1300 audit(1709060036.136:14): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=fffff1a46ef8 a2=4 a3=1 items=0 ppid=1 pid=654 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=1 comm="(systemd)" exe="/usr/lib/systemd/systemd-executor" key=(null)
[   13.870763] audit: type=1300 audit(1709060037.048:15): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=fffffb49d378 a2=4 a3=1 items=0 ppid=1 pid=566 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=tty7 ses=2 comm="(weston)" exe="/usr/lib/systemd/systemd-executor" key=(null)
[   21.183531] audit: type=1300 audit(1709060044.360:16): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=ffffd9025808 a2=1 a3=1 items=0 ppid=1 pid=1063 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/usr/lib/systemd/systemd-executor" key=(null)
[   21.224310] audit: type=1300 audit(1709060044.376:17): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffdb5f73f8 a2=90 a3=0 items=0 ppid=1 pid=1063 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)
[   21.264295] audit: type=1300 audit(1709060044.400:18): arch=c00000b7 syscall=57 success=yes exit=0 a0=8 a1=1 a2=0 a3=ffffbe23ec60 items=0 ppid=1 pid=1063 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/usr/lib/systemd/systemd" key=(null)
root@j721e-evm:~#
root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep error
[    1.133348] j721e-pcie 2910000.pcie: error -ENODEV: Failed to init phy
[    2.020071] am65-cpsw-nuss c000000.ethernet: /bus@100000/ethernet@c000000/ethernet-ports/port@3 error retrieving port phy: -19
[   10.716998] remoteproc remoteproc6: loading /lib/firmware/j7-main-r5f1_0-fw failed with error -22
[   10.725931] remoteproc remoteproc6: Direct firmware load for j7-main-r5f1_0-fw failed with error -22
[   10.741902] remoteproc remoteproc6: loading /lib/firmware/j7-main-r5f1_0-fw failed with error -22
[   10.750887] remoteproc remoteproc6: Direct firmware load for j7-main-r5f1_0-fw failed with error -22
root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep fail
[   10.716998] remoteproc remoteproc6: loading /lib/firmware/j7-main-r5f1_0-fw failed with error -22
[   10.725931] remoteproc remoteproc6: Direct firmware load for j7-main-r5f1_0-fw failed with error -22
[   10.741902] remoteproc remoteproc6: loading /lib/firmware/j7-main-r5f1_0-fw failed with error -22
[   10.750887] remoteproc remoteproc6: Direct firmware load for j7-main-r5f1_0-fw failed with error -22
[   10.761856] remoteproc remoteproc6: request_firmware failed: -22
root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep cdns-sierra-phy
root@j721e-evm:~#
root@j721e-evm:~# dmesg | grep serdes
[   22.192334] platform 5010000.serdes: deferred probe pending
root@j721e-evm:~#
root@j721e-evm:~# k3conf dump clock 293
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                             | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------------------------------------------|
|   293     |     0    | DEV_SERDES_16G1_CORE_REF1_CLK                                          | CLK_STATE_READY | 100000000       |
|   293     |     1    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
|   293     |     2    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   293     |     3    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153       |
|   293     |     4    | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   293     |     5    | DEV_SERDES_16G1_CLK                                                    | CLK_STATE_READY | 125000000       |
|   293     |     6    | DEV_SERDES_16G1_IP1_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     7    | DEV_SERDES_16G1_IP2_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     8    | DEV_SERDES_16G1_IP4_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |     9    | DEV_SERDES_16G1_IP4_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    10    | DEV_SERDES_16G1_IP3_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    11    | DEV_SERDES_16G1_IP2_LN0_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    12    | DEV_SERDES_16G1_IP1_LN1_TXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    13    | DEV_SERDES_16G1_CORE_REF_CLK                                           | CLK_STATE_READY | 100000000       |
|   293     |    14    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | CLK_STATE_READY | 19200000        |
|   293     |    15    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | CLK_STATE_READY | 0               |
|   293     |    16    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | CLK_STATE_READY | 153846153       |
|   293     |    17    | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | CLK_STATE_READY | 100000000       |
|   293     |    18    | DEV_SERDES_16G1_IP2_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    19    | DEV_SERDES_16G1_IP1_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    20    | DEV_SERDES_16G1_IP4_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    21    | DEV_SERDES_16G1_IP3_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    22    | DEV_SERDES_16G1_IP3_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    23    | DEV_SERDES_16G1_IP1_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    24    | DEV_SERDES_16G1_IP2_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    25    | DEV_SERDES_16G1_IP2_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    26    | DEV_SERDES_16G1_REF_DER_OUT_CLK                                        | CLK_STATE_READY | 0               |
|   293     |    27    | DEV_SERDES_16G1_IP1_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    28    | DEV_SERDES_16G1_IP3_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    29    | DEV_SERDES_16G1_IP1_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    30    | DEV_SERDES_16G1_IP1_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    31    | DEV_SERDES_16G1_IP4_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    32    | DEV_SERDES_16G1_IP3_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    33    | DEV_SERDES_16G1_IP4_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    34    | DEV_SERDES_16G1_IP3_LN1_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    35    | DEV_SERDES_16G1_IP4_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    36    | DEV_SERDES_16G1_IP2_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    37    | DEV_SERDES_16G1_IP2_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    38    | DEV_SERDES_16G1_IP1_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    39    | DEV_SERDES_16G1_REF_OUT_CLK                                            | CLK_STATE_READY | 0               |
|   293     |    40    | DEV_SERDES_16G1_REF1_OUT_CLK                                           | CLK_STATE_READY | 0               |
|   293     |    41    | DEV_SERDES_16G1_IP4_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    42    | DEV_SERDES_16G1_IP1_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    43    | DEV_SERDES_16G1_IP1_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    44    | DEV_SERDES_16G1_IP4_LN0_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    45    | DEV_SERDES_16G1_IP4_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    46    | DEV_SERDES_16G1_IP2_LN1_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    47    | DEV_SERDES_16G1_IP2_LN1_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    48    | DEV_SERDES_16G1_IP4_LN0_RXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    49    | DEV_SERDES_16G1_IP2_LN0_REFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    50    | DEV_SERDES_16G1_IP2_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    51    | DEV_SERDES_16G1_IP1_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    52    | DEV_SERDES_16G1_IP2_LN0_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    53    | DEV_SERDES_16G1_IP4_LN0_TXMCLK                                         | CLK_STATE_READY | 0               |
|   293     |    54    | DEV_SERDES_16G1_IP1_LN1_RXCLK                                          | CLK_STATE_READY | 0               |
|   293     |    55    | DEV_SERDES_16G1_IP4_LN1_TXFCLK                                         | CLK_STATE_READY | 0               |
|   293     |    60    | DEV_SERDES_16G1_CMN_REFCLK1_M                                          | CLK_STATE_READY | 0               |
|   293     |    67    | DEV_SERDES_16G1_CMN_REFCLK1_P                                          | CLK_STATE_READY | 0               |
|-----------------------------------------------------------------------------------------------------------------------------------|

root@j721e-evm:~#

Hi,

From above logs, it seems like probe itself failed for SerDes.
[   22.192334] platform 5010000.serdes: deferred probe pending

Can you please share the SerDes configuration used here.

Best Regards,
Sudheer

Is this a configuration you need to check?

		wiz@5010000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			power-domains = <0x08 0x125 0x01>;
			clocks = <0x07 0x125 0x05 0x07 0x125 0x0d 0x27>;
			clock-names = "fck\0core_ref_clk\0ext_ref_clk";
			assigned-clocks = <0x07 0x125 0x0d 0x07 0x125 0x00>;
			assigned-clock-parents = <0x07 0x125 0x11 0x07 0x125 0x04>;
			num-lanes = <0x02>;
			#reset-cells = <0x01>;
			ranges = <0x5010000 0x00 0x5010000 0x10000>;
			status = "okay";
			phandle = <0x33>;

			pll0-refclk {
				clocks = <0x07 0x125 0x0d 0x27>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x30>;
				assigned-clock-parents = <0x07 0x125 0x0d>;
				phandle = <0x30>;
			};

			pll1-refclk {
				clocks = <0x07 0x125 0x00 0x29>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x31>;
				assigned-clock-parents = <0x29>;
				phandle = <0x31>;
			};

			refclk-dig {
				clocks = <0x07 0x125 0x0d 0x07 0x125 0x00 0x27 0x29>;
				#clock-cells = <0x00>;
				assigned-clocks = <0x32>;
				assigned-clock-parents = <0x29>;
				phandle = <0x32>;
			};

			cmn-refclk-dig-div {
				clocks = <0x32>;
				#clock-cells = <0x00>;
				phandle = <0x34>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x31>;
				#clock-cells = <0x00>;
				phandle = <0x35>;
			};

			serdes@5010000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5010000 0x10000>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				#clock-cells = <0x01>;
				resets = <0x33 0x00>;
				reset-names = "sierra_reset";
				clocks = <0x34 0x35 0x30 0x31>;
				clock-names = "cmn_refclk_dig_div\0cmn_refclk1_dig_div\0pll0_refclk\0pll1_refclk";
				status = "okay";
				assigned-clocks = <0x2f 0x00 0x2f 0x01>;
				assigned-clock-parents = <0x2a 0x2a>;
				phandle = <0xe3>;
			};
		};
		
		
		
		ethernet@c000000 {
			compatible = "ti,j721e-cpswxg-nuss";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			reg = <0x00 0xc000000 0x00 0x200000>;
			reg-names = "cpsw_nuss";
			ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
			clocks = <0x07 0x13 0x59>;
			clock-names = "fck";
			power-domains = <0x08 0x13 0x01>;
			dmas = <0x10 0xca00 0x10 0xca01 0x10 0xca02 0x10 0xca03 0x10 0xca04 0x10 0xca05 0x10 0xca06 0x10 0xca07 0x10 0x4a00>;
			dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";
			status = "okay";
			phandle = <0xc1>;

			ethernet-ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@1 {
					reg = <0x01>;
					ti,mac-only;
					label = "port1";
					status = "disabled";
					phandle = <0xc2>;
				};

				port@2 {
					reg = <0x02>;
					ti,mac-only;
					label = "port2";
					status = "disabled";
					phandle = <0xc3>;
				};

				port@3 {
					reg = <0x03>;
					ti,mac-only;
					label = "port3";
					phandle = <0xc4>;
				};

				port@4 {
					reg = <0x04>;
					ti,mac-only;
					label = "port4";
					status = "disabled";
					phandle = <0xc5>;
				};

				port@5 {
					reg = <0x05>;
					ti,mac-only;
					label = "port5";
					status = "disabled";
					phandle = <0xc6>;
				};

				port@6 {
					reg = <0x06>;
					ti,mac-only;
					label = "port6";
					status = "disabled";
					phandle = <0xc7>;
				};

				port@7 {
					reg = <0x07>;
					ti,mac-only;
					label = "port7";
					status = "disabled";
					phandle = <0xc8>;
				};

				port@8 {
					reg = <0x08>;
					ti,mac-only;
					label = "port8";
					status = "disabled";
					phandle = <0xc9>;
				};
			};

			mdio@f00 {
				compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
				reg = <0x00 0xf00 0x00 0x100>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clocks = <0x07 0x13 0x59>;
				clock-names = "fck";
				bus_freq = <0xf4240>;
				status = "okay";
				phandle = <0xca>;
			};

			cpts@3d000 {
				compatible = "ti,j721e-cpts";
				reg = <0x00 0x3d000 0x00 0x400>;
				clocks = <0x07 0x13 0x10>;
				clock-names = "cpts";
				interrupts-extended = <0x01 0x00 0x10 0x04>;
				interrupt-names = "cpts";
				ti,cpts-ext-ts-inputs = <0x04>;
				ti,cpts-periodic-outputs = <0x02>;
			};
		};

Hi,

Can you share the device tree source files (dtsi, dts and dtso files)

Best Regards,
Sudheer

k3-j721e-evm-ethfw.dtso

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
 * DT Overlay for CPSW9G functionality with Ethernet Switch Firmware (EthFw)
 * and CPSW Proxy Client driver.
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include "k3-serdes.h"

&serdes_ln_ctrl {
	idle-states = <0x0>, <0x0>,
		      <0x0>, <0x0>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

/* uart2 is assigned to EthFw running on remote CPU core */
&main_uart2 {
	status = "reserved";
};

/* Reserve shared memory for inter-core network communication */
&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;

	main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@ac000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xac000000 0x00 0x200000>;
		no-map;
	};

	main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@ac200000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xac200000 0x00 0x1e00000>;
		no-map;
	};
};

&main_r5fss0_core0 {
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>,
			<&main_r5fss0_core0_shared_memory_queue_region>,
			<&main_r5fss0_core0_shared_memory_bufpool_region>;
};

/* EthFw uses timers so mark them reserved */
&main_timer12 {
	status = "reserved";
};

&main_timer13 {
	status = "reserved";
};

k3-j721e-main.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721E SoC Family Main Domain peripherals
 *
 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
 */
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-ti.h>
#include <dt-bindings/mux/mux.h>

#include "k3-serdes.h"

/ {
	cmn_refclk: clock-cmnrefclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	cmn_refclk1: clock-cmnrefclk1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};
};

&cbass_main {
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x800000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x800000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};
	};

	scm_conf: scm-conf@100000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x00100000 0x1c000>;

		serdes_ln_ctrl: mux-controller@4080 {
			compatible = "reg-mux";
			reg = <0x4080 0x50>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
					<0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
					<0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
					<0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
					<0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
					<0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
			idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
				      <J721E_SERDES1_LANE0_SGMII_LANE0>, <J721E_SERDES1_LANE1_SGMII_LANE1>,
				      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
				      <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
				      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
				      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
		};

		cpsw0_phy_gmii_sel: phy@4044 {
			compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
			ti,qsgmii-main-ports = <2>, <2>;
			reg = <0x4044 0x20>;
			#phy-cells = <1>;
		};

		usb_serdes_mux: mux-controller@4000 {
			compatible = "reg-mux";
			reg = <0x4000 0x20>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
					<0x10 0x8000000>; /* USB1 to SERDES1/2 mux */
		};

		ehrpwm_tbclk: clock-controller@4140 {
			compatible = "ti,am654-ehrpwm-tbclk";
			reg = <0x4140 0x18>;
			#clock-cells = <1>;
		};
	};

	main_ehrpwm0: pwm@3000000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3000000 0x00 0x100>;
		power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm1: pwm@3010000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3010000 0x00 0x100>;
		power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm2: pwm@3020000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3020000 0x00 0x100>;
		power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm3: pwm@3030000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3030000 0x00 0x100>;
		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm4: pwm@3040000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3040000 0x00 0x100>;
		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	main_ehrpwm5: pwm@3050000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3050000 0x00 0x100>;
		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
		clock-names = "tbclk", "fck";
		status = "disabled";
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
		      <0x00 0x01900000 0x00 0x100000>,	/* GICR */
		      <0x00 0x6f000000 0x00 0x2000>,	/* GICC */
		      <0x00 0x6f010000 0x00 0x1000>,	/* GICH */
		      <0x00 0x6f020000 0x00 0x2000>;	/* GICV */

		/* vcpumntirq: virtual CPU interface maintenance interrupt */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	main_gpio_intr: interrupt-controller@a00000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x00a00000 0x00 0x800>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <131>;
		ti,interrupt-ranges = <8 392 56>;
	};

	main_navss: bus@30000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
		dma-coherent;
		dma-ranges;

		ti,sci-dev-id = <199>;

		main_navss_intr: interrupt-controller@310e0000 {
			compatible = "ti,sci-intr";
			reg = <0x0 0x310e0000 0x0 0x4000>;
			ti,intr-trigger-type = <4>;
			interrupt-controller;
			interrupt-parent = <&gic500>;
			#interrupt-cells = <1>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <213>;
			ti,interrupt-ranges = <0 64 64>,
					      <64 448 64>,
					      <128 672 64>;
		};

		main_udmass_inta: interrupt-controller@33d00000 {
			compatible = "ti,sci-inta";
			reg = <0x0 0x33d00000 0x0 0x100000>;
			interrupt-controller;
			interrupt-parent = <&main_navss_intr>;
			msi-controller;
			#interrupt-cells = <0>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <209>;
			ti,interrupt-ranges = <0 0 256>;
		};

		secure_proxy_main: mailbox@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x32c00000 0x00 0x100000>,
			      <0x00 0x32400000 0x00 0x100000>,
			      <0x00 0x32800000 0x00 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		smmu0: iommu@36600000 {
			compatible = "arm,smmu-v3";
			reg = <0x0 0x36600000 0x0 0x100000>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			#iommu-cells = <1>;
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x00 0x30e00000 0x00 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f81000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f82000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f83000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f84000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f85000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f86000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f87000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f88000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f89000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		mailbox0_cluster11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			status = "disabled";
		};

		main_ringacc: ringacc@3c000000 {
			compatible = "ti,am654-navss-ringacc";
			reg = <0x0 0x3c000000 0x0 0x400000>,
			      <0x0 0x38000000 0x0 0x400000>,
			      <0x0 0x31120000 0x0 0x100>,
			      <0x0 0x33000000 0x0 0x40000>,
			      <0x0 0x31080000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
			ti,num-rings = <1024>;
			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <211>;
			msi-parent = <&main_udmass_inta>;
		};

		main_udmap: dma-controller@31150000 {
			compatible = "ti,j721e-navss-main-udmap";
			reg = <0x0 0x31150000 0x0 0x100>,
			      <0x0 0x34000000 0x0 0x100000>,
			      <0x0 0x35000000 0x0 0x100000>,
			      <0x0 0x30b00000 0x0 0x20000>,
			      <0x0 0x30c00000 0x0 0x10000>,
			      <0x0 0x30d00000 0x0 0x8000>;
			reg-names = "gcfg", "rchanrt", "tchanrt",
				    "tchan", "rchan", "rflow";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&dmsc>;
			ti,sci-dev-id = <212>;
			ti,ringacc = <&main_ringacc>;

			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>, /* TX_HCHAN */
						<0x10>; /* TX_UHCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>, /* RX_HCHAN */
						<0x0c>; /* RX_UHCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};

		cpts@310d0000 {
			compatible = "ti,j721e-cpts";
			reg = <0x0 0x310d0000 0x0 0x400>;
			reg-names = "cpts";
			clocks = <&k3_clks 201 1>;
			clock-names = "cpts";
			interrupts-extended = <&main_navss_intr 391>;
			interrupt-names = "cpts";
			ti,cpts-periodic-outputs = <6>;
			ti,cpts-ext-ts-inputs = <8>;
		};
	};

	cpsw0: ethernet@c000000 {
		compatible = "ti,j721e-cpswxg-nuss";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x0 0xc000000 0x0 0x200000>;
		reg-names = "cpsw_nuss";
		ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
		clocks = <&k3_clks 19 89>;
		clock-names = "fck";
		power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			cpsw0_port1: port@1 {
				reg = <1>;
				ti,mac-only;
				label = "port1";
				status = "disabled";
			};

			cpsw0_port2: port@2 {
				reg = <2>;
				ti,mac-only;
				label = "port2";
				status = "disabled";
			};

			cpsw0_port3: port@3 {
				reg = <3>;
				ti,mac-only;
				label = "port3";
			};

			cpsw0_port4: port@4 {
				reg = <4>;
				ti,mac-only;
				label = "port4";
				status = "disabled";
			};

			cpsw0_port5: port@5 {
				reg = <5>;
				ti,mac-only;
				label = "port5";
				status = "disabled";
			};

			cpsw0_port6: port@6 {
				reg = <6>;
				ti,mac-only;
				label = "port6";
				status = "disabled";
			};

			cpsw0_port7: port@7 {
				reg = <7>;
				ti,mac-only;
				label = "port7";
				status = "disabled";
			};

			cpsw0_port8: port@8 {
				reg = <8>;
				ti,mac-only;
				label = "port8";
				status = "disabled";
			};
		};

		cpsw9g_mdio: mdio@f00 {
			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
			reg = <0x0 0xf00 0x0 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k3_clks 19 89>;
			clock-names = "fck";
			bus_freq = <1000000>;
		};

		cpts@3d000 {
			compatible = "ti,j721e-cpts";
			reg = <0x0 0x3d000 0x0 0x400>;
			clocks = <&k3_clks 19 16>;
			clock-names = "cpts";
			interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cpts";
			ti,cpts-ext-ts-inputs = <4>;
			ti,cpts-periodic-outputs = <2>;
		};
	};

	main_crypto: crypto@4e00000 {
		compatible = "ti,j721e-sa2ul";
		reg = <0x0 0x4e00000 0x0 0x1200>;
		power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;

		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
				<&main_udmap 0x4001>;
		dma-names = "tx", "rx1", "rx2";

		rng: rng@4e10000 {
			compatible = "inside-secure,safexcel-eip76";
			reg = <0x0 0x4e10000 0x0 0x7d>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	main_pmx0: pinctrl@11c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x0 0x11c000 0x0 0x2b4>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
	main_timerio_input: pinctrl@104200 {
		compatible = "pinctrl-single";
		reg = <0x00 0x104200 0x00 0x50>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x00000007>;
	};

	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
	main_timerio_output: pinctrl@104280 {
		compatible = "pinctrl-single";
		reg = <0x00 0x104280 0x00 0x20>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x0000001f>;
	};

	ti_csi2rx0: ticsi2rx@4500000 {
		compatible = "ti,j721e-csi2rx-shim";
		reg = <0x0 0x4500000 0x0 0x1000>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>, <&main_udmap 0x4942>,
		       <&main_udmap 0x4943>, <&main_udmap 0x4944>, <&main_udmap 0x4945>,
		       <&main_udmap 0x4946>, <&main_udmap 0x4947>, <&main_udmap 0x4948>,
		       <&main_udmap 0x4949>, <&main_udmap 0x494a>, <&main_udmap 0x494b>,
		       <&main_udmap 0x494c>, <&main_udmap 0x494d>, <&main_udmap 0x494e>,
		       <&main_udmap 0x494f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";

		cdns_csi2rx0: csi-bridge@4504000 {
			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
			reg = <0x0 0x4504000 0x0 0x1000>;
			clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
				 <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				      "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy0>;
			phy-names = "dphy";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi0_port0: port@0 {
					reg = <0>;
					status = "disabled";
				};

				csi0_port1: port@1 {
					reg = <1>;
					status = "disabled";
				};

				csi0_port2: port@2 {
					reg = <2>;
					status = "disabled";
				};

				csi0_port3: port@3 {
					reg = <3>;
					status = "disabled";
				};

				csi0_port4: port@4 {
					reg = <4>;
					status = "disabled";
				};
			};
		};
	};

	ti_csi2rx1: ticsi2rx@4510000 {
		compatible = "ti,j721e-csi2rx-shim";
		reg = <0x0 0x4510000 0x0 0x1000>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		dmas = <&main_udmap 0x4960>, <&main_udmap 0x4961>, <&main_udmap 0x4962>,
		       <&main_udmap 0x4963>, <&main_udmap 0x4964>, <&main_udmap 0x4965>,
		       <&main_udmap 0x4966>, <&main_udmap 0x4967>, <&main_udmap 0x4968>,
		       <&main_udmap 0x4969>, <&main_udmap 0x496a>, <&main_udmap 0x496b>,
		       <&main_udmap 0x496c>, <&main_udmap 0x496d>, <&main_udmap 0x496e>,
		       <&main_udmap 0x496f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";

		cdns_csi2rx1: csi-bridge@4514000 {
			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
			reg = <0x0 0x4514000 0x0 0x1000>;
			clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
				 <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				      "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy1>;
			phy-names = "dphy";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi1_port0: port@0 {
					reg = <0>;
					status = "disabled";
				};

				csi1_port1: port@1 {
					reg = <1>;
					status = "disabled";
				};

				csi1_port2: port@2 {
					reg = <2>;
					status = "disabled";
				};

				csi1_port3: port@3 {
					reg = <3>;
					status = "disabled";
				};

				csi1_port4: port@4 {
					reg = <4>;
					status = "disabled";
				};
			};
		};
	};

	dphy0: phy@4580000 {
		compatible = "cdns,dphy-rx";
		reg = <0x0 0x4580000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	dphy1: phy@4590000 {
		compatible = "cdns,dphy-rx";
		reg = <0x0 0x4590000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	serdes_wiz0: wiz@5000000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5000000 0x0 0x5000000 0x10000>;
		status = "disabled";

		wiz0_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 292 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 292 0>;
		};

		wiz0_refclk_dig: refclk-dig {
			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_refclk_dig>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz0_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz0_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes0: serdes@5000000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5000000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz0 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
				 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
				      "pll0_refclk", "pll1_refclk";
			status = "disabled";
		};
	};

	serdes_wiz1: wiz@5010000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5010000 0x0 0x5010000 0x10000>;
		status = "okay";

		wiz1_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 293 13>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 293 0>;
		};

		wiz1_refclk_dig: refclk-dig {
			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_refclk_dig>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz1_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz1_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes1: serdes@5010000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5010000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz1 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
				 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
				      "pll0_refclk", "pll1_refclk";
			status = "okay";
		};
	};

	serdes_wiz2: wiz@5020000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5020000 0x0 0x5020000 0x10000>;
		status = "disabled";

		wiz2_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 294 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 294 0>;
		};

		wiz2_refclk_dig: refclk-dig {
			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_refclk_dig>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz2_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz2_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes2: serdes@5020000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5020000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz2 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
				 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
				      "pll0_refclk", "pll1_refclk";
			status = "disabled";
		};
	};

	serdes_wiz3: wiz@5030000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5030000 0x0 0x5030000 0x10000>;

		wiz3_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 295 9>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 295 0>;
		};

		wiz3_refclk_dig: refclk-dig {
			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_refclk_dig>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz3_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz3_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes3: serdes@5030000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5030000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz3 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
				 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
				      "pll0_refclk", "pll1_refclk";
		};
	};

	pcie0_rc: pcie@2900000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02900000 0x00 0x1000>,
		      <0x00 0x02907000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x00 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 239 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		status = "disabled";
	};

	pcie1_rc: pcie@2910000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 240 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x10000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		status = "disabled";
	};

	pcie2_rc: pcie@2920000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 241 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x20000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		status = "disabled";
	};

	pcie3_rc: pcie@2930000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02930000 0x00 0x1000>,
		      <0x00 0x02937000 0x00 0x400>,
		      <0x00 0x0e800000 0x00 0x00800000>,
		      <0x44 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 242 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x30000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		status = "disabled";
	};

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,am64-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 10>;
		assigned-clock-rates = <19200000>;
		num-lanes = <4>;
		#reset-cells = <1>;
		#clock-cells = <1>;
		ranges = <0x05050000 0x00 0x05050000 0x010000>,
			<0x0a030a00 0x00 0x0a030a00 0x40>;

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x05050000 0x010000>,
			      <0x0a030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
			clock-names = "refclk";
			assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
					  <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
					  <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
			assigned-clock-parents = <&k3_clks 297 9>,
						 <&k3_clks 297 9>,
						 <&k3_clks 297 9>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	main_timer0: timer@2400000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2400000 0x00 0x400>;
		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 49 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 49 1>;
		assigned-clock-parents = <&k3_clks 49 2>;
		power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer1: timer@2410000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2410000 0x00 0x400>;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 50 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
		assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
		power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer2: timer@2420000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2420000 0x00 0x400>;
		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 51 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 51 1>;
		assigned-clock-parents = <&k3_clks 51 2>;
		power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer3: timer@2430000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2430000 0x00 0x400>;
		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 52 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
		assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
		power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer4: timer@2440000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2440000 0x00 0x400>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 53 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 53 1>;
		assigned-clock-parents = <&k3_clks 53 2>;
		power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer5: timer@2450000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2450000 0x00 0x400>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 54 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
		assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
		power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer6: timer@2460000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2460000 0x00 0x400>;
		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 55 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 55 1>;
		assigned-clock-parents = <&k3_clks 55 2>;
		power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer7: timer@2470000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2470000 0x00 0x400>;
		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 57 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
		assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
		power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer8: timer@2480000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2480000 0x00 0x400>;
		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 58 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 58 1>;
		assigned-clock-parents = <&k3_clks 58 2>;
		power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer9: timer@2490000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2490000 0x00 0x400>;
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 59 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
		assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
		power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer10: timer@24a0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24a0000 0x00 0x400>;
		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 60 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 60 1>;
		assigned-clock-parents = <&k3_clks 60 2>;
		power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer11: timer@24b0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24b0000 0x00 0x400>;
		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 62 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
		assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
		power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer12: timer@24c0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24c0000 0x00 0x400>;
		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 63 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 63 1>;
		assigned-clock-parents = <&k3_clks 63 2>;
		power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer13: timer@24d0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24d0000 0x00 0x400>;
		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 64 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
		assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer14: timer@24e0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24e0000 0x00 0x400>;
		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 65 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 65 1>;
		assigned-clock-parents = <&k3_clks 65 2>;
		power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer15: timer@24f0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24f0000 0x00 0x400>;
		interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 66 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
		assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
		power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	main_timer16: timer@2500000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2500000 0x00 0x400>;
		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 67 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 67 1>;
		assigned-clock-parents = <&k3_clks 67 2>;
		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer17: timer@2510000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2510000 0x00 0x400>;
		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 68 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
		assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
		power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer18: timer@2520000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2520000 0x00 0x400>;
		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 69 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 69 1>;
		assigned-clock-parents = <&k3_clks 69 2>;
		power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer19: timer@2530000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2530000 0x00 0x400>;
		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 70 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
		assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
		power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_uart0: serial@2800000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x100>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 146 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart1: serial@2810000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x100>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 278 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart2: serial@2820000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x100>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 279 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart3: serial@2830000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02830000 0x00 0x100>;
		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 280 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart4: serial@2840000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02840000 0x00 0x100>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 281 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart5: serial@2850000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02850000 0x00 0x100>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 282 0>;
		clock-names = "fclk";
		status = "okay";
	};

	main_uart6: serial@2860000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02860000 0x00 0x100>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 283 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart7: serial@2870000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02870000 0x00 0x100>;
		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 284 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart8: serial@2880000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02880000 0x00 0x100>;
		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 285 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart9: serial@2890000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02890000 0x00 0x100>;
		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 286 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_gpio0: gpio@600000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00600000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <256>, <257>, <258>, <259>,
			     <260>, <261>, <262>, <263>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 105 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio1: gpio@601000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00601000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <288>, <289>, <290>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 106 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio2: gpio@610000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00610000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <264>, <265>, <266>, <267>,
			     <268>, <269>, <270>, <271>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 107 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio3: gpio@611000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00611000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <292>, <293>, <294>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 108 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio4: gpio@620000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00620000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <272>, <273>, <274>, <275>,
			     <276>, <277>, <278>, <279>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 109 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio5: gpio@621000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00621000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <296>, <297>, <298>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 110 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio6: gpio@630000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00630000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <280>, <281>, <282>, <283>,
			     <284>, <285>, <286>, <287>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 111 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_gpio7: gpio@631000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00631000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <300>, <301>, <302>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 112 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	main_sdhci0: mmc@4f80000 {
		compatible = "ti,j721e-sdhci-8bit";
		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
		assigned-clocks = <&k3_clks 91 1>;
		assigned-clock-parents = <&k3_clks 91 2>;
		bus-width = <8>;
		mmc-hs200-1_8v;
		mmc-ddr-1_8v;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-mmc-hs = <0x0>;
		ti,otap-del-sel-ddr52 = <0x5>;
		ti,otap-del-sel-hs200 = <0x6>;
		ti,otap-del-sel-hs400 = <0x0>;
		ti,itap-del-sel-legacy = <0x10>;
		ti,itap-del-sel-mmc-hs = <0xa>;
		ti,itap-del-sel-ddr52 = <0x3>;
		ti,trm-icp = <0x8>;
		dma-coherent;
		status = "disabled";
	};

	main_sdhci1: mmc@4fb0000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
		assigned-clocks = <&k3_clks 92 0>;
		assigned-clock-parents = <&k3_clks 92 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0x0>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,otap-del-sel-sdr104 = <0x5>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,itap-del-sel-ddr50 = <0x2>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
		sdhci-caps-mask = <0x2 0x0>;
		status = "disabled";
	};

	main_sdhci2: mmc@4f98000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
		assigned-clocks = <&k3_clks 93 0>;
		assigned-clock-parents = <&k3_clks 93 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0x0>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,otap-del-sel-sdr104 = <0x5>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,itap-del-sel-ddr50 = <0x2>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
		sdhci-caps-mask = <0x2 0x0>;
		status = "disabled";
	};

	usbss0: cdns-usb@4104000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4104000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb0: usb@6000000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6000000 0x00 0x10000>,
			      <0x00 0x6010000 0x00 0x10000>,
			      <0x00 0x6020000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	usbss1: cdns-usb@4114000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4114000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb1: usb@6400000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6400000 0x00 0x10000>,
			      <0x00 0x6410000 0x00 0x10000>,
			      <0x00 0x6420000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2000000 0x0 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 187 0>;
		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
		status = "disabled";
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2010000 0x0 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 188 0>;
		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2020000 0x0 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 189 0>;
		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2030000 0x0 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 190 0>;
		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c4: i2c@2040000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2040000 0x0 0x100>;
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 191 0>;
		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c5: i2c@2050000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2050000 0x0 0x100>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 192 0>;
		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	main_i2c6: i2c@2060000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2060000 0x0 0x100>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 193 0>;
		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	vxe384: video-encoder@4200000 {
		compatible = "img,vxe384";
		reg = <0x00 0x04200000>,
			<0x00 0x100000>;
		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
	};

	d5520: video-decoder@4300000 {
		compatible = "img,d5500-vxd";
		reg = <0x00 0x04300000>,
			<0x00 0x100000>;
		power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	};

	ufs_wrapper: ufs-wrapper@4e80000 {
		compatible = "ti,j721e-ufs";
		reg = <0x0 0x4e80000 0x0 0x100>;
		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 277 1>;
		assigned-clocks = <&k3_clks 277 1>;
		assigned-clock-parents = <&k3_clks 277 4>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		ufs@4e84000 {
			compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
			reg = <0x0 0x4e84000 0x0 0x10000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
			clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
			clock-names = "core_clk", "phy_clk", "ref_clk";
			dma-coherent;
		};
	};

	mhdp: dp-bridge@a000000 {
		compatible = "ti,j721e-mhdp8546";
		/*
		 * Note: we do not map DPTX PHY area, as that is handled by
		 * the PHY driver.
		 */
		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
		reg-names = "mhdptx", "j721e-intg";

		clocks = <&k3_clks 151 36>;

		interrupt-parent = <&gic500>;
		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;

		dp0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
			    reg = <0>;
			};

			port@4 {
			    reg = <4>;
			};
		};
	};

	dsi0: dsi@48000000 {
		compatible = "ti,j721e-dsi";
		reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
		clocks = <&k3_clks 150 1>, <&k3_clks 150 5>;
		clock-names = "dsi_p_clk", "dsi_sys_clk";
		power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
		interrupt-parent = <&gic500>;
		interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&dphy2>;
		phy-names = "dphy";
		status = "disabled";

		dsi0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	dss: dss@4a00000 {
		compatible = "ti,j721e-dss";
		reg =
			<0x00 0x04a00000 0x00 0x10000>, /* common_m */
			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/

			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */

			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */

			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
			<0x00 0x04af0000 0x00 0x10000>; /* wb */

		reg-names = "common_m", "common_s0",
			"common_s1", "common_s2",
			"vidl1", "vidl2","vid1","vid2",
			"ovr1", "ovr2", "ovr3", "ovr4",
			"vp1", "vp2", "vp3", "vp4",
			"wb";

		clocks = <&k3_clks 152 0>,
			 <&k3_clks 152 1>,
			 <&k3_clks 152 4>,
			 <&k3_clks 152 9>,
			 <&k3_clks 152 13>;
		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";

		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;

		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "common_m",
				  "common_s0",
				  "common_s1",
				  "common_s2";

		dss_ports: ports {
		};
	};

	mcasp0: mcasp@2b00000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b00000 0x0 0x2000>,
			<0x0 0x02b08000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 174 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp1: mcasp@2b10000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b10000 0x0 0x2000>,
			<0x0 0x02b18000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 175 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp2: mcasp@2b20000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b20000 0x0 0x2000>,
			<0x0 0x02b28000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 176 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp3: mcasp@2b30000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b30000 0x0 0x2000>,
			<0x0 0x02b38000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 177 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp4: mcasp@2b40000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b40000 0x0 0x2000>,
			<0x0 0x02b48000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 178 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp5: mcasp@2b50000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b50000 0x0 0x2000>,
			<0x0 0x02b58000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 179 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp6: mcasp@2b60000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b60000 0x0 0x2000>,
			<0x0 0x02b68000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 180 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp7: mcasp@2b70000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b70000 0x0 0x2000>,
			<0x0 0x02b78000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 181 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp8: mcasp@2b80000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b80000 0x0 0x2000>,
			<0x0 0x02b88000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 182 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp9: mcasp@2b90000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b90000 0x0 0x2000>,
			<0x0 0x02b98000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 183 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp10: mcasp@2ba0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02ba0000 0x0 0x2000>,
			<0x0 0x02ba8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 184 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcasp11: mcasp@2bb0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02bb0000 0x0 0x2000>,
			<0x0 0x02bb8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 185 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	watchdog0: watchdog@2200000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2200000 0x0 0x100>;
		clocks = <&k3_clks 252 1>;
		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 252 1>;
		assigned-clock-parents = <&k3_clks 252 5>;
	};

	watchdog1: watchdog@2210000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2210000 0x0 0x100>;
		clocks = <&k3_clks 253 1>;
		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 253 1>;
		assigned-clock-parents = <&k3_clks 253 5>;
	};

	main_r5fss0: r5fss@5c00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
			 <0x5d00000 0x00 0x5d00000 0x20000>;
		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss0_core0: r5f@5c00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5c00000 0x00008000>,
			      <0x5c10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <245>;
			ti,sci-proc-ids = <0x06 0xff>;
			resets = <&k3_reset 245 1>;
			firmware-name = "j7-main-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss0_core1: r5f@5d00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5d00000 0x00008000>,
			      <0x5d10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <246>;
			ti,sci-proc-ids = <0x07 0xff>;
			resets = <&k3_reset 246 1>;
			firmware-name = "j7-main-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	main_r5fss1: r5fss@5e00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
			 <0x5f00000 0x00 0x5f00000 0x20000>;
		power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss1_core0: r5f@5e00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5e00000 0x00008000>,
			      <0x5e10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <247>;
			ti,sci-proc-ids = <0x08 0xff>;
			resets = <&k3_reset 247 1>;
			firmware-name = "j7-main-r5f1_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss1_core1: r5f@5f00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5f00000 0x00008000>,
			      <0x5f10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <248>;
			ti,sci-proc-ids = <0x09 0xff>;
			resets = <&k3_reset 248 1>;
			firmware-name = "j7-main-r5f1_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	c66_0: dsp@4d80800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x80800000 0x00 0x00048000>,
		      <0x4d 0x80e00000 0x00 0x00008000>,
		      <0x4d 0x80f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <142>;
		ti,sci-proc-ids = <0x03 0xff>;
		resets = <&k3_reset 142 1>;
		firmware-name = "j7-c66_0-fw";
		status = "disabled";
	};

	c66_1: dsp@4d81800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x81800000 0x00 0x00048000>,
		      <0x4d 0x81e00000 0x00 0x00008000>,
		      <0x4d 0x81f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <143>;
		ti,sci-proc-ids = <0x04 0xff>;
		resets = <&k3_reset 143 1>;
		firmware-name = "j7-c66_1-fw";
		status = "disabled";
	};

	c71_0: dsp@64800000 {
		compatible = "ti,j721e-c71-dsp";
		reg = <0x00 0x64800000 0x00 0x00080000>,
		      <0x00 0x64e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <15>;
		ti,sci-proc-ids = <0x30 0xff>;
		resets = <&k3_reset 15 1>;
		firmware-name = "j7-c71_0-fw";
		status = "disabled";
	};

	timesync_router: pinctrl@a40000 {
		compatible = "pinctrl-single";
		reg = <0x0 0xa40000 0x0 0x800>;
		#address-cells = <1>;
		#size-cells = <0>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x000107ff>;
		status = "disabled";
	};

	icssg0: icssg@b000000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb000000 0x00 0x80000>;
		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b000000 0x100000>;

		icssg0_mem: memories@0 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg0_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg0_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
						 <&k3_clks 119 1>;  /* icssg0_iclk */
					assigned-clocks = <&icssg0_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 119 1>;
				};

				icssg0_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 3>,	/* icssg0_iep_clk */
						 <&icssg0_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg0_iepclk_mux>;
					assigned-clock-parents = <&icssg0_coreclk_mux>;
				};
			};
		};

		icssg0_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg0_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg0_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru0_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x3000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_0-fw";
		};

		rtu0_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_0-fw";
		};

		tx_pru0_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_0-fw";
		};

		pru0_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x3000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_1-fw";
		};

		rtu0_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_1-fw";
		};

		tx_pru0_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_1-fw";
		};

		icssg0_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 119 1>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	icssg1: icssg@b100000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb100000 0x00 0x80000>;
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b100000 0x100000>;

		icssg1_mem: memories@b100000 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg1_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg1_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
						 <&k3_clks 120 4>;  /* icssg1_iclk */
					assigned-clocks = <&icssg1_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 120 4>;
				};

				icssg1_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 9>,	/* icssg1_iep_clk */
						 <&icssg1_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg1_iepclk_mux>;
					assigned-clock-parents = <&icssg1_coreclk_mux>;
				};
			};
		};

		icssg1_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg1_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg1_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru1_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x4000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_0-fw";
		};

		rtu1_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_0-fw";
		};

		tx_pru1_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_0-fw";
		};

		pru1_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x4000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_1-fw";
		};

		rtu1_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_1-fw";
		};

		tx_pru1_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_1-fw";
		};

		icssg1_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 120 4>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	gpu: gpu@4e20000000 {
		compatible = "ti,j721e-pvr", "img,pvr-ge8430";
		reg = <0x4e 0x20000000 0x00 0x80000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
		power-domain-names = "firmware", "dust";
		clocks = <&k3_clks 125 0>;
		assigned-clocks = <&k3_clks 125 0>;
		assigned-clock-rates = <750000000>;
		clock-names = "core";
	};

	main_mcan0: can@2701000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02701000 0x00 0x200>,
		      <0x00 0x02708000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan1: can@2711000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02711000 0x00 0x200>,
		      <0x00 0x02718000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan2: can@2721000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02721000 0x00 0x200>,
		      <0x00 0x02728000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan3: can@2731000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02731000 0x00 0x200>,
		      <0x00 0x02738000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan4: can@2741000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02741000 0x00 0x200>,
		      <0x00 0x02748000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan5: can@2751000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02751000 0x00 0x200>,
		      <0x00 0x02758000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan6: can@2761000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02761000 0x00 0x200>,
		      <0x00 0x02768000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan7: can@2771000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02771000 0x00 0x200>,
		      <0x00 0x02778000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan8: can@2781000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02781000 0x00 0x200>,
		      <0x00 0x02788000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan9: can@2791000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02791000 0x00 0x200>,
		      <0x00 0x02798000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan10: can@27a1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027a1000 0x00 0x200>,
		      <0x00 0x027a8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan11: can@27b1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027b1000 0x00 0x200>,
		      <0x00 0x027b8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan12: can@27c1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027c1000 0x00 0x200>,
		      <0x00 0x027c8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_mcan13: can@27d1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027d1000 0x00 0x200>,
		      <0x00 0x027d8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	main_spi0: spi@2100000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02100000 0x00 0x400>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 266 1>;
		status = "disabled";
	};

	main_spi1: spi@2110000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02110000 0x00 0x400>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 267 1>;
		status = "disabled";
	};

	main_spi2: spi@2120000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02120000 0x00 0x400>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 268 1>;
		status = "disabled";
	};

	main_spi3: spi@2130000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02130000 0x00 0x400>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 269 1>;
		status = "okay";
		ti,spi-num-cs = <4>;
	};

	main_spi4: spi@2140000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02140000 0x00 0x400>;
		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 270 1>;
		status = "disabled";
	};

	main_spi5: spi@2150000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02150000 0x00 0x400>;
		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 271 1>;
		status = "okay";
	};

	main_spi6: spi@2160000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02160000 0x00 0x400>;
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 272 1>;
		status = "disabled";
	};

	main_spi7: spi@2170000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02170000 0x00 0x400>;
		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 273 1>;
		status = "disabled";
	};

	main_esm: esm@700000 {
		compatible = "ti,j721e-esm";
		reg = <0x0 0x700000 0x0 0x1000>;
		ti,esm-pins = <344>, <345>;
	};

	dphy2: phy@4480000 {
		compatible = "ti,j721e-dphy";
		reg = <0x0 0x04480000 0x0 0x1000>;
		clocks = <&k3_clks 296 1>, <&k3_clks 296 3>;
		clock-names = "psm", "pll_ref";
		#phy-cells = <0>;
		power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 296 3>;
		assigned-clock-parents = <&k3_clks 296 4>;
		assigned-clock-rates = <19200000>;
		status = "disabled";
	};
};

k3-j721e-common-proc-board.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Product Link: https://www.ti.com/tool/J721EXCPXEVM
 */

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>

/ {
	compatible = "ti,j721e-evm", "ti,j721e";
	model = "Texas Instruments J721e EVM";

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart0;
		serial7 = &main_uart5;
		spi3 = &main_spi3;
		spi5 = &main_spi5;
		ethernet0 = &cpsw_port1;
		mmc0 = &main_sdhci0;
		mmc1 = &main_sdhci1;
	};

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LMS140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		//gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv_alt: gpio-regulator-tps659411 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
		regulator-name = "vdd_sd_dv";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_3v3>;
		gpios = <&main_gpio0 111 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	dp_pwr_3v3: regulator-dp-pwr {
		compatible = "regulator-fixed";
		regulator-name = "dp-pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		//gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
		enable-active-high;
	};

	dp0: connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <&dp_pwr_3v3>;

		port {
			dp_connector_in: endpoint {
				remote-endpoint = <&dp0_out>;
			};
		};
	};

	pps_gpio {
		status = "okay";
		compatible = "pps-gpio";
		gpios = <&main_gpio1 13 GPIO_ACTIVE_HIGH>;
	};
};

&main_pmx0 {
	main_uart0_pins_default: main-uart0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
			J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
		>;
	};

	main_mmc1_pins_default: main-mmc1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
		>;
	};

	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
		>;
	};

	dp0_pins_default: dp0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
		>;
	};

	mcasp10_pins_default: mcasp10-default-pins {
		pinctrl-single,pins = <
			//J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ /*pin FOR I2C2  del 2025/02/25  */
			//J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */  /*pin FOR I2C2  del 2025/02/25  */
			//J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */     /*pin FOR UART3  del 2025/02/25  */
			//J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */     /*pin FOR UART3  del 2025/02/25  */
			//J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
			//J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
			// J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */	/* pin FOR SPI5  del 2025/02/27   */
			// J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
			// J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */	/* pin FOR SPI5  del 2025/02/27   */
		>;
	};

	/* conflict gpio delete for /dev/gpiochip0 */
	// audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins {
	// 	pinctrl-single,pins = <
	// 		J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
	// 	>;
	// };


	main_gpio0_pins_default: main-gpio0-default-pins {
		pinctrl-single,pins = <
			// J721E_IOPAD(0x4, PIN_OUTPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
			// J721E_IOPAD(0x8, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
			// J721E_IOPAD(0xc, PIN_OUTPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
			J721E_IOPAD(0x10, PIN_OUTPUT_PULLDOWN, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
			// J721E_IOPAD(0x14, PIN_OUTPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
			// J721E_IOPAD(0x1c, PIN_OUTPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
			J721E_IOPAD(0x28, PIN_INPUT, 7) /* (AG20) PRG1_PRU0_GPO9.GPIO0_10 */
			J721E_IOPAD(0x2c, PIN_OUTPUT_PULLUP, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
			// J721E_IOPAD(0x30, PIN_OUTPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
			// J721E_IOPAD(0x34, PIN_OUTPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
			// J721E_IOPAD(0x38, PIN_INPUT, 7) /* (AG24) PRG1_PRU0_GPO13.GPIO0_14 */
			// J721E_IOPAD(0x3c, PIN_OUTPUT, 7) /* (AD24) PRG1_PRU0_GPO14.GPIO0_15 */
			// J721E_IOPAD(0x40, PIN_INPUT, 7) /* (AC24) PRG1_PRU0_GPO15.GPIO0_16 */
			// J721E_IOPAD(0x44, PIN_INPUT, 7) /* (AE24) PRG1_PRU0_GPO16.GPIO0_17 */
			// J721E_IOPAD(0x4c, PIN_INPUT, 7) /* (AJ21) PRG1_PRU0_GPO17.GPIO0_18 */
			// J721E_IOPAD(0x50, PIN_INPUT, 7) /* (AE21) PRG1_PRU0_GPO18.GPIO0_19 */
			// J721E_IOPAD(0x54, PIN_INPUT, 7) /* (AH21) PRG1_PRU0_GPO19.GPIO0_20 */
			// J721E_IOPAD(0x58, PIN_INPUT, 7) /* (AE22) PRG1_PRU1_GPO0.GPIO0_21 */
			// J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
			// J721E_IOPAD(0x60, PIN_INPUT, 7) /* (AF23) PRG1_PRU1_GPO2.GPIO0_23 */
			// J721E_IOPAD(0x64, PIN_INPUT, 7) /* (AD23) PRG1_PRU1_GPO3.GPIO0_24 */
			// J721E_IOPAD(0x68, PIN_INPUT, 7) /* (AH24) PRG1_PRU1_GPO4.GPIO0_25 */
			// J721E_IOPAD(0x6c, PIN_INPUT, 7) /* (AG21) PRG1_PRU1_GPO5.GPIO0_26 */
			// J721E_IOPAD(0x70, PIN_INPUT, 7) /* (AE23) PRG1_PRU1_GPO6.GPIO0_27 */
			// J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */
			// J721E_IOPAD(0x78, PIN_INPUT, 7) /* (Y23) PRG1_PRU1_GPO8.GPIO0_29 */
			// J721E_IOPAD(0x7c, PIN_OUTPUT, 7) /* (AF21) PRG1_PRU1_GPO9.GPIO0_30 */
			// J721E_IOPAD(0x80, PIN_OUTPUT, 7) /* (AB23) PRG1_PRU1_GPO10.GPIO0_31 */
			// J721E_IOPAD(0x90, PIN_OUTPUT_PULLDOWN, 7) /* (AH26) PRG1_PRU1_GPO14.GPIO0_35 */
			J721E_IOPAD(0x94, PIN_INPUT, 7) /* (AJ27) PRG1_PRU1_GPO15.GPIO0_36 */
			J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 add for S32K SPI */
			// J721E_IOPAD(0xa8, PIN_OUTPUT, 7) /* (AD19) PRG1_MDIO0_MDIO.GPIO0_41 */
			// J721E_IOPAD(0xac, PIN_OUTPUT, 7) /* (AD18) PRG1_MDIO0_MDC.GPIO0_42 */
			// J721E_IOPAD(0xb0, PIN_OUTPUT, 7) /* (AF28) PRG0_PRU0_GPO0.GPIO0_43 */
			// J721E_IOPAD(0xb4, PIN_INPUT, 7) /* (AE28) PRG0_PRU0_GPO1.GPIO0_44 */
			// J721E_IOPAD(0xb8, PIN_OUTPUT, 7) /* (AE27) PRG0_PRU0_GPO2.GPIO0_45 */
			// J721E_IOPAD(0xbc, PIN_OUTPUT, 7) /* (AD26) PRG0_PRU0_GPO3.GPIO0_46 */
			// J721E_IOPAD(0xc0, PIN_INPUT, 7) /* (AD25) PRG0_PRU0_GPO4.GPIO0_47 */
			// J721E_IOPAD(0xc8, PIN_OUTPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
			// J721E_IOPAD(0xcc, PIN_OUTPUT, 7) /* (AC28) PRG0_PRU0_GPO7.GPIO0_50 */
			// J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (AC27) PRG0_PRU0_GPO8.GPIO0_51 */
			// J721E_IOPAD(0xdc, PIN_OUTPUT, 7) /* (AJ28) PRG0_PRU0_GPO11.GPIO0_54 */
			// J721E_IOPAD(0xe0, PIN_OUTPUT, 7) /* (AH27) PRG0_PRU0_GPO12.GPIO0_55 */
			// J721E_IOPAD(0xe4, PIN_INPUT, 7) /* (AH29) PRG0_PRU0_GPO13.GPIO0_56 */
			// J721E_IOPAD(0xe8, PIN_INPUT, 7) /* (AG28) PRG0_PRU0_GPO14.GPIO0_57 */
			// J721E_IOPAD(0xec, PIN_INPUT, 7) /* (AG27) PRG0_PRU0_GPO15.GPIO0_58 */
			// J721E_IOPAD(0xf0, PIN_OUTPUT, 7) /* (AH28) PRG0_PRU0_GPO16.GPIO0_59 */
			// J721E_IOPAD(0xf8, PIN_OUTPUT, 7) /* (AB29) PRG0_PRU0_GPO18.GPIO0_61 */
			// J721E_IOPAD(0xfc, PIN_INPUT, 7) /* (AB28) PRG0_PRU0_GPO19.GPIO0_62 */
			// J721E_IOPAD(0x100, PIN_INPUT, 7) /* (AE29) PRG0_PRU1_GPO0.GPIO0_63 */
			// J721E_IOPAD(0x104, PIN_INPUT, 7) /* (AD28) PRG0_PRU1_GPO1.GPIO0_64 */
			J721E_IOPAD(0x130, PIN_INPUT, 7) /* (AF27) PRG0_PRU1_GPO12.GPIO0_75 */
			J721E_IOPAD(0x134, PIN_OUTPUT_PULLUP, 7) /* (AF26) PRG0_PRU1_GPO13.GPIO0_76 */
			// J721E_IOPAD(0x138, PIN_OUTPUT_PULLUP, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
			// J721E_IOPAD(0x13c, PIN_OUTPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
			// J721E_IOPAD(0x140, PIN_INPUT, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */
			// J721E_IOPAD(0x154, PIN_OUTPUT_PULLDOWN, 7) /* (AA27) PRG0_MDIO0_MDC.GPIO0_84 */
			// J721E_IOPAD(0x168, PIN_OUTPUT, 7) /* (V27) RGMII5_TD1.GPIO0_89 */
			J721E_IOPAD(0x16c, PIN_INPUT, 7) /* (U28) RGMII5_TD0.GPIO0_90  OPEN for SPI3_CS2 IRQ */
			// J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 7) /* (U29) RGMII5_TXC.GPIO0_91 */
			// J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 7) /* (U25) RGMII5_RXC.GPIO0_92 */
			// J721E_IOPAD(0x178, PIN_OUTPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
			// J721E_IOPAD(0x17c, PIN_OUTPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
			// J721E_IOPAD(0x180, PIN_OUTPUT_PULLDOWN, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
			// J721E_IOPAD(0x184, PIN_OUTPUT_PULLDOWN, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
			// J721E_IOPAD(0x188, PIN_OUTPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
			J721E_IOPAD(0x18c, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
			J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
			// J721E_IOPAD(0x194, PIN_OUTPUT, 7) /* (W28) RGMII6_TD2.GPIO0_100 */
			// J721E_IOPAD(0x198, PIN_OUTPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
			// J721E_IOPAD(0x19c, PIN_OUTPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
			// J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
			J721E_IOPAD(0x1a4, PIN_INPUT, 7) /* (W26) RGMII6_RXC.GPIO0_104 */
			// J721E_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
			// J721E_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (Y4) SPI0_CS1.GPIO0_112 */
			// J721E_IOPAD(0x1c8, PIN_OUTPUT, 7) /* (AA1) SPI0_CLK.GPIO0_113 */
			// J721E_IOPAD(0x1cc, PIN_OUTPUT, 7) /* (AB5) SPI0_D0.GPIO0_114 */
			// J721E_IOPAD(0x1d0, PIN_OUTPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
			// J721E_IOPAD(0x1dc, PIN_INPUT, 7) /* (Y1) SPI1_CLK.GPIO0_118 */
			// J721E_IOPAD(0x1e0, PIN_INPUT, 7) /* (Y5) SPI1_D0.GPIO0_119 */
			J721E_IOPAD(0x1e4, PIN_INPUT, 7) /* (Y2) SPI1_D1.GPIO0_120 */
		>;
	};


	main_gpio1_pins_default: main-gpio1-default-pins {
		pinctrl-single,pins = <
			// J721E_IOPAD(0x218, PIN_OUTPUT, 7) /* (W2) I3C0_SCL.GPIO1_5 */
			// J721E_IOPAD(0x21c, PIN_INPUT, 7) /* (W1) I3C0_SDA.GPIO1_6 */
			// J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
			// J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
			J721E_IOPAD(0x238, PIN_INPUT, 7) /* (V6) TIMER_IO0.GPIO1_13 ADD for PPS */
			J721E_IOPAD(0x260, PIN_OUTPUT_PULLDOWN, 7) /* (T28) MMC2_DAT3.GPIO1_23 */
			// J721E_IOPAD(0x264, PIN_INPUT, 7) /* (T29) MMC2_DAT2.GPIO1_24 */
			//J721E_IOPAD(0x268, PIN_OUTPUT_PULLUP, 7) /* (T27) MMC2_DAT1.GPIO1_25 */ /*pin FOR TDA4_LG69T_RST  del 2025/02/25  */
			// J721E_IOPAD(0x26c, PIN_OUTPUT, 7) /* (T24) MMC2_DAT0.GPIO1_26 */
			// J721E_IOPAD(0x270, PIN_INPUT, 7) /* (T26) MMC2_CLK.GPIO1_27 */
			// J721E_IOPAD(0x274, PIN_INPUT, 7) /* (T25) MMC2_CMD.GPIO1_28 */
			// J721E_IOPAD(0x290, PIN_OUTPUT, 7) /* (U6) USB0_DRVVBUS.GPIO1_29 */
			// J721E_IOPAD(0x294, PIN_INPUT, 7) /* (AD1) MLB0_MLBSP.GPIO1_30 */
			// J721E_IOPAD(0x298, PIN_INPUT, 7) /* (AC1) MLB0_MLBSN.GPIO1_31 */
			// J721E_IOPAD(0x29c, PIN_INPUT, 7) /* (AC3) MLB0_MLBDP.GPIO1_32 */
			// J721E_IOPAD(0x2a0, PIN_INPUT, 7) /* (AD3) MLB0_MLBDN.GPIO1_33 */
			// J721E_IOPAD(0x2a4, PIN_INPUT, 7) /* (AD2) MLB0_MLBCP.GPIO1_34 */
			// J721E_IOPAD(0x2a8, PIN_INPUT, 7) /* (AE2) MLB0_MLBCN.GPIO1_35 */
		>;
	};

	// add
	main_mcasp1_pins_default: main-mcasp1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x108, PIN_INPUT, 12) /* (AD27) PRG0_PRU1_GPO2.MCASP1_ACLKR */
			J721E_IOPAD(0x114, PIN_INPUT, 12) /* (AB27) PRG0_PRU1_GPO5.MCASP1_ACLKX */
			J721E_IOPAD(0x120, PIN_INPUT, 12) /* (AA28) PRG0_PRU1_GPO8.MCASP1_AFSX */
			J721E_IOPAD(0x10c, PIN_INPUT, 13) /* (AC25) PRG0_PRU1_GPO3.MCASP1_AXR11 */
		>;
	};

	// add
	main_mmcsd1_pins_default: main-mmcsd1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
		>;
	};

	// add
	main_pcie3_pins_default: main-pcie3-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x25c, PIN_INPUT, 6) /* (R28) MMC1_SDWP.PCIE3_CLKREQn */
		>;
	};

	/* AG190W SPI <---> TDA4 SPI3 */
	main_spi3_pins_default: main-spi3-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x144, PIN_INPUT, 4) /* (Y25) PRG0_PRU1_GPO17.SPI3_CLK */
			J721E_IOPAD(0x11c, PIN_INPUT, 4) /* (AA24) PRG0_PRU1_GPO7.SPI3_CS0 */
			J721E_IOPAD(0xd4, PIN_INPUT, 4) /* (AB26) PRG0_PRU0_GPO9.SPI3_CS1 */
			J721E_IOPAD(0xd8, PIN_INPUT, 4) /* (AB25) PRG0_PRU0_GPO10.SPI3_CS2 */
			J721E_IOPAD(0x124, PIN_INPUT, 4) /* (Y24) PRG0_PRU1_GPO9.SPI3_CS3 */
			J721E_IOPAD(0x148, PIN_INPUT, 4) /* (AA26) PRG0_PRU1_GPO18.SPI3_D0 */
			J721E_IOPAD(0x14c, PIN_INPUT, 4) /* (AA29) PRG0_PRU1_GPO19.SPI3_D1 */
		>;
	};

	/* Add for A2 Sample AG568N <---> TDA4 SPI5 */
	main_spi5_pins_default: main_spi5-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1a0, PIN_INPUT, 3) /* (W29) RGMII6_TXC.SPI5_CLK */
			J721E_IOPAD(0x1b4, PIN_INPUT, 3) /* (W25) RGMII6_RD0.SPI5_CS1 */
			J721E_IOPAD(0x198, PIN_INPUT, 3) /* (V25) RGMII6_TD1.SPI5_D0 */
			J721E_IOPAD(0x1b0, PIN_INPUT, 3) /* (W24) RGMII6_RD1.SPI5_D1 */
		>;
	};

	// add
	main_system0_pins_default: main-system0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x278, PIN_OUTPUT, 0) /* (T6) RESETSTATz */
			J721E_IOPAD(0x280, PIN_INPUT, 0) /* (U4) SOC_SAFETY_ERRORn */
		>;
	};

	/* AG190W Uart3 <----> TDA4 Uart5 */
	main_uart5_pins_default: main-uart5-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d4, PIN_INPUT, 3) /* (Y3) SPI1_CS0.UART5_RXD */
			J721E_IOPAD(0x1d8, PIN_OUTPUT, 3) /* (W4) SPI1_CS1.UART5_TXD */
		>;
	};
};

&wkup_pmx0 {
	/delete-node/ pmic-irq-default-pins;

	mcu_fss0_ospi0_pins_default: mcu_fss0_ospi0-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
			J721E_WKUP_IOPAD(0x3c, PIN_INPUT_PULLUP, 6) /* (B23) MCU_OSPI1_DQS.MCU_OSPI0_ECC_FAIL */
			J721E_WKUP_IOPAD(0x38, PIN_OUTPUT_PULLUP, 6) /* (A23) MCU_OSPI1_LBCLKO.MCU_OSPI0_RESET_OUT0 */
		>;
	};

	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
		>;
	};

	// modify
	// mcu_mdio_pins_default: mcu-mdio1-default-pins {
	// 	pinctrl-single,pins = <
	// 		J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
	// 		J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
	// 	>;
	// };
	mcu_mdio_pins_default: mcu-mdio1-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
			J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
		>;
	};

	wkup_gpio_pins_default: wkup-gpio-default-pins {
		pinctrl-single,pins = <
	//		J721E_WKUP_IOPAD(0xbc, PIN_OUTPUT_PULLDOWN, 7) /* (F27) WKUP_GPIO0_3 */ /*pin Board_ID_EEPROM_WP  del 2025/02/25  */
	// 		J721E_WKUP_IOPAD(0xc8, PIN_INPUT, 7) /* (F29) WKUP_GPIO0_6 */
	// 		J721E_WKUP_IOPAD(0xcc, PIN_OUTPUT, 7) /* (G28) WKUP_GPIO0_7 */
	// 		J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_8 */
	// 		J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */
	// 		J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (H26) WKUP_GPIO0_10 */
	// 		J721E_WKUP_IOPAD(0xdc, PIN_OUTPUT, 7) /* (H27) WKUP_GPIO0_11 */
	// 		J721E_WKUP_IOPAD(0x4, PIN_INPUT_PULLUP, 7) /* (C21) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */
	// 		J721E_WKUP_IOPAD(0x34, PIN_INPUT, 7) /* (F22) MCU_OSPI1_CLK.WKUP_GPIO0_29 */
	// 		J721E_WKUP_IOPAD(0x44, PIN_OUTPUT, 7) /* (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
	// 		J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
	// 		J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
	// 		J721E_WKUP_IOPAD(0x50, PIN_OUTPUT_PULLUP, 7) /* (C22) MCU_OSPI1_CSn0.WKUP_GPIO0_36 */
	// 		J721E_WKUP_IOPAD(0x9c, PIN_INPUT, 7) /* (E25) MCU_SPI0_CS0.WKUP_GPIO0_55 */
	// 		J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 7) /* (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
	// 		J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 7) /* (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
	//		J721E_WKUP_IOPAD(0x108, PIN_OUTPUT_PULLDOWN, 7) /* (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */  /*pin BOOT_EEPROM_WP  del 2025/02/25  */
		>;
	};


	// add
	mcu_rgmii1_pins_default: mcu-rgmii1-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
			J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
		>;
	};

};

&main_spi3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi3_pins_default>;
	spidev@0 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <0>;
		spi-cpol = <1>; // CPOL = 1
		spi-cpha = <1>; // CPHA = 1
	};
	spidev@1 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <1>;
		spi-cpol = <0>; // CPOL = 0
		spi-cpha = <1>; // CPHA = 1
	};
	spidev@2 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <2>;
		spi-cpol = <0>; // CPOL = 0
		spi-cpha = <0>; // CPHA = 0
		// interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
	};
	spidev@3 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <3>;
		spi-cpol = <0>; // CPOL = 0
		spi-cpha = <1>; // CPHA = 1
	};
};

&main_spi5 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi5_pins_default>;
	spidev@0 {
		compatible = "ti,spi-evm";
		spi-max-frequency = <3125000>;
		reg = <0>;
		spi-cpol = <1>; // CPOL = 1
		spi-cpha = <1>; // CPHA = 1
	};
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	status = "reserved";
};

&mcu_uart0 {
	status = "reserved";

};

&main_uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	/* Shared with ATF on this platform */
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart1 {
	status = "disabled";
};

&main_uart2 {
	status = "disabled";
};

&main_uart4 {
	status = "disabled";
};

&wkup_gpio0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_gpio_pins_default>;
};

&main_gpio0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_gpio0_pins_default>;
};

&main_gpio1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_gpio1_pins_default>;
};

&main_sdhci0 {
	/* eMMC */
	status = "okay";
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	/* SD/MMC */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	no-1-8-v;
	sdhci-caps-mask = <0x8000000F 0x0>;

};

&ufs_wrapper {
	status = "okay";
	ufs@4e84000 {
	/* ufs */
	status = "okay";
	freq-table-hz = <26000000 26000000>, 
                	<19200000 19200000>,  
                	<19200000 19200000>;	
	};
};

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_QSGMII_LANE1>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
		      <J721E_SERDES1_LANE0_QSGMII_LANE3>, <J721E_SERDES1_LANE1_QSGMII_LANE4>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz3 {
	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
};

&serdes3 {
	serdes3_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
	};
};


&ospi0 {
	status = "okay";
	flash@0 {
		cdns,read-delay = <4>;
	};
};

&ospi1 {
	status = "disabled";
};

&tscadc0 {
	status = "okay";
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&tscadc1 {
	status = "okay";
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

/* conflict gpio delete for /dev/gpiochip0 */
// &k3_clks {
// 	/* Confiure AUDIO_EXT_REFCLK2 pin as output */
// 	pinctrl-names = "default";
// 	pinctrl-0 = <&audi_ext_refclk2_pins_default>;
// };

&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;

	cpts@3d000 {
		/* Map HW4_TS_PUSH to GENF1 */
		ti,pps = <3 1>;
	};
};

&davinci_mdio {
	phy2: ethernet-phy@2 {
		reg = <2>;
		mv86666660-reset-gpios = <&main_gpio0 76 GPIO_ACTIVE_HIGH>;
		reset-assert-us = <10000>;	// 10ms
		reset-deassert-us = <10000>;	// 10ms
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&phy2>;
};

&dss {
	/*
	 * These clock assignments are chosen to enable the following outputs:
	 *
	 * VP0 - DisplayPort SST
	 * VP1 - DPI0
	 * VP2 - DSI
	 * VP3 - DPI1
	 */

	assigned-clocks = <&k3_clks 152 1>,
			  <&k3_clks 152 4>,
			  <&k3_clks 152 9>,
			  <&k3_clks 152 13>;
	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
};

&dss_ports {
	port {
		dpi0_out: endpoint {
			remote-endpoint = <&dp0_in>;
		};
	};
};

&dp0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dp0_in: endpoint {
			remote-endpoint = <&dpi0_out>;
		};
	};

	port@4 {
		reg = <4>;
		dp0_out: endpoint {
			remote-endpoint = <&dp_connector_in>;
		};
	};
};

&mcasp10 {
	status = "okay";
	#sound-dai-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp10_pins_default>;

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	auxclk-fs-ratio = <256>;

	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 1 1 1
		2 2 2 0
	>;
	tx-num-evt = <0>;
	rx-num-evt = <0>;
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz0_refclk_dig {
	assigned-clocks = <&wiz0_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_pll1_refclk {
	assigned-clocks = <&wiz1_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_refclk_dig {
	assigned-clocks = <&wiz1_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_pll1_refclk {
	assigned-clocks = <&wiz2_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_refclk_dig {
	assigned-clocks = <&wiz2_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&serdes0 {
	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz0_pll1_refclk>;

	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>;
	};
};

&cpsw0 {
	status = "okay";
};

&cpsw9g_mdio {
	status = "okay";
};

/*&cpsw0_port3 {
	phy-mode = "sgmii";
	phys = <&cpsw0_phy_gmii_sel 3>, <&serdes1_sgmii_link>;
	mac-address = [00 00 00 00 00 00];
	phy-names = "mac", "serdes";
	// phy-names = "portmode", "serdes-phy";
	status = "okay";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};*/

&serdes1 {
	/*assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz1_pll1_refclk>;*/

	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
	#address-cells = <1>;
	#size-cells = <0>;

	/*serdes1_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz1 1>;
	};*/
};

&serdes2 {
	assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz2_pll1_refclk>;

	serdes2_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};
};

&serdes4 {
	torrent_phy_dp: phy@0 {
		reg = <0>;
		resets = <&serdes_wiz4 1>;
		cdns,phy-type = <PHY_TYPE_DP>;
		cdns,num-lanes = <4>;
		cdns,max-bit-rate = <2700>;
		#phy-cells = <0>;
	};
};

&mhdp {
	phys = <&torrent_phy_dp>;
	phy-names = "dpphy";
	pinctrl-names = "default";
	pinctrl-0 = <&dp0_pins_default>;
};

&pcie0_rc {
	status = "okay";
	//reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <1>;
};

&pcie1_rc {
	status = "okay";
	//reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
	//phys = <&serdes1_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
};

&pcie2_rc {
	status = "okay";
	//reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
	phys = <&serdes2_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
};

#define K3_TS_OFFSET(pa, val)	(0x4+(pa)*4) (0x10000 | val)

&timesync_router {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_cpts>;

	/* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */
	mcu_cpsw_cpts: mcu-cpsw-cpts {
		pinctrl-single,pins = <
			/* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */
			K3_TS_OFFSET(25, 17)
			>;
	};
};

&wkup_i2c0 {
	/delete-node/ eeprom@50;
	/delete-node/ pmic@48;
	/delete-node/ pmic@4c;
	/*status = "reserved";*/
};

&cbass_main {
	phy@4580000 {
                status = "disable";
                };

	phy@4590000 {
                status = "disable";
                };

	dp-bridge@a000000  {
                status = "disable";
                };
};

Hi,

Can you check with SerDes1 in below, I have checked with SerDes0 initially on my side, In my case SerDes 0 is enabled by default so may be same clock was mapped.

&serdes1 {
    /*assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
    assigned-clock-parents = <&wiz1_pll1_refclk>;*/

    assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>, <&serdes1 CDNS_SIERRA_PLL_CMNLC1>;
    assigned-clock-parents = <&wiz1_pll1_refclk>, <&wiz1_pll1_refclk>;
    #address-cells = <1>;

Also, can you please confirm is SerDes1 enabled at U-boot?

Best Regards,
Sudheer