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Original question:

[FAQ] TDA4VM: How to configure RGMII clock delay on J7 devices?

TDA4VM: How to set RGMII_ID_MODE bit to 1 in Linux code?

zs xu
Prodigy 220 points
Part Number: TDA4VM

Tool/software:

I used SDK10.0 CPSW2G's RGMII in Linux and turned off ETHFW.
Reading the 0x40F04040 register found that the RGMII_ID_MODE bit was 0, which prevented me from ping an external Ethernet device.
I changed the "phy-mode" in the device tree to this "rgmi-id, rgmi-txid, rgmi-rxid, rgmii" none of which could set the RGMII_ID_MODE bit to 1.
How to set RGMII_ID_MODE bit to 1 in Linux code?

  • 0
    TI__Mastermind 34680 points

    Hi,

    Can you try integrating the following patch and try again : 

    5483.add-rgmii-id-support.diff 
    diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 2828f888ad92..b09285ebc019 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -210,26 +210,36 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = {
 
 static const
 struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = {
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
-	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x0, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x4, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x8, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0xC, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x10, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x14, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x18, 4, 4), },
+	{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2),
+	  [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x1C, 4, 4), },
 };
 
 static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
+	.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
 };
 
 static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
+	.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
 	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
 	.num_ports = 4,
 	.num_qsgmii_main_ports = 1,
@@ -239,6 +249,7 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
+	.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
 	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
 	.num_ports = 8,
 	.num_qsgmii_main_ports = 2,
@@ -248,6 +259,7 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
+	.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
 	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
 		       BIT(PHY_INTERFACE_MODE_USXGMII),
 	.num_ports = 8,

    Regards,
    Tanmay

  • 0 in reply to Tanmay Patil
    Prodigy 220 points

    I added this patch, however the RGMII_ID_MODE bit of register 0x40F04040 is not set to 1.
    This patch seems to be for cpsw9g, I need to change it for register 0x40F04040 of cpsw2g.

  • 0 in reply to zs xu
    Prodigy 220 points

    Any updates?

  • 0 in reply to zs xu
    TI__Mastermind 34680 points

    Hi,

    This should work for CPSW2G as well. Can you add any print statements in this driver and see if the image is updated properly in your build flow.

    Regards,
    Tanmay

  • 0 in reply to Tanmay Patil
    Prodigy 220 points

    Can I adjust the delay time of RGMII?

  • 0 in reply to Tanmay Patil
    Prodigy 220 points

    Can I modify the delay time of RGMII in TDA4?

  • 0 in reply to zs xu
    TI__Mastermind 34680 points

    Hi,

    It cannot be updated from the MAC. It is fixed. However, if you are using a phy, it depends upon phy, but mostly you are able to upgrade it.

    The phy delay ideally should be controllable from phy node in device tree provided such support id present in the phy driver.

    Regards,
    Tanmay