[FAQ] SK-AM62A-LP: max. recommended trace length for RGMII

Hello Haim Giladi

Thank you for the query.

Please check if the below E2E thread helps.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1398576/tda4vl-q1-tda4vl-q1-rgmii-tx-data-to-clock-skew-tunning

Is your question for the SK or custom board?

Regards,

Sreenivasa

Hello, 

I ask again , it's about AM62, not TDA4.

Hello Haim Giladi

Thank you.

The RGMII interface implementation is similar and can be reused.

refer below inputs i received from the expert:

Both TX data path and RX data path are completely independent of each other, where they each have their own clock and data signals that perform source synchronous data transfers.  Therefore, RGMII does not have a MAC to PHY or PHY to MAC round trip timing constraints like RMII that uses a shared clock for TX and RX paths. 

The challenge is keeping the signals short enough that the PCB doesn’t attenuate the high frequency content of the signal which is required to achieve the appropriate signal rise/fall times.  The only way I know someone can confirm their PCB is providing an acceptable path is perform a signal quality simulation of their PCB implementation using the IBIS models for each device to verify each data path.

Regards,

Sreenivasa