AM620-Q1: How to implement M4F control epwm-SOCA pulse output function on AM620

Hi, try the register bit settings below to control the SOC A and SOC B outputs.

The register description below belongs to the AM64X SOC and the PWM IPs are the same in the AM64X and AM62X device as well.

So, try to enable these bits and see if you are able to see the pulse on the SOCA and SOC B pin. 

thank you

Paula

hi，Paula

Can you provide some APIs that can modify the SOCASEL and SOCBSEL bits in normal code?
I did not find any relevant APIs in the existing API list

Thank you

hi，Paula

Modifying the ETSEL register alone with Jtag does not output the waveforms of soc A and socB.
I tried to modify the ETPS register at the same time,

the results were:
1. The pulse time of SOCA output is very short, about 200ns (epwm base clock is 250Mhz, divided by 4). This is too short for our application. I tried to modify the epwm division to 100, but the value remained unchanged.

My question is:

1. Can the pulse width of socA be adjusted? How to adjust it?

2. What does sysclk period mean in the TRM? If the pwm clock is 250Mhz and the frequency division is 4, what should the value of sysclk period  be?

Hi Owens, let me check internally and come back to you

thank you,

Paula

Hi, what's the result of the verification?

Hi Owens, I checked with a colleague, and SOCA pulse cannot be stretched in code since it is internal to the PWM and is an output directly from the PWM. 

We would need some other peripheral that has access to the SOCA signal that gets generated from the PWM to stretch this signal further. Is it possible for you to use ETFLG to generate and interrupt?

How are you planning to connect SOCA to ADC?

thank you,

Paula

hi，Paula

We plan to use MSPM0L to implement the function of externally triggering ADC sampling.
-Physical connection: AM620 ewpm SOCA is connected to the IO port of MSPM0L through a resistor.
-Timing:
   --The frequency of AM620 ewpm is around 150Khz.
  --The expected pulse width of AM620 ewpm SOCA is 1us~2us
  --MSPM0L IO detected a rising edge and performed sequential sampling of ADC multi-channel.

You mentioned 'use ETFLG to generate and interrupt' above
Because the EPWM peripheral is located in the main domain,
1. What is the time delay for the EPWM ET interrupt to reach M4F? How much range of jitter will there be?
2. Can the EPWM ET interrupt across domains stably trigger ISR? Will it be affected by the A53 CPU load in the main domain?
3. If an IO is selected to output ETFLG related interrupts to the outside, should it be in the main domain or the MCU domain?

4. Can you provide a demo example

thank you,

owens

Hello Owens,

I have looked at the datasheet . The SOC A and SOC B output signals can't be drive with user configurable frequency like 1use or 2usec or x usec.

Can you please confirm are you suing the PWMA and PWMB output signals in your use case ?

If you are using the PWMA ouptut signal then why can't use PWMB for the driving 2usec signal . Because both PWMA and PWMB are running with the same Timer and they are in synch .

Regards,

Anil.

Hello   ( Paula Carrillo),

Can you please reproduce the testing on our side ?

 As per Owen's comments, if we change the Prescalar setting to an EPWM module, the SOCA pulse duration should be changed, but this is not changing.

Here the system clock is 250MHZ and after the clock is divided, the system clock is changed and the SOCA pulse duration also changes.

Please capture waveforms in the CRO and not in the logic analyzer..

Regards,

Anil.

hi Swargam

We need to add one channel of SOCA signal on the basis of using the 6-channel PWM output (PWM0~3, PWM_A + PWM_B，for bldc motor control)

Owens, if you can share project and/or steps you are using for getting the scope shots this would help us reproduce it

thank you,

Paula

Hello Owens,

If you are using all ePWM modules, then we should consider using either the SOCA or SOCB signal or a manual GPIO trigger is used to start the external ADC conversion .

GPIO Trigger:

Trigger a PWM interrupt at 150 kHz, and in the PWM ISR, toggle the GPIO signal.

Method 2:

Adjust the TBCLK (ON) period to precisely match the pulse width of the SOCA signal.

For Method 2, we need to verify the SOCA pulse behavior at different TBCLK periods.

If you have an example running on the M4F core, please share it with us. Paula can perform the testing and provide feedback on the results.

Regards,

Anil.

hi, Swargam & Paula 

  Here are my project and steps.

test_am62x-sk-lp_m4fss0.zip

Hello Owens ,

I have checked my side and your observation is correct.

The SOCA puls is mainly dependent on the sysclk, which is 250MHz, and does not depend on the precular values.

With this pulse signal do you want to start the ADC from an MSP device ?

Is this Ton period not detected by the MSP device ?

Why can't you go with the controlling GPIO ?

Regards,

Anil.

hi，Swargam

"Why can't you go with the controlling GPIO ?"

Because we can't find data on delay and jitter of cross-domain interrupt response in the manual, we want to minimize cross-domain ISR interrupts. Can you provide this data?

"The SOCA puls is mainly dependent on the sysclk, which is 250MHz, and does not depend on the precular values."

Then we use this 120ns pulse width and add other circuits to increase the pulse width of the soc pulse. Can you provide the API for modifying the SOCASEL & ETPS bits related to SOCA?

Hello Owens ,

Swargam Anil said:

With this pulse signal do you want to start the ADC from an MSP device ?

Is this Ton period not detected by the MSP device ?

Can you please provide the answers to the above query ?

How much Ton period needed and why ?

owens shi said:

Then we use this 120ns pulse width and add other circuits to increase the pulse width of the soc pulse. Can you provide the API for modifying the SOCASEL & ETPS bits related to SOCA?

Ya sure, we can provide the APIs for the above implementation.

Paula Carrillo, Please provide APIs to implement above logic .

Regards,

Anil.

hi，Swargam

Swargam Anil said:

With this pulse signal do you want to start the ADC from an MSP device ?

Is this Ton period not detected by the MSP device ?

yes. 

we use mspm0L intead of MSP.

The pulse interval is about 150Khz(may be adjusted according to the pwm cycle). The pulse width is recommended to be about 2us

Owens, we don't have APIs for enabling/configuring SOCA in our AM62x MCU+SDK. However, for a different device (AM63Px) we do, so we could borrow them from there

https://github.com/TexasInstruments/mcupsdk-core/tree/next/source/drivers/epwm/v1 

EPWM_enableADCTrigger() https://github.com/TexasInstruments/mcupsdk-core/blob/next/source/drivers/epwm/v1/etpwm.h#L6232 

EPWM_disableADCTrigger() https://github.com/TexasInstruments/mcupsdk-core/blob/next/source/drivers/epwm/v1/etpwm.h#L6265 

EPWM_setADCTriggerSource() https://github.com/TexasInstruments/mcupsdk-core/blob/next/source/drivers/epwm/v1/etpwm.h#L6315 

EPWM_setADCTriggerEventPrescale() https://github.com/TexasInstruments/mcupsdk-core/blob/next/source/drivers/epwm/v1/etpwm.h#L6462 

EPWM_ADCStartOfConversionType: https://github.com/TexasInstruments/mcupsdk-core/blob/next/source/drivers/epwm/v1/etpwm.h#L1283 

EPWM_ADCStartOfConversionSource: https://github.com/TexasInstruments/mcupsdk-core/blob/next/source/drivers/epwm/v1/etpwm.h#L1317C3-L1317C34 

Thank you,

Paula

hi，Paula

  The compiler cannot recognize these macros.

   I have added the following .h files.

  Which file should contain the definitions of these macros?

Hello Owens ,

The MCU core has dedicated Timer which supports the PWM generation.

So, I assume that with this timer you can drive the PWM signal.

In your use case , you need to drive the Ton Period is 2usec and Period is 6.6usec.

Does that solution work for you ?

Regards,

Anil.

hi,  Swargam & Paula

I have configured epwm -socA according to this api and it can output 120ns waveform. Could experts please review if there is any problem.

The image shows the function call
The compressed package shows the API implementation

user_soca_driver.zip

Hi Owens we will take a look and come back to you in a day or two

thank you,

Paula

hi,Paula

Thank you for pointing out the problem. The code is modified as follows

Hello Owens,

Swargam Anil said:

In your use case , you need to drive the Ton Period is 2usec and Period is 6.6usec.

Does that solution work for you ?

Please confirm if the above suggestion works for you or not ?

Regards,

Anil.

hi,Swargam 

  Our requirement is to align the rising edge of the pulse with the PD event of the pwm. According to my understanding, the pwm timer method is similar to another method: directly controlling the GPIO in the PWM ISR. Both methods involve cross-domain interrupt delay and jitter. Now these data are missing.

Dear Owens.

okay, please let us know which solution you will take. 

thanks a lot!

yong

hi，yong

 Our solution is as follows

owens shi said:

we use this 120ns pulse width and add other circuits to increase the pulse width of the soc pulse

Dear Owens

okay, then we can close this ticket, right?

thanks a lot!

yong

hi yong

  yes，you're right