AM623: SDK10.1 eMMC HS200 improvement

Bin, Tony,

By signal polarity, I will asume you are talking about data launch on pos edge or neg edge of clock.

If so, then V1P8_SIGNAL_ENA does affect "polarity".

When V1P8_SIGNAL_ENA is set, we switch to full cycle timing or data launch at clock rising edge.

~ Judith

Hi Bin, Judith,

Firstly, the patch resolved the issue. In order to identify the root cause and effective fact of the patch, customer split the patch to pieces, found the real effected change is "SDHCI_CTRL_VDD_180" operation.

Can I understand the original drive did not set SDHCI_CTRL_VDD_180 for eMMC as it always works at 1.8V, but SDHCI_CTRL_VDD_180 impact data/clock polarity beside signal voltage, and it was not mentioned in TRM register description, if so, need to update it, and share us the correct register field description.

Judith Mendez said:

When V1P8_SIGNAL_ENA is set, we switch to full cycle timing or data launch at clock rising edge.

We need more details to help understanding.

#1. From eMMC protocol standard, data always output(launch) at positive edge, is it at negative edge in default when SDHCI_CTRL_VDD_180 is not set? If so, the eMMC was working at wrong timing with old SDK? 

#2. It explained why customers always report HS200 not working stable. But one of my customer's board work with SDK8.3 and mass productioned, if the timing polarity is wrong, how to assess the risk it the board in field will fail or not stable at HS200?

#3. If my understanding of #1 is right, should be able to observe polarity changing on data/clock with/without SDHCI_CTRL_VDD_180 set. Is there waveform record when identify this issue.

#4. Do you mean full cycle=double edge for DDR mode? HS200 is single edge mode, it should be not relevant.

Hi Tony,

Please let us know if you still have question after Paul's explanation offline.

Update from offline by Paul:

Half-cycle timing – this is where data is launched on the negative edge of clock and latched on the following positive edge of clock.

Full-cycle timing – this is where data launched on the positive edge of clock and latched on the following positive edge of clock.

DDR – this is where data is launched on each edge of clock and latched on the following edge of clock.

The appropriate timing mode for each device is shown in the respective datasheet Switching Characteristics table and associated timing diagram.  For example, the AM62x device expects the host controller to operate in Half-cycle timing when you reference the Switching Characteristics of Legacy SDR and High Speed SDR modes.  You can see an example of Full-cycle timing when referencing the Switching Characteristics of HS200 mode.

Hi Paul,

Customer needs to evaluate the risk of boards working in wrong timing mode in field, Question as below:

As wrong configured to Half cycle timing for HS200 which should be full cycle timing. 

#1. What is the setup/hold time requirements of wrong configured HS200 receive mode, customer need the data similar as below table SDR timing at 200MHz.

#2. Also need the transmit timing data of HS200 wrong configured at half timing mode.

Closing this after the offline communication.