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AM625-Q1: Single channel OLDI output : only half display screen

Part Number: AM625-Q1
Other Parts Discussed in Thread: AM62P, AM625

Tool/software:

Hi Team,
We have custom board with OLDI port 0 output for Display 800x480 .
when i use 800x480 timing i get half display . Height seems fine . Width has issues

static const struct drm_display_mode custom_mode = {
 	.clock = 24750,
 	.hdisplay = 800,
 	.hsync_start = 800 + 54,
 	.hsync_end = 800 + 54 + 2,
 	.htotal = 800 + 54 + 2 + 44,
 	.vdisplay = 480,
 	.vsync_start = 480 + 49,
 	.vsync_end = 480 + 49 + 2,
 	.vtotal = 480 + 49 + 2 + 22,
 };
 static const struct panel_desc custom = {
 	.modes = &custom_mode,
 	.num_modes = 1,
 	.bpc = 8,
 	.size = {
 		.width = 152,
 		.height = 91,
 	},
 	.delay = {
 		.prepare = 50,
 		.disable = 50,
 	},
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
 };

but when i use 1600x480 , it display full 800x480 but Unfortunately modetest get 1600x480 so, the GUI we did for 800x480 is collapsed.
static const struct drm_display_mode custom_mode = {
 	.clock = 49500,
 	.hdisplay = 1600, 
 	.hsync_start = 1600 + 54,
 	.hsync_end = 1600 + 54 + 2,
 	.htotal = 1600 + 54 + 2 + 44,
 	.vdisplay = 480,
 	.vsync_start = 480 + 49,
 	.vsync_end = 480 + 49 + 2,
 	.vtotal = 480 + 49 + 2 + 22,
 };
 static const struct panel_desc custom = {
 	.modes = &custom_mode,
 	.num_modes = 1,
 	.bpc = 8,
 	.size = {
 		.width = 152,
 		.height = 91,
 	},
 	.delay = {
 		.prepare = 50,
 		.disable = 50,
 	},
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
 };

any idea why its happening?
this is the overlay we use FYR

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/**
 * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for AM625 - SK
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "k3-pinctrl.h"

&{/} {
	display {
        	compatible ="custom";
		port@0 {
			dual-lvds-odd-pixels;
			lcd_in0: endpoint {
				remote-endpoint = <&oldi_out0>;
			};
		};
    	};
	hdmi0: connector {
		status = "disabled";
	};
};

&dss {
    status = "okay";
};
&main_pmx0 {
	main_oldi0_pins_default: main-oldi0-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x0260, PIN_OUTPUT, 0) /* (AA5) OLDI0_A0N */
			AM62X_IOPAD(0x025c, PIN_OUTPUT, 0) /* (Y6) OLDI0_A0P */
			AM62X_IOPAD(0x0268, PIN_OUTPUT, 0) /* (AD3) OLDI0_A1N */
			AM62X_IOPAD(0x0264, PIN_OUTPUT, 0) /* (AB4) OLDI0_A1P */
			AM62X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (Y8) OLDI0_A2N */
			AM62X_IOPAD(0x026c, PIN_OUTPUT, 0) /* (AA8) OLDI0_A2P */
			AM62X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AB6) OLDI0_A3N */
			AM62X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AA7) OLDI0_A3P */
			AM62X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AC6) OLDI0_A4N */
			AM62X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AC5) OLDI0_A4P */
			AM62X_IOPAD(0x0288, PIN_OUTPUT, 0) /* (AE5) OLDI0_A5N */
			AM62X_IOPAD(0x0284, PIN_OUTPUT, 0) /* (AD6) OLDI0_A5P */
			AM62X_IOPAD(0x0290, PIN_OUTPUT, 0) /* (AE6) OLDI0_A6N */
			AM62X_IOPAD(0x028c, PIN_OUTPUT, 0) /* (AD7) OLDI0_A6P */
			AM62X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AD8) OLDI0_A7N */
			AM62X_IOPAD(0x0294, PIN_OUTPUT, 0) /* (AE7) OLDI0_A7P */
			AM62X_IOPAD(0x02a0, PIN_OUTPUT, 0) /* (AD4) OLDI0_CLK0N */
			AM62X_IOPAD(0x029c, PIN_OUTPUT, 0) /* (AE3) OLDI0_CLK0P */
			AM62X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (AE4) OLDI0_CLK1N */
			AM62X_IOPAD(0x02a4, PIN_OUTPUT, 0) /* (AD5) OLDI0_CLK1P */
		>;
	};
};

&dss {
	pinctrl-names = "default";
	pinctrl-0 = <&main_oldi0_pins_default &main_dss0_pins_default>;
};
&dss_ports {
 	#address-cells = <1>;
	#size-cells = <0>;   

    	/* VP1: Output to OLDI */
    	port@0 {
        	reg = <0>;
        	oldi_out0: endpoint {
            		remote-endpoint = <&lcd_in0>;
        	};
    	};
	port@1 {
                status = "disabled";
	};
};

&main_i2c1 {
	
	sii9022: sii9022@3b {
		status = "disabled";
	};
};

  • Hi Team,

    Half display, I mean 800 width UI got shrunk to 400 and Rest are black.
    like below image

    but 1600x480 is displaying completely. But Because of that resolution ,our 800x480 static GUI is collapsed

  • What is the resolution of your display panel?

  • Hi Divyansh,
    Our display panel resolution is 800x480 
    And we have OLDI to RGB (DS90CR286AMTD ) IC.

    and we are using A0 to A4 Ports.

  • Hey,
    As a part of the debug effort, can you please check and share the following:
    1. What is the pixel clock you see on probing the OLDI pin?
    2. What is the value inside register: 0x3020a160
    3. Can you please cross the timings and clocks you have configured in your dts with your panel vendor datasheet.

  • Hi Divyansh,

    1. Have difficulty probing them, will send you resut soon.
    2. Read at address 0x3020A160 (0xffff901b7160): 0x00001183

    3.Thanks.we set this exact timing of display panel we use , 

    .clock = 49500,
    .hdisplay = 800,
    .hsync_start = 800 + 210,
    .hsync_end = 800 + 210 + 10,
    .htotal = 800 + 210 + 10 + 46,
    .vdisplay = 480,
    .vsync_start = 480 + 22,
    .vsync_end = 480 + 22 + 10,
    .vtotal = 480 + 22 + 10 + 23,

    but still half display

  • Thanks.
    How did you compute the clock freq here? Was it given in the datasheet? What happens when you double it?

  • Hi Divyansh,

    Was it given in the datasheet?


    Typ Fclk was 33Mhz for panel.
    Went for Max approx 80 Refresh rate -> 49.5M/(1066*535).
    But I even  reduced clock frequency and tried .same output.

    What is the value inside register

    is it fine?

    What happens when you double it?

    I don't know if i can go to 50Mhz which is Fclk MAX defined in panel DS.
    thats why i tried 49.5.

  • If you have temporary fix to make linux believe 1600 is 800 , it will be use for us now.
    or any way to try different timings from linux shell to speed up debug?

  • Hi,
    Can you also please share results when you run kmsprint and kmstest. What do you see on screen on running kmstest with both 800x480 and 1600x480?

    Have difficulty probing them, will send you resut soon.

    This is an important debug point. Please share the results when you have them.

  • is it fine?

    The value of this register in our internal tests is 0x000011A5. You can check the TRM for further details on the VP1_OLDI_CFG register.
    Basically it means that we are using you are using JEIDA compatible single-link display (which shouldn't be any issue).
    and, your dts is working in independent mode, while our is working in clone mode (shouldn't be an issue again).

    Just to check if clone vs independent mode is making a difference, try using this dtso:

    /dts-v1/;
    /plugin/;
    
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    
    &{/} {
    	display0 {
    		compatible = "custom";
    		dual-lvds-odd-pixels;
    		port {
    			lcd0_in: endpoint {
    				remote-endpoint = <&oldi_0_out>;
    			};
    		};
    	};
    };
    
    &dss {
    	status = "okay";
    };
    
    &oldi0 {
    	status = "okay";
    };
    
    &oldi0_ports {
    	#address-cells = <1>;
    	#size-cells = <0>;
    
    	port@0 {
    		reg = <0>;
    		oldi_0_in: endpoint {
    			remote-endpoint = <&dpi0_out0>;
    		};
    	};
    
    	port@1 {
    		reg = <1>;
    		oldi_0_out: endpoint {
    			remote-endpoint = <&lcd0_in>;
    		};
    	};
    };
    
    &dss_ports {
    	#address-cells = <1>;
    	#size-cells = <0>;
    
    	/* VP1: Output to OLDI */
    	port@0 {
    		reg = <0>;
    		#address-cells = <1>;
    		#size-cells = <0>;
    
    		dpi0_out0: endpoint@0 {
    			reg = <0>;
    			remote-endpoint = <&oldi_0_in>;
    		};
    	};
    };



  • Hi Divyansh,

    shouldn't be an issue agai

    Thanks for your clarification.

    try using this dtso:

    okay.. we will try and let you know

    sorry for the delay
    Here is the OLDI CLK0 P , 
    1: 800x480 35 MHz clock expected : half is detected 18Mhz



    Modetest result:

    Encoders:
            id      crtc    type    possible crtcs  possible clones
            39      38      LVDS    0x00000001      0x00000001
    
            Connectors:
            id      encoder status          name            size (mm)       modes   encoders
            40      39      connected       LVDS-1          154x86          1       39
            modes:
                    index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
            #0 800x480 61.37 800 1010 1020 1066 480 502 512 535 35000 flags: ; type: preferred, driver
            props:
                    1 EDID:
                            flags: immutable blob
                            blobs:
    
                            value:
                    2 DPMS:
                            flags: enum
                            enums: On=0 Standby=1 Suspend=2 Off=3
                            value: 0
                    5 link-status:
                            flags: enum
                            enums: Good=0 Bad=1
                            value: 0
                    6 non-desktop:
                            flags: immutable range
                            values: 0 1
                            value: 0
                    4 TILE:
                            flags: immutable blob
                            blobs:
    
                            value:
    
            CRTCs:
            id      fb      pos     size
            38      53      (0,0)   (800x480)
            #0 800x480 61.37 800 1010 1020 1066 480 502 512 535 35000 flags: ; type: preferred, driver
            props:
                    24 VRR_ENABLED:
                            flags: range
                            values: 0 1
                            value: 0
                    27 CTM:
                            flags: blob
                            blobs:
    
                            value:
                    28 GAMMA_LUT:
                            flags: blob
                            blobs:
    
                            value:
                    29 GAMMA_LUT_SIZE:
                            flags: immutable range
                            values: 0 4294967295
                            value: 256
    
            Planes:
            id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
            31      38      53      0,0             0,0     0               0x00000001
            formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
            props:
                    8 type:
                            flags: immutable enum
                            enums: Overlay=0 Primary=1 Cursor=2
                            value: 1
                    30 IN_FORMATS:
                            flags: immutable blob
                            blobs:
    
                            value:
                                    01000000000000001d00000018000000
                                    01000000900000004152313241423132
                                    52413132524731364247313641523135
                                    41423135415232344142323452413234
                                    42413234524732344247323441523330
                                    41423330585231325842313252583132
                                    58523135584231355852323458423234
                                    52583234425832345852333058423330
                                    59555956555956594e56313200000000
                                    ffffff1f000000000000000000000000
                                    0000000000000000
                            in_formats blob decoded:
                                    AR12:  LINEAR(0x0)
                                    AB12:  LINEAR(0x0)
                                    RA12:  LINEAR(0x0)
                                    RG16:  LINEAR(0x0)
                                    BG16:  LINEAR(0x0)
                                    AR15:  LINEAR(0x0)
                                    AB15:  LINEAR(0x0)
                                    AR24:  LINEAR(0x0)
                                    AB24:  LINEAR(0x0)
                                    RA24:  LINEAR(0x0)
                                    BA24:  LINEAR(0x0)
                                    RG24:  LINEAR(0x0)
                                    BG24:  LINEAR(0x0)
                                    AR30:  LINEAR(0x0)
                                    AB30:  LINEAR(0x0)
                                    XR12:  LINEAR(0x0)
                                    XB12:  LINEAR(0x0)
                                    RX12:  LINEAR(0x0)
                                    XR15:  LINEAR(0x0)
                                    XB15:  LINEAR(0x0)
                                    XR24:  LINEAR(0x0)
                                    XB24:  LINEAR(0x0)
                                    RX24:  LINEAR(0x0)
                                    BX24:  LINEAR(0x0)
                                    XR30:  LINEAR(0x0)
                                    XB30:  LINEAR(0x0)
                                    YUYV:  LINEAR(0x0)
                                    UYVY:  LINEAR(0x0)
                                    NV12:  LINEAR(0x0)
                    33 zpos:
                            flags: range
                            values: 0 1
                            value: 0
                    34 COLOR_ENCODING:
                            flags: enum
                            enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                            value: 0
                    35 COLOR_RANGE:
                            flags: enum
                            enums: YCbCr limited range=0 YCbCr full range=1
                            value: 1
                    36 alpha:
                            flags: range
                            values: 0 65535
                            value: 65535
                    37 pixel blend mode:
                            flags: enum
                            enums: Pre-multiplied=0 Coverage=1
                            value: 0
            41      0       0       0,0             0,0     0               0x00000001
            formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
            props:
                    8 type:
                            flags: immutable enum
                            enums: Overlay=0 Primary=1 Cursor=2
                            value: 0
                    30 IN_FORMATS:
                            flags: immutable blob
                            blobs:
    
                            value:
                                    01000000000000001d00000018000000
                                    01000000900000004152313241423132
                                    52413132524731364247313641523135
                                    41423135415232344142323452413234
                                    42413234524732344247323441523330
                                    41423330585231325842313252583132
                                    58523135584231355852323458423234
                                    52583234425832345852333058423330
                                    59555956555956594e56313200000000
                                    ffffff1f000000000000000000000000
                                    0000000000000000
                            in_formats blob decoded:
                                    AR12:  LINEAR(0x0)
                                    AB12:  LINEAR(0x0)
                                    RA12:  LINEAR(0x0)
                                    RG16:  LINEAR(0x0)
                                    BG16:  LINEAR(0x0)
                                    AR15:  LINEAR(0x0)
                                    AB15:  LINEAR(0x0)
                                    AR24:  LINEAR(0x0)
                                    AB24:  LINEAR(0x0)
                                    RA24:  LINEAR(0x0)
                                    BA24:  LINEAR(0x0)
                                    RG24:  LINEAR(0x0)
                                    BG24:  LINEAR(0x0)
                                    AR30:  LINEAR(0x0)
                                    AB30:  LINEAR(0x0)
                                    XR12:  LINEAR(0x0)
                                    XB12:  LINEAR(0x0)
                                    RX12:  LINEAR(0x0)
                                    XR15:  LINEAR(0x0)
                                    XB15:  LINEAR(0x0)
                                    XR24:  LINEAR(0x0)
                                    XB24:  LINEAR(0x0)
                                    RX24:  LINEAR(0x0)
                                    BX24:  LINEAR(0x0)
                                    XR30:  LINEAR(0x0)
                                    XB30:  LINEAR(0x0)
                                    YUYV:  LINEAR(0x0)
                                    UYVY:  LINEAR(0x0)
                                    NV12:  LINEAR(0x0)
                    43 zpos:
                            flags: range
                            values: 0 1
                            value: 1
                    44 COLOR_ENCODING:
                            flags: enum
                            enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                            value: 0
                    45 COLOR_RANGE:
                            flags: enum
                            enums: YCbCr limited range=0 YCbCr full range=1
                            value: 1
                    46 alpha:
                            flags: range
                            values: 0 65535
                            value: 65535
                    47 pixel blend mode:
                            flags: enum
                            enums: Pre-multiplied=0 Coverage=1
                            value: 0
    
            Frame buffers:
            id      size    pitch

    2.1600x480 40Mhz expected : detected same half of it 20mhz


    modetest result:

    Encoders:
            id      crtc    type    possible crtcs  possible clones
            39      38      LVDS    0x00000001      0x00000001
    
            Connectors:
            id      encoder status          name            size (mm)       modes   encoders
            40      39      connected       LVDS-1          154x86          1       39
            modes:
                    index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
            #0 1600x480 40.07 1600 1810 1820 1866 480 502 512 535 40000 flags: ; type: preferred, driver
            props:
                    1 EDID:
                            flags: immutable blob
                            blobs:
    
                            value:
                    2 DPMS:
                            flags: enum
                            enums: On=0 Standby=1 Suspend=2 Off=3
                            value: 0
                    5 link-status:
                            flags: enum
                            enums: Good=0 Bad=1
                            value: 0
                    6 non-desktop:
                            flags: immutable range
                            values: 0 1
                            value: 0
                    4 TILE:
                            flags: immutable blob
                            blobs:
    
                            value:
    
            CRTCs:
            id      fb      pos     size
            38      53      (0,0)   (1600x480)
            #0 1600x480 40.07 1600 1810 1820 1866 480 502 512 535 40000 flags: ; type: preferred, driver
            props:
                    24 VRR_ENABLED:
                            flags: range
                            values: 0 1
                            value: 0
                    27 CTM:
                            flags: blob
                            blobs:
    
                            value:
                    28 GAMMA_LUT:
                            flags: blob
                            blobs:
    
                            value:
                    29 GAMMA_LUT_SIZE:
                            flags: immutable range
                            values: 0 4294967295
                            value: 256
    
            Planes:
            id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
            31      38      53      0,0             0,0     0               0x00000001
            formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
            props:
                    8 type:
                            flags: immutable enum
                            enums: Overlay=0 Primary=1 Cursor=2
                            value: 1
                    30 IN_FORMATS:
                            flags: immutable blob
                            blobs:
    
                            value:
                                    01000000000000001d00000018000000
                                    01000000900000004152313241423132
                                    52413132524731364247313641523135
                                    41423135415232344142323452413234
                                    42413234524732344247323441523330
                                    41423330585231325842313252583132
                                    58523135584231355852323458423234
                                    52583234425832345852333058423330
                                    59555956555956594e56313200000000
                                    ffffff1f000000000000000000000000
                                    0000000000000000
                            in_formats blob decoded:
                                    AR12:  LINEAR(0x0)
                                    AB12:  LINEAR(0x0)
                                    RA12:  LINEAR(0x0)
                                    RG16:  LINEAR(0x0)
                                    BG16:  LINEAR(0x0)
                                    AR15:  LINEAR(0x0)
                                    AB15:  LINEAR(0x0)
                                    AR24:  LINEAR(0x0)
                                    AB24:  LINEAR(0x0)
                                    RA24:  LINEAR(0x0)
                                    BA24:  LINEAR(0x0)
                                    RG24:  LINEAR(0x0)
                                    BG24:  LINEAR(0x0)
                                    AR30:  LINEAR(0x0)
                                    AB30:  LINEAR(0x0)
                                    XR12:  LINEAR(0x0)
                                    XB12:  LINEAR(0x0)
                                    RX12:  LINEAR(0x0)
                                    XR15:  LINEAR(0x0)
                                    XB15:  LINEAR(0x0)
                                    XR24:  LINEAR(0x0)
                                    XB24:  LINEAR(0x0)
                                    RX24:  LINEAR(0x0)
                                    BX24:  LINEAR(0x0)
                                    XR30:  LINEAR(0x0)
                                    XB30:  LINEAR(0x0)
                                    YUYV:  LINEAR(0x0)
                                    UYVY:  LINEAR(0x0)
                                    NV12:  LINEAR(0x0)
                    33 zpos:
                            flags: range
                            values: 0 1
                            value: 0
                    34 COLOR_ENCODING:
                            flags: enum
                            enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                            value: 0
                    35 COLOR_RANGE:
                            flags: enum
                            enums: YCbCr limited range=0 YCbCr full range=1
                            value: 1
                    36 alpha:
                            flags: range
                            values: 0 65535
                            value: 65535
                    37 pixel blend mode:
                            flags: enum
                            enums: Pre-multiplied=0 Coverage=1
                            value: 0
            41      0       0       0,0             0,0     0               0x00000001
            formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
            props:
                    8 type:
                            flags: immutable enum
                            enums: Overlay=0 Primary=1 Cursor=2
                            value: 0
                    30 IN_FORMATS:
                            flags: immutable blob
                            blobs:
    
                            value:
                                    01000000000000001d00000018000000
                                    01000000900000004152313241423132
                                    52413132524731364247313641523135
                                    41423135415232344142323452413234
                                    42413234524732344247323441523330
                                    41423330585231325842313252583132
                                    58523135584231355852323458423234
                                    52583234425832345852333058423330
                                    59555956555956594e56313200000000
                                    ffffff1f000000000000000000000000
                                    0000000000000000
                            in_formats blob decoded:
                                    AR12:  LINEAR(0x0)
                                    AB12:  LINEAR(0x0)
                                    RA12:  LINEAR(0x0)
                                    RG16:  LINEAR(0x0)
                                    BG16:  LINEAR(0x0)
                                    AR15:  LINEAR(0x0)
                                    AB15:  LINEAR(0x0)
                                    AR24:  LINEAR(0x0)
                                    AB24:  LINEAR(0x0)
                                    RA24:  LINEAR(0x0)
                                    BA24:  LINEAR(0x0)
                                    RG24:  LINEAR(0x0)
                                    BG24:  LINEAR(0x0)
                                    AR30:  LINEAR(0x0)
                                    AB30:  LINEAR(0x0)
                                    XR12:  LINEAR(0x0)
                                    XB12:  LINEAR(0x0)
                                    RX12:  LINEAR(0x0)
                                    XR15:  LINEAR(0x0)
                                    XB15:  LINEAR(0x0)
                                    XR24:  LINEAR(0x0)
                                    XB24:  LINEAR(0x0)
                                    RX24:  LINEAR(0x0)
                                    BX24:  LINEAR(0x0)
                                    XR30:  LINEAR(0x0)
                                    XB30:  LINEAR(0x0)
                                    YUYV:  LINEAR(0x0)
                                    UYVY:  LINEAR(0x0)
                                    NV12:  LINEAR(0x0)
                    43 zpos:
                            flags: range
                            values: 0 1
                            value: 1
                    44 COLOR_ENCODING:
                            flags: enum
                            enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                            value: 0
                    45 COLOR_RANGE:
                            flags: enum
                            enums: YCbCr limited range=0 YCbCr full range=1
                            value: 1
                    46 alpha:
                            flags: range
                            values: 0 65535
                            value: 65535
                    47 pixel blend mode:
                            flags: enum
                            enums: Pre-multiplied=0 Coverage=1
                            value: 0
    
            Frame buffers:
            id      size    pitch

    and 

    if you have device tree definition to specify timing parameter , please let us know ,

    tried this, it did not work

    // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
    /**
     * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for AM625 - SK
     *
     * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
     */
    
    /dts-v1/;
    /plugin/;
    
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    
    #include "k3-pinctrl.h"
    
    &{/} {
    	panel_lvds: panel-lvds {
    		bootph-pre-ram;
    		compatible = "simple-panel";
    		status= "okay";
    		width-mm = <154>;
    		height-mm = <86>;
    		data-mapping = "jeida-24";
    		panel-timings {
    				bootph-pre-ram;
    				clock-frequency = <35000>;
    				hactive = <800>;
    				vactive = <480>;
    				hback-porch = <46>;
    				hfront-porch = <210>;
    				vback-porch = <23>;
    				vfront-porch = <22>;
    				hsync-len = <20>;
    				vsync-len = <10>;
    				de-active = <1>;
    		};
    		port@0 {
    			dual-lvds-odd-pixels;
    			lcd_in0: endpoint {
    				remote-endpoint = <&oldi_out0>;
    			};
    		};
        	};
    	hdmi0: connector {
    		status = "disabled";
    	};
    };
    
    &dss {
        status = "okay";
    };
    &main_pmx0 {
    	main_oldi0_pins_default: main-oldi0-pins-default {
    		pinctrl-single,pins = <
    			AM62X_IOPAD(0x0260, PIN_OUTPUT, 0) /* (AA5) OLDI0_A0N */
    			AM62X_IOPAD(0x025c, PIN_OUTPUT, 0) /* (Y6) OLDI0_A0P */
    			AM62X_IOPAD(0x0268, PIN_OUTPUT, 0) /* (AD3) OLDI0_A1N */
    			AM62X_IOPAD(0x0264, PIN_OUTPUT, 0) /* (AB4) OLDI0_A1P */
    			AM62X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (Y8) OLDI0_A2N */
    			AM62X_IOPAD(0x026c, PIN_OUTPUT, 0) /* (AA8) OLDI0_A2P */
    			AM62X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AB6) OLDI0_A3N */
    			AM62X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AA7) OLDI0_A3P */
    			AM62X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AC6) OLDI0_A4N */
    			AM62X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AC5) OLDI0_A4P */
    			AM62X_IOPAD(0x0288, PIN_OUTPUT, 0) /* (AE5) OLDI0_A5N */
    			AM62X_IOPAD(0x0284, PIN_OUTPUT, 0) /* (AD6) OLDI0_A5P */
    			AM62X_IOPAD(0x0290, PIN_OUTPUT, 0) /* (AE6) OLDI0_A6N */
    			AM62X_IOPAD(0x028c, PIN_OUTPUT, 0) /* (AD7) OLDI0_A6P */
    			AM62X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AD8) OLDI0_A7N */
    			AM62X_IOPAD(0x0294, PIN_OUTPUT, 0) /* (AE7) OLDI0_A7P */
    			AM62X_IOPAD(0x02a0, PIN_OUTPUT, 0) /* (AD4) OLDI0_CLK0N */
    			AM62X_IOPAD(0x029c, PIN_OUTPUT, 0) /* (AE3) OLDI0_CLK0P */
    			AM62X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (AE4) OLDI0_CLK1N */
    			AM62X_IOPAD(0x02a4, PIN_OUTPUT, 0) /* (AD5) OLDI0_CLK1P */
    		>;
    	};
    };
    
    &dss {
    	pinctrl-names = "default";
    	pinctrl-0 = <&main_oldi0_pins_default &main_dss0_pins_default>;
    };
    &dss_ports {
     	#address-cells = <1>;
    	#size-cells = <0>;   
    
        	/* VP1: Output to OLDI */
        	port@0 {
            	reg = <0>;
            	oldi_out0: endpoint {
                		remote-endpoint = <&lcd_in0>;
            	};
        	};
    	port@1 {
                    status = "disabled";
    	};
    };
    
    &main_i2c1 {
    	
    	sii9022: sii9022@3b {
    		status = "disabled";
    	};
    };

  • Hi Divyansh,
    Gentle reminder

  • Hi,
    Thanks for the probe results.
    As an experiment to solve this issue, can you please try disabling splash in u-boot.
    You can find the instructions here: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/latest/exports/docs/linux/Foundational_Components/U-Boot/UG-Splash-Screen.html#disabling-splash-screen 
    Do you still see half-clock/half-display after this?

  • Hi Divyansh,
    Splash screen still comes. 4 penguins on top left corner.
    What i did was added this am62x_evm_prune_splashscreen.config to configs/  in  our uboot repo and built an image.
    Still getting 18Mhz for 35 Mhz clock set.

    should i add those contents to a53 defconfig ? or  should i try disabling it in ti-linux kernel defconfigs too ?

  • Hi,
    Splashscreen in U-Boot refers to the TI logo. Penguins are rendered by Kernel.

    should i add those contents to a53 defconfig ? or  should i try disabling it in ti-linux kernel defconfigs too ?

    Not really needed. What do you see in the output of `k3conf dump clock | grep DSS0_DPI_0` for either cases? Is it the expected frequency, or the actual frequency?

  • Hi Divyansh,
    Ti logo we never got on display.

    `k3conf dump clock | grep DSS0_DPI_0`

    For 35Mhz 800x480 | Halfscreen
    |   186     |     0    | DEV_DSS0_DPI_0_IN_CLK                                                                                | CLK_STATE_READY     | 244800000

    No difference for uboot splash disable and enable.

  • Hi,
    Can you please remove the following line from both your and my dts:

    dual-lvds-odd-pixels;

    and check again if it makes any difference with either of our patches.

  • Hi Divyansh,
    Made the change, still getting same output.

  • Can you also please share results when you run kmsprint and kmstest. What do you see on screen on running kmstest with both 800x480 and 1600x480?

    Hi, I am still waiting on these results. Please share these

  • Also, does your panel really use JEIDA format.
    Can you try changing that to the following and see what happens?

    .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG

  • HI Divyansh,

    We have "modetest -M tidss" results already for 800x480 and 1600x480
    below one is 800x480

    Modetest result:

    below one is 1600x480

    Modetest result:

    i thought kms and modetest are same, isn't ?

  • Hi  Divyansh,

    does your panel really
    we have OLDI to RGB (DS90CR286AMTD ) IC

    the display adapter which uses this IC is designed for JEIDA. 

    I hope trying SPWG wont affect my display panel. Tomorrow i will try that and let you know. 

  • Would like to check what clock kmprint and kmstest report. I have seen the modetest results.

  • Hi Divyansh,

    try changing that to the following and see what happens?

    root@am62xx-evm:~# kmsprint
    Connector 0 (40) LVDS-1 (connected)
      Encoder 0 (39) LVDS
        Crtc 0 (38) 800x480@61.37 35.000 800/210/10/46/? 480/22/10/23/? 61 (61.37) P|D
          Plane 0 (31) fb-id: 53 (crtcs: 0) 0,0 800x480 -> 0,0 800x480 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
            FB 53 800x480 XR24
            
    root@am62xx-evm:~# kmsxxtest
    Connector 0/@40: LVDS-1
      Crtc 0/@38: 800x480@61.37 35.000 800/210/10/46/? 480/22/10/23/? 61 (61.37) P|D
      Plane 0/@31: 0,0-800x480
        Fb 49 800x480-XR24
    press enter to exit

    there is a block orientation change 



    will send the 800x480 and 1600x480 in an hour

  • Hi  Divyansh,

    check what clock kmprint and kmstest report

    reverted to jeida

    1.800x480 35Mhz

    root@am62xx-evm:~# kmsprint
    Connector 0 (40) LVDS-1 (connected)
      Encoder 0 (39) LVDS
        Crtc 0 (38) 800x480@60.80 35.000 800/210/20/46/? 480/22/10/23/? 61 (60.80) P|D
          Plane 0 (31) fb-id: 50 (crtcs: 0) 0,0 800x480 -> 0,0 800x480 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
            FB 50 800x480 XR24
    
    root@am62xx-evm:~# kmsxxtest
    Connector 0/@40: LVDS-1
      Crtc 0/@38: 800x480@60.80 35.000 800/210/20/46/? 480/22/10/23/? 61 (60.80) P|D
      Plane 0/@31: 0,0-800x480
        Fb 49 800x480-XR24


    2.1600x480 40Mhz

    root@am62xx-evm:~# kmsprint
    Connector 0 (40) LVDS-1 (connected)
      Encoder 0 (39) LVDS
        Crtc 0 (38) 1600x480@39.85 40.000 1600/210/20/46/? 480/22/10/23/? 40 (39.85) P|D
          Plane 0 (31) fb-id: 50 (crtcs: 0) 0,0 1600x480 -> 0,0 1600x480 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
            FB 50 1600x480 XR24
    
    root@am62xx-evm:~# kmsxxtest
    Connector 0/@40: LVDS-1
      Crtc 0/@38: 1600x480@39.85 40.000 1600/210/20/46/? 480/22/10/23/? 40 (39.85) P|D
      Plane 0/@31: 0,0-1600x480
        Fb 49 1600x480-XR24
    press enter to exit




    is there any possibility because of SDK 9 ?

  • Thanks for the results.

    is there any possibility because of SDK 9 ?

    There are constant improvements that we do with each SDK release, would urge you to at least test your setup on SDK11. 

  • okay.. We are setting it up parallelly. Since we are using AGL, it takes time.
    but have you faced any such Freq/2 issue on SDK 9.?
    if possible , Could try a oldi panel with EVM of SDK 9.02 , and try if results are same ? since trying downgraded image is possible immediately.
     

  • I will be trying using your exact patch with SDK 9.0, but please expect response in this regard by next week.

  • Sure Divyansh, it will be really helpful if you get results sooner than that. 
    and meanwhile , we will also inform anything we find. if you have any suggestions to test from our side ,please let me know.
    and I have one doubt, 
    Can am62x drive two displays with half half content on each display ? so that together they will become one display output . If yes , in that case ,will each display get half frequency and half resolution ? 

  • Hi Divyansh,
    Can you suggest a device tree definition that uses panel-lvds instead of panel-simple ? 

  • Can am62x drive two displays with half half content on each display ? so that together they will become one display output . If yes , in that case ,will each display get half frequency and half resolution ? 

    Some userspace application will have to stitch that.

    Can you suggest a device tree definition that uses panel-lvds instead of panel-simple

    Unfortunately, we do not have any such example.

    Please be patient, will update you when I have some results.

  • Okay Divyansh, Thanks for your clarification .We will wait.

  • Hi Divyansh,

    Gentle Reminder. 
    dual-lvds-odd-pixels; removal had no effect. So what is the proper dts definition for single channel? and should i also add the lvds definition in uboot dts ?

  • Hi Pawan,
    I tested your dts on SDK 9.0, (and their equivalents for newer SDKs) on both AM62x and AM62P.

    The equivalent versions work on on AM62P, but I am currently debugging into why it does not work on AM62x (even with newer SDKs).
    Will hopefully have an update for you this Friday, but feel free to ping again if I don't.

  • Hi Divyansh,

    does not work

    you mean , no display output or same half clock ? 

    thanks for your update. 

  • I see random colored vertical lines on screen, not limited to half-screen. Debugging it, will get back to you.

  • Hi Divyansh,

    random colored vertical lines on screen

    We too got the same when we connected directly to lvds panel from Orient, we got modetest connected status, tried glmmark and we could sense glmark is running when started and stopped , there was some difference , hard to notice on camera because vertical lines dominated that.
    any progress on that ? 
     

  • If you were seeing vertical lines initially, what changes you did to atleast see half screen?

  • No actually , it was different, direct lvds input panel 1024x600 of orient. We dropped it since we could not get output and also we wire soldered lvds lines from our am625 board connectors to panel..

    We got half screen on the actual application, rgb input panel  800x480 with Adapter board which has DS90CR286AMTD  IC, this board came from EMS, week after  giving up orient. 
    To sum it up,

    1. before actual board came, we tested on  orient with soldered wires, got vertical lines, dropped it.

    2. after actual board arrival, we tested with proper ffc cables , got halfscreen.

    it will be very helpful if give us probed lvds +/- frequency of your setup and programmed pixel clock freq for which you got vertical lines.

  • Hi Divyansh,
    Gentle reminder.

  • Hi Pawan,
    Sorry for the delay. Our dev team is actively working on the issue by comparing AM62x and AM62P counter parts.

    Currently I do not have the probing setup ready, but will share an update with you as soon as I can.

  • Can you please try this and share results:
    In the file: <U-boot Repo>/configs/am62x_evm_a53_defconfig
    Replace the following line:

    #include <configs/am62x_a53_splashscreen.config>

    with

    #include <configs/am62x_evm_prune_splashscreen.config>

    Build and  install u-boot binaries and retry. Do you see any improvement? For me, I see proper display instead of vertical lines.

  • Hi Divyansh,
    Sorry for the delayed response. 
    We applied the change, still getting Half clock and Half screen.

    i have few queries.

    1. Were you able to reproduce our case in EVM, there is forum of half screen happened on EVM , any idea about it?
    i dont know how its happening but feels answer's inside am62x. 
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1328612/sk-am62-am62xx-evm-lvds-display-half-screen-problem
    note: we have verified that our DT does not have HDMI related nodes on LVDS dts as mentioned in above forum.

    2. i think , SK-LCD1 is using this panel ,which is dual channel lvds, Any single channel panel was tried during your development or validation of single channel oldi output  , if so could you provide that panel part no, since we may try to procure and  validate on our evm and evm compatible our image try if possible ?

    3. What would be the result look like if  output of am62x is programmed single channel for a dual channel panel? 

    we will try other possibilities in the mean time and let you know within within this week .

  • 1. After disabling the splash, the dts works.

    2. The single-link we used is https://www.ti.com/tool/TMDSLCD1EVM but we also use a bridge to convert dual-link output from our EVMs to single-link. This adapter is currently experimental and internal so cannot share details on the ones we use.

    3. Visually the output remains the same on am62x with single-link.

    we will try other possibilities in the mean time and let you know within within this week .

    Thanks, will be waiting.

  • Hi Divyansh,

    i have queries,

    .1.  I'm confused, if

    Visually the output remains the same on am62x with single-link.

    then why its needed for a 

    bridge to convert dual-link output from our EVMs to single-link.

    . It can be directly interfaced with single link OLDI panel from EVM isn't it ? 

    adapter is currently experimental and internal so cannot share

    2. I understand, may i know the reason for the dual to single link conversion ? Because if thats the case, do i need to make such adapter for our single link Panel ?


  • then why its needed

    Dual link would provide capability to provide higher resolution/fps than single link.

    It can be directly interfaced with single link OLDI panel from EVM isn't it ? 
    may i know the reason for the dual to single link conversion ? Because if thats the case, do i need to make such adapter for our single link Panel

    TI's AM62x EVM cannot be directly interfaced with single link OLDI. The EVM port only supports dual link OLDI. You may not need the adaptor if you are directly interfacing with SoC instead of EVM.

  • Hi Divyansh
    Thanks for your explanation .

    I have found the solution, when replacing the uboot dts default panel-lvds with kernel dts definiton , I got complete output.

    Dual link would provide capability to provide higher resolution/fps than single link

    Could you provide maximum how much Resolution / fps can be achieved through Single link ?, our design depends on single link..

  • I do not have exact numbers for resolution per say, but max. pixel clock that can be supported is 165 MHz. You can estimate if your single-link display is supported or not by calculating the pixel clock requirement for your resolution against 165 MHz.

  • Okay..Understood. Thank you Divyansh for your effort on deduction, it was really helpful.