AM625: EThernet switch with am625

Hello, 

1. What Linux SDK version are you using? Are you able to work on the SDK 10.01 or newer?

2. Can you share what DTS configuration you have for the CPSW nodes? Is port 5 on your switch the one that is connected to port2 on the AM625 board? 

-Daolin

hi Daolin Qiu,

/# uname -r
6.1.80-6.7.0-devel+git.603f75dc931d

SDK version we are using is 6.1.80-6.7.0-devel+git.603f75dc931d.

&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii1>;
	status = "disabled";
};

/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
	phy-handle = <&cpsw3g_phy0>;
	phy-mode = "rgmii-rxid";
	status = "disabled";
};

/* Verdin ETH_2_RGMII */
&cpsw_port2 {
	status = "disabled";
};

/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
	assigned-clocks = <&k3_clks 157 20>;
	assigned-clock-parents = <&k3_clks 157 22>;
	assigned-clock-rates = <25000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eth_clock>, <&pinctrl_mdio>;
	status = "disabled";

	cpsw3g_phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-id2000.a231";
		reg = <0>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_eth_int>, <&pinctrl_eth_reset>;
		reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>;
		reset-assert-us = <10>;
		reset-deassert-us = <1000>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
	};
};/

* Verdin ETHs */
&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
	status = "okay";
};

/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
	status = "okay";
	 cpsw3g_phy1: ethernet-phy@7 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <7>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
		micrel,led-mode = <0>;
	};
};

/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
	status = "okay";
};

/* Verdin ETH_2_RGMII */
&cpsw_port2 {
	phy-handle = <&cpsw3g_phy1>;
	phy-mode = "rgmii-rxid";
	status = "okay";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

lan9374: switch@1 {
                    compatible = "microchip,lan9374";
                    reg = <1>;
                    spi-max-frequency = <2000000>;
                    ethernet-ports {
                            #address-cells = <1>;
                            #size-cells = <0>;
 
                            port@0 {
                                    reg = <0>;
                                    label = "lan1";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy0>;
                            };
 
                            port@1 {
                                    reg = <1>;
                                    label = "lan2";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy1>;
                            };
 
                            port@2 {
                                    reg = <2>;
                                    label = "lan4";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy2>;
                            };
 
                            port@3 {
                                    reg = <3>;
                                    label = "lan6";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy3>;
                            };
 
                            port@4 {
                                    reg = <4>;
                                    phy-mode = "rgmii";
                                    tx-internal-delay-ps = <2000>;
                                    rx-internal-delay-ps = <2000>;
                                    ethernet = <&cpsw_port2>;
 
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
 
                            port@5 {
                                    reg = <5>;
                                    label = "lan7";
                                    phy-mode = "rgmii";
                                    tx-internal-delay-ps = <2000>;
                                    rx-internal-delay-ps = <2000>;
 
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
 
                            port@6 {
                                    reg = <6>;
                                    label = "lan5";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy6>;
                            };
 
                            port@7 {
                                    reg = <7>;
                                    label = "lan3";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy7>;
                            };
                    };
 
                    mdio {
                            #address-cells = <1>;
                            #size-cells = <0>;
 
                            t1phy0: ethernet-phy@0{
                                    reg = <0x0>;
                            };
 
                            t1phy1: ethernet-phy@1{
                                    reg = <0x1>;
                            };
 
                            t1phy2: ethernet-phy@2{
                                    reg = <0x2>;
                            };
 
                            t1phy3: ethernet-phy@3{
                                    reg = <0x3>;
                            };
 
                            t1phy6: ethernet-phy@6{
                                    reg = <0x6>;
                            };
 
                            t1phy7: ethernet-phy@7{
                                    reg = <0x7>;
                            };
                    };
            };
            

Hello,

It looks the "spi spi0.1: deferred probe pending" might be indicating something wrong with the driver for the SPI device (your switch) is waiting to be probed but the probe hasn't occurred. Did you check with your switch vendor that your device tree settings for the switch is correctly set? Also, is there an existing Linux driver for your specific switch? If there is one, did you make sure to enable it in your kernel configuration?

Please note, these are purely suggestions, we at TI cannot provide direct support on integrating your switch and can only provide some suggestions.

-Daolin

Hi Daolin Qiu,

Thanks for your inputs,

we have somehow fixed the issue of deferred probind and it was not because of the SPI driver for LAN9374. This LAN9374 is connected to the RGMII2 of the AM62x and when we use cpsw_port2 as  a reference node for the LAN9374, the driver does not load  and we drfeered probing.

but when i use cpsw3g as a reference port all works fine except the ping.

below is the device tree.

/* Verdin ETHs */
&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
	status = "okay";
	
		fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
	status = "okay";
	/* cpsw3g_phy1: ethernet-phy@7 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <7>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
		micrel,led-mode = <0>;
	}; */
};

/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
	status = "okay";
};

/* Verdin ETH_2_RGMII */
&cpsw_port2 {
	phy-mode = "rgmii-id";
	status = "disabled";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

lan9374: switch@1 {
                    compatible = "microchip,lan9374";
                    reg = <1>;
                    spi-max-frequency = <44000000>;
 
                    ethernet-ports {
                            #address-cells = <1>;
                            #size-cells = <0>;
 
                            port@0 {
                                    reg = <0>;
                                    label = "lan1";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy0>;
                            };
 
                            port@1 {
                                    reg = <1>;
                                    label = "lan2";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy1>;
                            };
 
                            port@2 {
                                    reg = <2>;
                                    label = "lan4";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy2>;
                            };
 
                            port@3 {
                                    reg = <3>;
                                    label = "lan6";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy3>;
                            };
 
                            port@4 {
                                    reg = <4>;
                                    phy-mode = "rgmii-id";
                                    tx-internal-delay-ps = <2000>;
                                    rx-internal-delay-ps = <2000>;
                                    ethernet = <&cpsw3g>;
 
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
 
                            port@5 {
                                    reg = <5>;
                                    label = "lan7";
                                    phy-mode = "rgmii-id";
                                    tx-internal-delay-ps = <2000>;
                                    rx-internal-delay-ps = <2000>;
 
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
 
                            port@6 {
                                    reg = <6>;
                                    label = "lan5";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy6>;
                            };
 
                            port@7 {
                                    reg = <7>;
                                    label = "lan3";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy7>;
                            };
                    };
 
                    mdio {
                            #address-cells = <1>;
                            #size-cells = <0>;
 
                            t1phy0: ethernet-phy@0{
                                    reg = <0x0>;
                            };
 
                            t1phy1: ethernet-phy@1{
                                    reg = <0x1>;
                            };
 
                            t1phy2: ethernet-phy@2{
                                    reg = <0x2>;
                            };
 
                            t1phy3: ethernet-phy@3{
                                    reg = <0x3>;
                            };
 
                            t1phy6: ethernet-phy@6{
                                    reg = <0x6>;
                            };
 
                            t1phy7: ethernet-phy@7{
                                    reg = <0x7>;
                            };
                    };
            };
            
            

wih the ip link show command i get the below logs

1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
    link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1502 qdisc mq state UP mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:ea:67:48 brd ff:ff:ff:ff:ff:ff
3: lan1@eth0: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:ea:67:48 brd ff:ff:ff:ff:ff:ff
4: lan2@eth0: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:ea:67:48 brd ff:ff:ff:ff:ff:ff
5: lan4@eth0: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:ea:67:48 brd ff:ff:ff:ff:ff:ff
6: lan6@eth0: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:ea:67:48 brd ff:ff:ff:ff:ff:ff
7: lan7@eth0: <BROADCAST,MULTICAST,DYNAMIC,UP,LOWER_UP> mtu 1500 qdisc noqueue state UP mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:ea:67:48 brd ff:ff:ff:ff:ff:ff
8: lan5@eth0: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:ea:67:48 brd ff:ff:ff:ff:ff:ff
9: lan3@eth0: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:ea:67:48 brd ff:ff:ff:ff:ff:ff

i feel that LAN is somehow trying to use eth0 instead of eth1, please correct me if i am wrong. or how cani verify that RGMII2 is used by LAN2 for communication.

because currently when i assign an IP usng ifconfig for LAN ports , ping does not work.

 to add More info LAN9374 is connected to the RGMII2, so i believe this should get connected to the eth1 port, in my system i can see all this ports are connected to eth0. if i give command ip link set eth0 down, the LAN9374 ports are going Down.

so please suggest i can i connect the LAN9374 ports to eth1.

please let me know

Hi,

naveenkumar Muthusamy said:

we have somehow fixed the issue of deferred probind and it was not because of the SPI driver for LAN9374. This LAN9374 is connected to the RGMII2 of the AM62x and when we use cpsw_port2 as  a reference node for the LAN9374, the driver does not load  and we drfeered probing.

but when i use cpsw3g as a reference port all works fine except the ping.

Good to hear that you figured out the deferred probe issue.

naveenkumar Muthusamy said:

 to add More info LAN9374 is connected to the RGMII2, so i believe this should get connected to the eth1 port, in my system i can see all this ports are connected to eth0. if i give command ip link set eth0 down, the LAN9374 ports are going Down.

so please suggest i can i connect the LAN9374 ports to eth1.

Are you using the "aliases" property in your device tree? From my understanding, the aliases property is used to specify which interface name gets attached to a specific device configured in the DTS. For example, the below is used in the AM64x EVM DTS (k3-am642-evm.dts) to especially configure eth0 interface to the &cpsw_port1 and eth1 to &cpsw_port2. Perhaps the same can be done for the LAN9374 ports to eth1 interface for your case.

aliases {
    serial0 = &mcu_uart0;
    serial1 = &main_uart1;
    serial2 = &main_uart0;
    serial3 = &main_uart3;
    i2c0 = &main_i2c0;
    i2c1 = &main_i2c1;
    mmc0 = &sdhci0;
    mmc1 = &sdhci1;
    ethernet0 = &cpsw_port1;
    ethernet1 = &cpsw_port2;
    ethernet2 = &icssg1_emac0;
};

-Daolin

Hi Daolin Qiu, 

In the device tree I have shared, I have used the cpsw3g as the reference for ethernet port. 

And in the logs of ip link show all the LAN ports seem to be connected to etho. If I want the LAN to use eth1, what should be done?

Hi Daolin Qiu,

After a lot of investigation I have understood that the switch needs the ethernet controller as a reference for registering the ports. So when I use cpsw3g all lan ports are registered and also to make it connected to eth1 i believe some dsa driver level changed are required.

Kindly correct me if I am wrong. The current driver always connects to the port0 only.

hi Daolin Qiu,

Any update on this issue?

Hi Naveenkumar, 

naveenkumar Muthusamy said:

So when I use cpsw3g all lan ports are registered and also to make it connected to eth1 i believe some dsa driver level changed are required.

Apologies for the delayed response. I'm a bit confused by this statement, does using cpsw3g as a reference as you specified not achieve your goal of connecting to eth1? Can you point me to specifically what DSA driver you are talking about?

-Daolin

Hi Daolin Qiu,

Thanks for your reply.

We have checked few other devices in which each port has a separate controller with separate memory address in device tree. in this case, In device tree, if i  want to connect port2, i can directly give the node name as a reference and it works. but in case of am62x, we have node cpsw3g from which eth0 and eth1 are derived. here when i give the reference of cpsw_port2, the switch is not at all registered and i don't get LAN ports from switch. instead of this if give cpsw3g the switch gets registered and i get LAN ports from switch but the switch always gets connected to eth0 and i am unable ping any of the ethernet address.

Please check the logs i have provided above.

In my understanding, DSA driver just takes only one port in the reference node from cpsw3g which is by default eth0. in my case eth1 should be connected.

so i need your support in modifying the driver to connect the eth1.

Please provide your suggestions here.

Hi Naveenkumar, 

Daolin Qiu said:

Are you using the "aliases" property in your device tree? From my understanding, the aliases property is used to specify which interface name gets attached to a specific device configured in the DTS. For example, the below is used in the AM64x EVM DTS (k3-am642-evm.dts) to especially configure eth0 interface to the &cpsw_port1 and eth1 to &cpsw_port2. Perhaps the same can be done for the LAN9374 ports to eth1 interface for your case.

naveenkumar Muthusamy said:

In the device tree I have shared, I have used the cpsw3g as the reference for ethernet port. 

Your device tree that you have shared did not include the use of "aliases" property" from what I could see. Have you tried to use aliases for your LAN9374 ports yet? 

naveenkumar Muthusamy said:

In my understanding, DSA driver just takes only one port in the reference node from cpsw3g which is by default eth0. in my case eth1 should be connected.

so i need your support in modifying the driver to connect the eth1.

I will need some time to discuss this with a colleague. I plan to update you on this tomorrow or Friday. Please kindly ping this thread if you don't receive a response by Friday.

-Daolin

Hi Naveenkumar, 

Why are you disabling cpsw_port2 in your DTS?

/* Verdin ETH_2_RGMII */
&cpsw_port2 {
	phy-mode = "rgmii-id";
	status = "disabled";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

Are you able to share a snippet of your schematic of what and how you attached both CPSW ports? Please note, this is a public forum so anything attached here will be publicly viewable. If this is a problem for you, you can send a direct message on E2E to me with the schematic.

How are you controlling your switch, through MDIO or through SPI?

Are you able to share your entire DTS?

Can you also give an updated version of your current full boot log? We want to see how your switch driver is identifying itself in the boot log.

Daolin Qiu said:

Can you point me to specifically what DSA driver you are talking about?

Can you additionally point me to specifically what DSA driver you are talking about? Perhaps a file path from the top-level Linux directory.

-Daolin

Hi Daolin Qiu,

 Why are you disabling cpsw_port2 in your DTS?

we were trying to debug the issue on LAN9374, so we kept cpsw_port2 as disabled but it made no difference.

in our latest device tree which we tested cpsw_port2 is enabled but still lan9374 ports are connected to eth0 only.

dsa drivers are found in directory:

/net/dsa/

the files are dsa.c and dsa2.c

Hi Naveenkumar, 

Daolin Qiu said:

Are you able to share a snippet of your schematic of what and how you attached both CPSW ports? Please note, this is a public forum so anything attached here will be publicly viewable. If this is a problem for you, you can send a direct message on E2E to me with the schematic.

How are you controlling your switch, through MDIO or through SPI?

Are you able to share your entire DTS?

Can you also give an updated version of your current full boot log? We want to see how your switch driver is identifying itself in the boot log.

Thanks for sharing the detail about why cpsw_port2 is disabled and which dsa drivers you are referencing. 

Can you additionally share an updated version of your full boot log and confirm whether you are controlling your switch through MDIO or through SPI (I'm guessing SPI since your latest DTS sent through direct message references the spi node)?

-Daolin

Hi Daolin Qiu,

I have shared the details over Message.Please check and let me know.

Hi Naveenkumar, 

Thanks for sharing the boot log and full DTS. I still don't seem to see where CPSW port 1 is attached to in your schematic, can you also share that?

"Your schematic seems to show just the Switch attachment to CPSW port 2, can you also show in your schematics how CPSW port 1 is connected and with what is CPSW port 1 connected to? "

I will take a closer look into this next week.

-Daolin

Hi Naveenkumar, 

Looking at your latest full DTS, it looks like you changed the reference in your switch node to &cpsw3g back to &cpsw_port2? From my understanding, previously when you referenced &cpsw_port2 it leads to probe errors. Unfortunately, because we at TI don't have a way to test a switch connection to our AM6x SoCs, the support we can offer is limited.

That being said, looking at a couple other E2E threads where other customers are looking to implement a similar setup, the reference to &cpsw3g appears to be what is necessary to get past the probe error. Additionally, it looks like some customers had to patch the DSA kernel driver to get past the problem of getting linked to the wrong eth port. See https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1131909/am6442-device-tree-with-marvell-switch-88e6341/4219456#4219456 

While I discuss internally with a colleague on this issue, it may be worth checking what the other customer had patched to the DSA kernel driver and see if works for your system.

Please kindly ping this thread again if you don't hear a response by Wednesday.

-Daolin

Hi Daolin Qiu,

i followed the the instructions shared the post from the link, but i am getting below error,

root@verdin-am62-15361864:~# dmesg | grep lan
[    0.000000] Kernel command line: root=PARTUUID=541926bb-02 ro rootwait console=tty1 console=ttyS2,115200 consoleblank=0 earlycon=ns16550a,mmio32,0x02800000
[    4.791611] ksz-switch spi0.1 lan1 (uninitialized): validation of internal with support 00000000,00000000,00006280 and advertisement 00000000,00000000,00000280 failed: -EINVAL
[    4.791795] ksz-switch spi0.1 lan1 (uninitialized): failed to connect to PHY: -EINVAL
[    4.791803] ksz-switch spi0.1 lan1 (uninitialized): error -22 setting up PHY for tree 1, switch 0, port 0
[    4.792245] ksz-switch spi0.1 lan2 (uninitialized): validation of internal with support 00000000,00000000,00006280 and advertisement 00000000,00000000,00000280 failed: -EINVAL
[    4.792406] ksz-switch spi0.1 lan2 (uninitialized): failed to connect to PHY: -EINVAL
[    4.792412] ksz-switch spi0.1 lan2 (uninitialized): error -22 setting up PHY for tree 1, switch 0, port 1
[    4.792729] ksz-switch spi0.1 lan4 (uninitialized): validation of internal with support 00000000,00000000,00006280 and advertisement 00000000,00000000,00000280 failed: -EINVAL
[    4.792884] ksz-switch spi0.1 lan4 (uninitialized): failed to connect to PHY: -EINVAL
[    4.792890] ksz-switch spi0.1 lan4 (uninitialized): error -22 setting up PHY for tree 1, switch 0, port 2
[    4.793180] ksz-switch spi0.1 lan6 (uninitialized): validation of internal with support 00000000,00000000,00006280 and advertisement 00000000,00000000,00000280 failed: -EINVAL
[    4.793334] ksz-switch spi0.1 lan6 (uninitialized): failed to connect to PHY: -EINVAL
[    4.793340] ksz-switch spi0.1 lan6 (uninitialized): error -22 setting up PHY for tree 1, switch 0, port 3
[    4.795057] ksz-switch spi0.1 lan5 (uninitialized): validation of internal with support 00000000,00000000,00006280 and advertisement 00000000,00000000,00000280 failed: -EINVAL
[    4.795313] ksz-switch spi0.1 lan5 (uninitialized): failed to connect to PHY: -EINVAL
[    4.795321] ksz-switch spi0.1 lan5 (uninitialized): error -22 setting up PHY for tree 1, switch 0, port 6
[    4.795663] ksz-switch spi0.1 lan3 (uninitialized): validation of internal with support 00000000,00000000,00006280 and advertisement 00000000,00000000,00000280 failed: -EINVAL
[    4.795822] ksz-switch spi0.1 lan3 (uninitialized): failed to connect to PHY: -EINVAL
[    4.795828] ksz-switch spi0.1 lan3 (uninitialized): error -22 setting up PHY for tree 1, switch 0, port 7
[   10.462322] ksz-switch spi0.1 lan7: configuring for fixed/rgmii-rxid link mode
[   10.462711] ksz-switch spi0.1 lan7: Link is Up - 100Mbps/Full - flow control off

Hi Daolin Qiu,

on top of the changes provided from the link you have provided, i have made changes in the slave.c files under /net/dsa,

below are the changes

#if 0
    ret = phylink_of_phy_connect(dp->pl, port_dn, phy_flags);
    if (ret == -ENODEV && ds->slave_mii_bus) {
        /* We could not connect to a designated PHY or SFP, so try to
         * use the switch internal MDIO bus instead
         */
        ret = dsa_slave_phy_connect(slave_dev, dp->index, phy_flags);
    }
    if (ret) {
        netdev_err(slave_dev, "failed to connect to PHY: %pe\n",
               ERR_PTR(ret));
        dsa_port_phylink_destroy(dp);
    }
#endif

This section is commented out, now under ip link show, we get this,

1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
    link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
2: eth0: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc mq state DOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:e6:eb:5f brd ff:ff:ff:ff:ff:ff
3: eth1: <BROADCAST,MULTICAST,DYNAMIC,UP,LOWER_UP> mtu 1502 qdisc mq state UP mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:f6:eb:5f brd ff:ff:ff:ff:ff:ff
4: lan1@eth1: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:f6:eb:5f brd ff:ff:ff:ff:ff:ff
5: lan2@eth1: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:f6:eb:5f brd ff:ff:ff:ff:ff:ff
6: lan4@eth1: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:f6:eb:5f brd ff:ff:ff:ff:ff:ff
7: lan6@eth1: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:f6:eb:5f brd ff:ff:ff:ff:ff:ff
8: lan7@eth1: <BROADCAST,MULTICAST,DYNAMIC,UP,LOWER_UP> mtu 1500 qdisc noqueue state UP mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:f6:eb:5f brd ff:ff:ff:ff:ff:ff
9: lan5@eth1: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:f6:eb:5f brd ff:ff:ff:ff:ff:ff
10: lan3@eth1: <NO-CARRIER,BROADCAST,MULTICAST,DYNAMIC,UP> mtu 1500 qdisc noqueue state LOWERLAYERDOWN mode DEFAULT group default qlen 1000
    link/ether 00:14:2d:f6:eb:5f brd ff:ff:ff:ff:ff:ff

But still ping does not work,

below is the device tree,

/* Verdin ETHs */
&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
	status = "okay";
};

/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
	status = "okay";
#if 0
	cpsw3g_phy1: ethernet-phy@7 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <7>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
		micrel,led-mode = <0>;
	};
#endif
};

/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
	status = "okay";
};

/* Verdin ETH_2_RGMII */
&cpsw_port2 {
	//phy-handle = <&cpsw3g_phy1>;
	phy-mode = "rgmii-rxid";
	status = "okay";
	
	fixed-link {
		speed = <100>;
		full-duplex;
	};
};

let me know if any chnages are needed

Hi Naveenkumar, 

Since the patch was made by the other customer, it will be hard for me to comment on what changes are needed. Additionally, the DSA driver is not a TI specific driver so our support on making modifications on the DSA driver is limited. I proposed looking at that patch made by the other customer as a starting point for you in case helps you but I won't be able to provide specific steps on how to fix any issues you may see as result of trying the patch out.

One thing to double check is if you made the same set of changes as described in the patch? Specifically the "master = of_find_net_device_by_name("eth1");" part?

## DSA Core Patch

diff --git a/include/linux/of_net.h b/include/linux/of_net.h
index 71bbfcf3adcd..ba84ffefaddc 100644
--- a/include/linux/of_net.h
+++ b/include/linux/of_net.h
@@ -15,6 +15,9 @@ struct net_device;
 extern int of_get_phy_mode(struct device_node *np, phy_interface_t *interface);
 extern const void *of_get_mac_address(struct device_node *np);
 extern struct net_device *of_find_net_device_by_node(struct device_node *np);
+/* start duagon addition */
+extern struct net_device *of_find_net_device_by_name(const char *name);
+/* end duagon addition */
 #else
 static inline int of_get_phy_mode(struct device_node *np,
                   phy_interface_t *interface)
diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c
index 99303897b7bb..ae4b3eed13bf 100644
--- a/net/core/net-sysfs.c
+++ b/net/core/net-sysfs.c
@@ -1942,6 +1942,20 @@ struct net_device *of_find_net_device_by_node(struct device_node *np)
     return to_net_dev(dev);
 }
 EXPORT_SYMBOL(of_find_net_device_by_node);
+
+/* start duagon addition */
+struct net_device *of_find_net_device_by_name(const char* name)
+{
+    struct device *dev;
+
+    dev = class_find_device_by_name(&net_class, name);
+    if (!dev)
+        return NULL;
+
+    return to_net_dev(dev);
+}
+EXPORT_SYMBOL(of_find_net_device_by_name);
+/* end duagon addition */
 #endif
 
 /* Delete sysfs entries but hold kobject reference until after all
diff --git a/net/dsa/dsa2.c b/net/dsa/dsa2.c
index 71c8ef7d4087..91be6ce3a870 100644
--- a/net/dsa/dsa2.c
+++ b/net/dsa/dsa2.c
@@ -765,7 +765,8 @@ static int dsa_port_parse_of(struct dsa_port *dp, struct device_node *dn)
     if (ethernet) {
         struct net_device *master;
 
-        master = of_find_net_device_by_node(ethernet);
+        /* duagon patch */
+        master = of_find_net_device_by_name("eth1");
         if (!master)
             return -EPROBE_DEFER;

-Daolin

Hi Daolin Qiu,

i Have made the changes but yet no improvement, still the issue persists. still trying to get the communication up.

one question can i use fixed link on all lan ports from lan9374?

any other inputs regarding the driver change is welcome.

Hi Naveenkumar,

naveenkumar Muthusamy said:

one question can i use fixed link on all lan ports from lan9374?

From my understanding, only one lan port is connected to the CPSW port2 (from the latest full DTS file you shared, this was lan "port@5"). While I cannot comment on what DTS changes you need for the switch you are using (not a TI part), my guess is that it probably won't fix/improve the issue you are seeing since the other lan ports aren't directly connected to the CPSW. 

port@5 {
    reg = <5>;
    phy-mode = "rgmii-rxid";
    tx-internal-delay-ps = <2000>;
    rx-internal-delay-ps = <2000>;
    ethernet = <&cpsw_port2>;
    fixed-link {
        speed = <100>;
        full-duplex;
    };
};

For CPSW port1, do you have that connected to an Ethernet PHY that is completely separate from the lan9374? What is making me concerned is the lan "port@4" configuration you have in your DTS. Why does it have a fixed-link node?

port@4 {
    reg = <4>;
    label = "lan7";
    phy-mode = "rgmii-rxid";
    tx-internal-delay-ps = <2000>;
    rx-internal-delay-ps = <2000>;
    fixed-link {
        speed = <100>;
        full-duplex;
    };
};

For the &cpsw_port2 node, instead of phy-mode = "rgmii-rxid", could you try phy-mode = "rgmii-id"? 

/* Verdin ETH_2_RGMII */
&cpsw_port2 {

	status = "okay";
	phy-mode = "rgmii-id";
	fixed-link {
		speed = <100>;
		full-duplex;
	};
};

-Daolin

Hi Daolin Qiu,

i have tried the Rgmii-id as well, but it does not seem to work and the Port 4 and port5 decide where the rgmii port is connected to LAN9374.

LAN9374 has two ethernet ports RGMII1 and RGMII2 and depends on this , we have to use the ethernet property.

in my systesm RGMII from am62 is connected to the RGMII1, so i have to use ethernet property in  port5.

Hi Naveenkumar,

Just to be clear, there is no RGMII connection to the AM62x through port4 (RGMII2) correct? Only port5 has a connection to AM62x (RGMII1)?

What is connected on port4?

-Daolin

Hi Daolin Qiu,

we have connected to RGMII1 of the LAN9374 using the am62x RGMII2. As per the datasheet of LAN9374 port5 should be used if we use RGMII1 of LAN9374. In port4 nothing is connected.

we need your help in connecting the LAN9374 to the eth1. as i said earlier if i use ethernet port as cpsw_port2, i get deferred probing. and if i use cpsw3g, i get device registered but all ports are connected to the eth0.

so in this case, what changes are needed. i tried the patch file you have shared, but still i cant get any ping going out.

i measured the RX_CLK and tx_CLK which is around 125MHZ.

Hi Naveenkumar,

naveenkumar Muthusamy said:

we need your help in connecting the LAN9374 to the eth1. as i said earlier if i use ethernet port as cpsw_port2, i get deferred probing. and if i use cpsw3g, i get device registered but all ports are connected to the eth0.

so in this case, what changes are needed. i tried the patch file you have shared, but still i cant get any ping going out.

There are two things we need to look into:

1. As you mentioned, using cpsw_port2 will cause issues (seems to be related to the switch not recognizing the Ethernet controller/"master" in DSA terminology based on another customer's issue -  https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1500268/am625-ethernet-switch-connection-to-rgmii-2.

We (you and I) need to understand if cpsw3g actually supposed to be used here or if it simply makes it seem like the right option because it gets rid of the deferred probing issue, but later introduces the fact that the switch is not attached to the 2nd CPSW port. I think this happening seems to make sense because the cpsw3g would probably assume the 1st cpsw port is what the switch should automatically be attached to, especially since using cpsw3g has no way of specifying which port should be used.

I know eventually you will need cpsw port 1 to be used, but can you try disabling cpsw port 1 (eth0) in the device tree and see what happens? 

2. If indeed the cpsw3g should be used, there may be some changes needed related to enabling VLAN aware mode in an external switch. I need to check with a colleague about the details of these changes and if these changes were ever integrated on the latest TI SDK.

The colleague will be out of office for the rest of this week so likely I won't be able to get back to you until next week Tuesday at the earliest (Monday is a holiday in the US). 

naveenkumar Muthusamy said:

/# uname -r
6.1.80-6.7.0-devel+git.603f75dc931d

SDK version we are using is 6.1.80-6.7.0-devel+git.603f75dc931d.

In the meantime, are you able to test on a newer SDK version- either 10.1 or 11.0 (Kernel version 6.6 or 6.12)?

-Daolin

HI Daolin Qiu,

Daolin Qiu said:

In the meantime, are you able to test on a newer SDK version- either 10.1 or 11.0 (Kernel version 6.6 or 6.12)?

I have tested with the latest kernel versions as well, still i am getting the same issue. with CPSw3g i don't get deferred probing, but with cpsw_port2, i get deferred probing

Hi Naveenkumar, 

Daolin Qiu said:

I know eventually you will need cpsw port 1 to be used, but can you try disabling cpsw port 1 (eth0) in the device tree and see what happens? 

Have you also tried this?

-Daolin

Daolin Qiu said:

I know eventually you will need cpsw port 1 to be used, but can you try disabling cpsw port 1 (eth0) in the device tree and see what happens? 

we eventually need cpsw_port2. we have also tried disabling cpsw_port1, but still i see the same issue.

Hi Naveenkumar, 

Can you share your decompiled DTS (i.e. decompiled from DTB)?

-Daolin 

Hi Daolin Qiu,

i have attached file with this

/dts-v1/;

/ {
	model = "Toradex Verdin AM62 on Verdin Development Board";
	compatible = "toradex,verdin-am62-nonwifi-dev\0toradex,verdin-am62-nonwifi\0toradex,verdin-am62\0ti,am625";
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;

	chosen {
		stdout-path = "serial2:115200n8";
	};

	firmware {

		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci {
			compatible = "arm,psci-1.0";
			method = "smc";
			phandle = <0x7b>;
		};
	};

	timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
		phandle = <0x7c>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <0x01 0x07 0x04>;
		phandle = <0x7d>;
	};

	bus@f0000 {
		compatible = "simple-bus";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges = <0x00 0xf0000 0x00 0xf0000 0x00 0x30000 0x00 0x420000 0x00 0x420000 0x00 0x1000 0x00 0x600000 0x00 0x600000 0x00 0x1100 0x00 0x703000 0x00 0x703000 0x00 0x200 0x00 0x70c000 0x00 0x70c000 0x00 0x200 0x00 0xa40000 0x00 0xa40000 0x00 0x800 0x00 0x1000000 0x00 0x1000000 0x00 0x1b28400 0x00 0x8000000 0x00 0x8000000 0x00 0x200000 0x00 0xe000000 0x00 0xe000000 0x00 0x1d20000 0x00 0xfd00000 0x00 0xfd00000 0x00 0x20000 0x00 0x20000000 0x00 0x20000000 0x00 0xa008000 0x00 0x30040000 0x00 0x30040000 0x00 0x80000 0x00 0x30101000 0x00 0x30101000 0x00 0x10100 0x00 0x30200000 0x00 0x30200000 0x00 0x10000 0x00 0x30300000 0x00 0x30300000 0x00 0x1000 0x00 0x31000000 0x00 0x31000000 0x00 0x50000 0x00 0x31100000 0x00 0x31100000 0x00 0x50000 0x00 0x40900000 0x00 0x40900000 0x00 0x30000 0x00 0x43600000 0x00 0x43600000 0x00 0x10000 0x00 0x44043000 0x00 0x44043000 0x00 0xfe0 0x00 0x44860000 0x00 0x44860000 0x00 0x40000 0x00 0x48000000 0x00 0x48000000 0x00 0x6400000 0x00 0x60000000 0x00 0x60000000 0x00 0x8000000 0x00 0x70000000 0x00 0x70000000 0x00 0x10000 0x01 0x00 0x01 0x00 0x00 0x310000 0x05 0x00 0x05 0x00 0x01 0x00 0x00 0x3b000000 0x00 0x3b000000 0x00 0x400 0x00 0x50000000 0x00 0x50000000 0x00 0x8000000 0x00 0x4000000 0x00 0x4000000 0x00 0x1ff1400 0x00 0xb00000 0x00 0xb00000 0x00 0x2400 0x00 0x2b000000 0x00 0x2b000000 0x00 0x300400 0x00 0x43000000 0x00 0x43000000 0x00 0x20000 0x00 0x78000000 0x00 0x78000000 0x00 0x8000 0x00 0x78100000 0x00 0x78100000 0x00 0x8000>;
		phandle = <0x7e>;

		bus@4000000 {
			compatible = "simple-bus";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges = <0x00 0x4000000 0x00 0x4000000 0x00 0x1ff1400>;
			phandle = <0x7f>;

			pinctrl@4084000 {
				compatible = "pinctrl-single";
				reg = <0x00 0x4084000 0x00 0x88>;
				#pinctrl-cells = <0x01>;
				pinctrl-single,register-width = <0x20>;
				pinctrl-single,function-mask = <0xffffffff>;
				phandle = <0x80>;

				mcu-gpio0-0-pins-default {
					pinctrl-single,pins = <0x00 0x50007>;
					phandle = <0x81>;
				};

				mcu-gpio0-1-pins-default {
					pinctrl-single,pins = <0x04 0x50007>;
					phandle = <0x07>;
				};

				mcu-gpio0-2-pins-default {
					pinctrl-single,pins = <0x08 0x50007>;
					phandle = <0x08>;
				};

				mcu-gpio0-3-pins-default {
					pinctrl-single,pins = <0x0c 0x50007>;
					phandle = <0x09>;
				};

				mcu-gpio0-4-pins-default {
					pinctrl-single,pins = <0x10 0x50007>;
					phandle = <0x0a>;
				};

				mcu-gpio-5-default {
					pinctrl-single,pins = <0x14 0x50007>;
					phandle = <0x0b>;
				};

				mcu-gpio-6-default {
					pinctrl-single,pins = <0x18 0x50007>;
					phandle = <0x0c>;
				};

				mcu-gpio-7-default {
					pinctrl-single,pins = <0x1c 0x50007>;
					phandle = <0x0d>;
				};

				mcu-gpio-8-default {
					pinctrl-single,pins = <0x20 0x50007>;
					phandle = <0x0e>;
				};

				mcu-gpio-11-default {
					pinctrl-single,pins = <0x2c 0x50007>;
					phandle = <0x0f>;
				};

				mcu-gpio-12-default {
					pinctrl-single,pins = <0x30 0x50007>;
					phandle = <0x10>;
				};

				mcu-gpio0-13-pins-default {
					pinctrl-single,pins = <0x34 0x50007>;
					phandle = <0x11>;
				};

				mcu-gpio0-14-pins-default {
					pinctrl-single,pins = <0x38 0x50007>;
					phandle = <0x12>;
				};

				mcu-gpio0-15-pins-default {
					pinctrl-single,pins = <0x3c 0x50007>;
					phandle = <0x82>;
				};

				mcu-gpio0-16-pins-default {
					pinctrl-single,pins = <0x40 0x50007>;
					phandle = <0x13>;
				};

				mcu-gpio-23-default {
					pinctrl-single,pins = <0x84 0x50007>;
					phandle = <0x14>;
				};

				wkup-uart0-pins-default {
					pinctrl-single,pins = <0x24 0x60000 0x28 0x10000>;
					phandle = <0x16>;
				};

				mcu-i2c0-pins-default {
					pinctrl-single,pins = <0x44 0x60000 0x48 0x60000>;
					phandle = <0x04>;
				};
			};

			timer@4800000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x4800000 0x00 0x400>;
				clocks = <0x02 0x23 0x02>;
				clock-names = "fck";
				power-domains = <0x03 0x23 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x83>;
			};

			timer@4810000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x4810000 0x00 0x400>;
				clocks = <0x02 0x30 0x02>;
				clock-names = "fck";
				power-domains = <0x03 0x30 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x84>;
			};

			timer@4820000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x4820000 0x00 0x400>;
				clocks = <0x02 0x31 0x02>;
				clock-names = "fck";
				power-domains = <0x03 0x31 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x85>;
			};

			timer@4830000 {
				compatible = "ti,am654-timer";
				reg = <0x00 0x4830000 0x00 0x400>;
				clocks = <0x02 0x32 0x02>;
				clock-names = "fck";
				power-domains = <0x03 0x32 0x01>;
				ti,timer-pwm;
				status = "reserved";
				phandle = <0x86>;
			};

			esm@4100000 {
				compatible = "ti,j721e-esm";
				reg = <0x00 0x4100000 0x00 0x1000>;
				ti,esm-pins = <0x00 0x01 0x02 0x55>;
				phandle = <0x87>;
			};

			serial@4a00000 {
				compatible = "ti,am64-uart\0ti,am654-uart";
				reg = <0x00 0x4a00000 0x00 0x100>;
				interrupts = <0x00 0xb9 0x04>;
				power-domains = <0x03 0x95 0x01>;
				clocks = <0x02 0x95 0x00>;
				clock-names = "fclk";
				status = "disabled";
				phandle = <0x1d>;
			};

			i2c@4900000 {
				compatible = "ti,am64-i2c\0ti,omap4-i2c";
				reg = <0x00 0x4900000 0x00 0x100>;
				interrupts = <0x00 0x6b 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				power-domains = <0x03 0x6a 0x01>;
				clocks = <0x02 0x6a 0x02>;
				clock-names = "fck";
				status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <0x04>;
				clock-frequency = <0x186a0>;
				phandle = <0x88>;

				hwmon@40 {
					compatible = "ti,ina260";
					reg = <0x40>;
				};

				hwmon@41 {
					compatible = "ti,ina260";
					reg = <0x41>;
				};

				hwmon@42 {
					compatible = "ti,ina260";
					reg = <0x42>;
				};

				hwmon@43 {
					compatible = "ti,ina260";
					reg = <0x43>;
				};

				hwmon@44 {
					compatible = "ti,ina260";
					reg = <0x44>;
				};

				hwmon@45 {
					compatible = "ti,ina260";
					reg = <0x45>;
				};

				hwmon@46 {
					compatible = "ti,ina260";
					reg = <0x46>;
				};

				hwmon@47 {
					compatible = "ti,ina260";
					reg = <0x47>;
				};

				hwmon@48 {
					compatible = "ti,ina260";
					reg = <0x4b>;
				};

				lm73@49 {
					compatible = "ti,lm73";
					reg = <0x49>;
				};

				lm73@50 {
					compatible = "ti,lm73";
					reg = <0x4a>;
				};
			};

			spi@4b00000 {
				compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
				reg = <0x00 0x4b00000 0x00 0x400>;
				interrupts = <0x00 0xb0 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				power-domains = <0x03 0x93 0x01>;
				clocks = <0x02 0x93 0x00>;
				status = "disabled";
				phandle = <0x89>;
			};

			spi@4b10000 {
				compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
				reg = <0x00 0x4b10000 0x00 0x400>;
				interrupts = <0x00 0xb1 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				power-domains = <0x03 0x94 0x01>;
				clocks = <0x02 0x94 0x00>;
				status = "disabled";
				phandle = <0x8a>;
			};

			interrupt-controller@4210000 {
				compatible = "ti,sci-intr";
				reg = <0x00 0x4210000 0x00 0x200>;
				ti,intr-trigger-type = <0x01>;
				interrupt-controller;
				interrupt-parent = <0x01>;
				#interrupt-cells = <0x01>;
				ti,sci = <0x05>;
				ti,sci-dev-id = <0x05>;
				ti,interrupt-ranges = <0x00 0x68 0x04>;
				phandle = <0x06>;
			};

			gpio@4201000 {
				compatible = "ti,am64-gpio\0ti,keystone-gpio";
				reg = <0x00 0x4201000 0x00 0x100>;
				gpio-controller;
				#gpio-cells = <0x02>;
				interrupt-parent = <0x06>;
				interrupts = <0x1e 0x1f>;
				interrupt-controller;
				#interrupt-cells = <0x02>;
				ti,ngpio = <0x18>;
				ti,davinci-gpio-unbanked = <0x00>;
				power-domains = <0x03 0x4f 0x01>;
				clocks = <0x02 0x4f 0x00>;
				clock-names = "gpio";
				gpio-line-names = "SODIMM_244 - DO_1V8_NCS_FRAM\0SODIMM_206 - DI_1V8_SW2\0SODIMM_208 - DI_1V8_SW3\0SODIMM_210 -DI_1V8_SW4\0SODIMM_212 - DI_1V8_SW5\0\0\0\0\0\0SODIMM_143\0\0\0SODIMM_26\0\0\0\0\0\0\0\0\0\0SODIMM_91 - DI_1V8_SW1";
				pinctrl-names = "default";
				pinctrl-0 = <0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14>;
				phandle = <0x8b>;
			};

			watchdog@4880000 {
				compatible = "ti,j7-rti-wdt";
				reg = <0x00 0x4880000 0x00 0x100>;
				clocks = <0x02 0x83 0x00>;
				power-domains = <0x03 0x83 0x01>;
				assigned-clocks = <0x02 0x83 0x00>;
				assigned-clock-parents = <0x02 0x83 0x02>;
				status = "reserved";
				phandle = <0x8c>;
			};

			m4fss@5000000 {
				compatible = "ti,am64-m4fss";
				reg = <0x00 0x5000000 0x00 0x30000 0x00 0x5040000 0x00 0x10000>;
				reg-names = "iram\0dram";
				ti,sci = <0x05>;
				ti,sci-dev-id = <0x09>;
				ti,sci-proc-ids = <0x18 0xff>;
				resets = <0x15 0x09 0x01>;
				firmware-name = "am62-mcu-m4f0_0-fw";
				wakeup-source;
				phandle = <0x8d>;
			};

			can@4e08000 {
				compatible = "bosch,m_can";
				reg = <0x00 0x4e08000 0x00 0x200 0x00 0x4e00000 0x00 0x8000>;
				reg-names = "m_can\0message_ram";
				power-domains = <0x03 0xbc 0x01>;
				clocks = <0x02 0xbc 0x06 0x02 0xbc 0x01>;
				clock-names = "hclk\0cclk";
				bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
				wakeup-source;
				status = "disabled";
				phandle = <0x1b>;
			};

			can@4e18000 {
				compatible = "bosch,m_can";
				reg = <0x00 0x4e18000 0x00 0x200 0x00 0x4e10000 0x00 0x8000>;
				reg-names = "m_can\0message_ram";
				power-domains = <0x03 0xbd 0x01>;
				clocks = <0x02 0xbd 0x06 0x02 0xbd 0x01>;
				clock-names = "hclk\0cclk";
				bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
				wakeup-source;
				status = "disabled";
				phandle = <0x1c>;
			};
		};

		bus@b00000 {
			compatible = "simple-bus";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges = <0x00 0xb00000 0x00 0xb00000 0x00 0x2400 0x00 0x2b000000 0x00 0x2b000000 0x00 0x300400 0x00 0x43000000 0x00 0x43000000 0x00 0x20000 0x00 0x78000000 0x00 0x78000000 0x00 0x8000 0x00 0x78100000 0x00 0x78100000 0x00 0x8000>;
			phandle = <0x8e>;

			syscon@43000000 {
				compatible = "syscon\0simple-mfd";
				reg = <0x00 0x43000000 0x00 0x20000>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x43000000 0x20000>;
				phandle = <0x5d>;

				chipid@14 {
					compatible = "ti,am654-chipid";
					reg = <0x14 0x04>;
					phandle = <0x8f>;
				};

				syscon@4008 {
					compatible = "syscon";
					reg = <0x4008 0x04>;
					phandle = <0x58>;
				};

				syscon@4018 {
					compatible = "syscon";
					reg = <0x4018 0x04>;
					phandle = <0x59>;
				};
			};

			target-module@2b300050 {
				compatible = "ti,sysc-omap2\0ti,sysc";
				reg = <0x00 0x2b300050 0x00 0x04 0x00 0x2b300054 0x00 0x04 0x00 0x2b300058 0x00 0x04>;
				reg-names = "rev\0sysc\0syss";
				ti,sysc-mask = <0x07>;
				ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
				ti,syss-mask = <0x01>;
				ti,no-reset-on-init;
				power-domains = <0x03 0x72 0x01>;
				clocks = <0x02 0x72 0x00>;
				clock-names = "fck";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x2b300000 0x100000>;

				serial@0 {
					compatible = "ti,am64-uart\0ti,am654-uart";
					reg = <0x00 0x100>;
					interrupts = <0x00 0xba 0x04>;
					status = "okay";
					pinctrl-names = "default";
					pinctrl-0 = <0x16>;
					phandle = <0x1e>;
				};
			};

			i2c@2b200000 {
				compatible = "ti,am64-i2c\0ti,omap4-i2c";
				reg = <0x00 0x2b200000 0x00 0x100>;
				interrupts = <0x00 0xa5 0x04>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				power-domains = <0x03 0x6b 0x01>;
				clocks = <0x02 0x6b 0x04>;
				clock-names = "fck";
				status = "disabled";
				phandle = <0x90>;
			};

			rtc@2b1f0000 {
				compatible = "ti,am62-rtc";
				reg = <0x00 0x2b1f0000 0x00 0x100>;
				interrupts = <0x00 0x64 0x04>;
				clocks = <0x02 0x75 0x06 0x02 0x75 0x00>;
				clock-names = "vbus\0osc32k";
				power-domains = <0x03 0x75 0x01>;
				wakeup-source;
				phandle = <0x91>;
			};

			watchdog@2b000000 {
				compatible = "ti,j7-rti-wdt";
				reg = <0x00 0x2b000000 0x00 0x100>;
				clocks = <0x02 0x84 0x00>;
				power-domains = <0x03 0x84 0x01>;
				assigned-clocks = <0x02 0x84 0x00>;
				assigned-clock-parents = <0x02 0x84 0x02>;
				status = "reserved";
				phandle = <0x92>;
			};

			r5fss@78000000 {
				compatible = "ti,am62-r5fss";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x78000000 0x00 0x78000000 0x8000 0x78100000 0x00 0x78100000 0x8000>;
				power-domains = <0x03 0x77 0x01>;
				phandle = <0x93>;

				r5f@78000000 {
					compatible = "ti,am62-r5f";
					reg = <0x78000000 0x8000 0x78100000 0x8000>;
					reg-names = "atcm\0btcm";
					ti,sci = <0x05>;
					ti,sci-dev-id = <0x79>;
					ti,sci-proc-ids = <0x01 0xff>;
					resets = <0x15 0x79 0x01>;
					firmware-name = "ti-sysfw/ti-fs-stub-firmware-am62x-gp-signed.bin";
					ti,atcm-enable = <0x01>;
					ti,btcm-enable = <0x01>;
					ti,loczrama = <0x01>;
					phandle = <0x94>;
				};
			};

			temperature-sensor@b00000 {
				compatible = "ti,j7200-vtm";
				reg = <0x00 0xb00000 0x00 0x400 0x00 0xb01000 0x00 0x400>;
				power-domains = <0x03 0x5f 0x01>;
				#thermal-sensor-cells = <0x01>;
				phandle = <0x6f>;
			};
		};

		sram@70000000 {
			compatible = "mmio-sram";
			reg = <0x00 0x70000000 0x00 0x10000>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x00 0x70000000 0x10000>;
			phandle = <0x95>;
		};

		interrupt-controller@1800000 {
			compatible = "arm,gic-v3";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges;
			#interrupt-cells = <0x03>;
			interrupt-controller;
			reg = <0x00 0x1800000 0x00 0x10000 0x00 0x1880000 0x00 0xc0000 0x00 0x1880000 0x00 0xc0000 0x01 0x00 0x00 0x2000 0x01 0x10000 0x00 0x1000 0x01 0x20000 0x00 0x2000>;
			interrupts = <0x01 0x09 0x04>;
			phandle = <0x01>;

			msi-controller@1820000 {
				compatible = "arm,gic-v3-its";
				reg = <0x00 0x1820000 0x00 0x10000>;
				socionext,synquacer-pre-its = <0x1000000 0x400000>;
				msi-controller;
				#msi-cells = <0x01>;
				phandle = <0x96>;
			};
		};

		syscon@100000 {
			compatible = "syscon\0simple-mfd";
			reg = <0x00 0x100000 0x00 0x20000>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x00 0x100000 0x20000>;
			phandle = <0x97>;

			phy@4044 {
				compatible = "ti,am654-phy-gmii-sel";
				reg = <0x4044 0x08>;
				#phy-cells = <0x01>;
				phandle = <0x5c>;
			};

			clock@4130 {
				compatible = "ti,am62-epwm-tbclk";
				reg = <0x4130 0x04>;
				#clock-cells = <0x01>;
				phandle = <0x69>;
			};

			dss-oldi-io-ctrl@8600 {
				compatible = "syscon";
				reg = <0x8600 0x200>;
				phandle = <0x64>;
			};

			clock@82e0 {
				compatible = "ti,am62-audio-refclk";
				reg = <0x82e0 0x04>;
				clocks = <0x02 0x9d 0x00>;
				assigned-clocks = <0x02 0x9d 0x00>;
				assigned-clock-parents = <0x02 0x9d 0x08>;
				#clock-cells = <0x00>;
				phandle = <0x98>;
			};

			clock@82e4 {
				compatible = "ti,am62-audio-refclk";
				reg = <0x82e4 0x04>;
				clocks = <0x02 0x9d 0x0a>;
				assigned-clocks = <0x02 0x9d 0x0a>;
				assigned-clock-parents = <0x02 0x9d 0x12>;
				#clock-cells = <0x00>;
				phandle = <0x99>;
			};
		};

		bus@48000000 {
			compatible = "simple-mfd";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			dma-ranges;
			ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x6400000>;
			ti,sci-dev-id = <0x19>;
			phandle = <0x9a>;

			mailbox@4d000000 {
				compatible = "ti,am654-secure-proxy";
				#mbox-cells = <0x01>;
				reg-names = "target_data\0rt\0scfg";
				reg = <0x00 0x4d000000 0x00 0x80000 0x00 0x4a600000 0x00 0x80000 0x00 0x4a400000 0x00 0x80000>;
				interrupt-names = "rx_012";
				interrupts = <0x00 0x22 0x04>;
				phandle = <0x1a>;
			};

			interrupt-controller@48000000 {
				compatible = "ti,sci-inta";
				reg = <0x00 0x48000000 0x00 0x100000>;
				#interrupt-cells = <0x00>;
				interrupt-controller;
				interrupt-parent = <0x01>;
				msi-controller;
				ti,sci = <0x05>;
				ti,sci-dev-id = <0x1c>;
				ti,interrupt-ranges = <0x04 0x44 0x24>;
				ti,unmapped-event-sources = <0x17 0x18>;
				phandle = <0x19>;
			};

			dma-controller@485c0100 {
				compatible = "ti,am64-dmss-bcdma";
				reg = <0x00 0x485c0100 0x00 0x100 0x00 0x4c000000 0x00 0x20000 0x00 0x4a820000 0x00 0x20000 0x00 0x4aa40000 0x00 0x20000 0x00 0x4bc00000 0x00 0x100000>;
				reg-names = "gcfg\0bchanrt\0rchanrt\0tchanrt\0ringrt";
				msi-parent = <0x19>;
				#dma-cells = <0x03>;
				ti,sci = <0x05>;
				ti,sci-dev-id = <0x1a>;
				ti,sci-rm-range-bchan = <0x20>;
				ti,sci-rm-range-rchan = <0x21>;
				ti,sci-rm-range-tchan = <0x22>;
				phandle = <0x17>;
			};

			dma-controller@485c0000 {
				compatible = "ti,am64-dmss-pktdma";
				reg = <0x00 0x485c0000 0x00 0x100 0x00 0x4a800000 0x00 0x20000 0x00 0x4aa00000 0x00 0x40000 0x00 0x4b800000 0x00 0x400000>;
				reg-names = "gcfg\0rchanrt\0tchanrt\0ringrt";
				msi-parent = <0x19>;
				#dma-cells = <0x02>;
				ti,sci = <0x05>;
				ti,sci-dev-id = <0x1e>;
				ti,sci-rm-range-tchan = <0x23 0x24 0x25 0x26>;
				ti,sci-rm-range-tflow = <0x10 0x11 0x12 0x13>;
				ti,sci-rm-range-rchan = <0x29 0x2b 0x2d 0x2f 0x31 0x33>;
				ti,sci-rm-range-rflow = <0x2a 0x2c 0x2e 0x32>;
				phandle = <0x18>;
			};
		};

		system-controller@44043000 {
			compatible = "ti,k2g-sci";
			ti,host-id = <0x0c>;
			mbox-names = "rx\0tx";
			mboxes = <0x1a 0x0c 0x1a 0x0d>;
			reg-names = "debug_messages";
			reg = <0x00 0x44043000 0x00 0xfe0>;
			ti,partial-io-wakeup-sources = <0x1b 0x1c 0x1d 0x1e>;
			phandle = <0x05>;

			power-controller {
				compatible = "ti,sci-pm-domain";
				#power-domain-cells = <0x02>;
				phandle = <0x03>;
			};

			clock-controller {
				compatible = "ti,k2g-sci-clk";
				#clock-cells = <0x02>;
				phandle = <0x02>;
			};

			reset-controller {
				compatible = "ti,sci-reset";
				#reset-cells = <0x02>;
				phandle = <0x15>;
			};
		};

		crypto@40900000 {
			compatible = "ti,am62-sa3ul";
			reg = <0x00 0x40900000 0x00 0x1200>;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
			dmas = <0x18 0xf501 0x00 0x18 0x7506 0x00 0x18 0x7507 0x00>;
			dma-names = "tx\0rx1\0rx2";
			phandle = <0x9b>;
		};

		mcrc@30300000 {
			compatible = "ti,mcrc";
			reg = <0x00 0x30300000 0x00 0x1000>;
			clocks = <0x02 0x74 0x00>;
			power-domains = <0x03 0x74 0x01>;
			phandle = <0x9c>;
		};

		mailbox@43600000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <0x01>;
			reg-names = "target_data\0rt\0scfg";
			reg = <0x00 0x43600000 0x00 0x10000 0x00 0x44880000 0x00 0x20000 0x00 0x44860000 0x00 0x20000>;
			status = "disabled";
			phandle = <0x9d>;
		};

		pinctrl@f4000 {
			compatible = "ti,am6-padconf";
			reg = <0x00 0xf4000 0x00 0x2ac>;
			#pinctrl-cells = <0x01>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0xffffffff>;
			interrupts = <0x00 0x62 0x04>;
			interrupt-controller;
			#interrupt-cells = <0x01>;
			phandle = <0x9e>;

			main-gpio0-0-pins-default {
				pinctrl-single,pins = <0x00 0x50007>;
				phandle = <0x3c>;
			};

			main-gpio0-3-pins-default {
				pinctrl-single,pins = <0x0c 0x50007>;
				phandle = <0x3e>;
			};

			main-gpio0-4-pins-default {
				pinctrl-single,pins = <0x10 0x50007>;
				phandle = <0x3f>;
			};

			main-gpio0-5-pins-default {
				pinctrl-single,pins = <0x14 0x50007>;
				phandle = <0x40>;
			};

			main-gpio0-6-pins-default {
				pinctrl-single,pins = <0x18 0x50007>;
				phandle = <0x41>;
			};

			main-gpio0-12-pins-default {
				pinctrl-single,pins = <0x30 0x50007>;
				phandle = <0x43>;
			};

			main-gpio0-11-pins-default {
				pinctrl-single,pins = <0x2c 0x50007>;
				phandle = <0x42>;
			};

			main-gpio0-18-pins-default {
				pinctrl-single,pins = <0x48 0x50007>;
				phandle = <0x44>;
			};

			main-gpio0-70-pins-default {
				pinctrl-single,pins = <0x120 0x50007>;
				phandle = <0x45>;
			};

			main-gpio0-68-pins-default {
				pinctrl-single,pins = <0x114 0x50007>;
				phandle = <0x46>;
			};

			main-gpio0-67-pins-default {
				pinctrl-single,pins = <0x110 0x50007>;
				phandle = <0x47>;
			};

			main-gpio0-66-pins-default {
				pinctrl-single,pins = <0x10c 0x50007>;
				phandle = <0x48>;
			};

			main-gpio0-65-pins-default {
				pinctrl-single,pins = <0x108 0x50007>;
				phandle = <0x49>;
			};

			main-gpio0-16-pins-default {
				pinctrl-single,pins = <0x40 0x50007>;
				phandle = <0x4a>;
			};

			main-gpio0-2-pins-default {
				pinctrl-single,pins = <0x08 0x50007>;
				phandle = <0x4b>;
			};

			main-gpio0-1-pins-default {
				pinctrl-single,pins = <0x04 0x50007>;
				phandle = <0x4c>;
			};

			main-gpio0-14-pins-default {
				pinctrl-single,pins = <0x38 0x50007>;
				phandle = <0x4d>;
			};

			main-gpio0-33-pins-default {
				pinctrl-single,pins = <0x88 0x50007>;
				phandle = <0x4f>;
			};

			main-gpio0-34-pins-default {
				pinctrl-single,pins = <0x8c 0x07>;
				phandle = <0x51>;
			};

			main-gpio0-35-pins-default {
				pinctrl-single,pins = <0x90 0x50007>;
				phandle = <0x52>;
			};

			main-gpio0-37-pins-default {
				pinctrl-single,pins = <0x98 0x50007>;
				phandle = <0x53>;
			};

			main-gpio1-12-pins-default {
				pinctrl-single,pins = <0x1a8 0x50007>;
				phandle = <0x55>;
			};

			main-gpio1-10-pins-default {
				pinctrl-single,pins = <0x1a0 0x50006>;
				phandle = <0x6a>;
			};

			main-gpio0-71-pins-default {
				pinctrl-single,pins = <0x124 0x50007>;
				phandle = <0x54>;
			};

			main-gpio1-51-pins-default {
				pinctrl-single,pins = <0x258 0x50007>;
				phandle = <0x56>;
			};

			main-gpio0-17-pins-default {
				pinctrl-single,pins = <0x44 0x50007>;
				phandle = <0x62>;
			};

			main-gpio0-20-pins-default {
				pinctrl-single,pins = <0x50 0x50007>;
				phandle = <0x27>;
			};

			main-gpio0-21-pins-default {
				pinctrl-single,pins = <0x54 0x50007>;
				phandle = <0x3d>;
			};

			main-gpio0-22-pins-default {
				pinctrl-single,pins = <0x58 0x50007>;
				phandle = <0x9f>;
			};

			main-gpio0-25-pins-default {
				pinctrl-single,pins = <0x64 0x60007>;
				phandle = <0x61>;
			};

			main-gpio0-26-pins-default {
				pinctrl-single,pins = <0x68 0x50007>;
				phandle = <0xa0>;
			};

			main-gpio0-27-pins-default {
				pinctrl-single,pins = <0x6c 0x50007>;
				phandle = <0xa1>;
			};

			main-gpio0-31-pins-default {
				pinctrl-single,pins = <0x7c 0x50007>;
				phandle = <0x4e>;
			};

			main-gpio0-32-pins-default {
				pinctrl-single,pins = <0x84 0x60007>;
				phandle = <0x50>;
			};

			main-gpio0-38-pins-default {
				pinctrl-single,pins = <0x9c 0x50007>;
				phandle = <0x63>;
			};

			main-gpio0-36-pins-default {
				pinctrl-single,pins = <0x94 0x50007>;
				phandle = <0xa2>;
			};

			main-gpio0-40-pins-default {
				pinctrl-single,pins = <0xa4 0x50007>;
				phandle = <0xa3>;
			};

			main-gpio0-41-pins-default {
				pinctrl-single,pins = <0xa8 0x50007>;
				phandle = <0xa4>;
			};

			main-gpio0-42-pins-default {
				pinctrl-single,pins = <0xac 0x50007>;
				phandle = <0xa5>;
			};

			main-i2c0-pins-default {
				pinctrl-single,pins = <0x1e0 0x50000 0x1e4 0x50000>;
				phandle = <0x26>;
			};

			main-mdio1-pins-default {
				pinctrl-single,pins = <0x160 0x10000 0x15c 0x50000>;
				phandle = <0x60>;
			};

			main-mmc0-pins-default {
				pinctrl-single,pins = <0x220 0x50000 0x218 0x50000 0x214 0x50000 0x210 0x50000 0x20c 0x50000 0x208 0x50000 0x204 0x50000 0x200 0x50000 0x1fc 0x50000 0x1f8 0x50000>;
				phandle = <0x57>;
			};

			main-rgmii1-pins-default {
				pinctrl-single,pins = <0x14c 0x50000 0x150 0x50000 0x154 0x50000 0x158 0x50000 0x148 0x50000 0x144 0x50000 0x134 0x10000 0x138 0x10000 0x13c 0x10000 0x140 0x10000 0x130 0x10000 0x12c 0x10000>;
				phandle = <0x5a>;
			};

			main-rgmii2-pins-default {
				pinctrl-single,pins = <0x184 0x50000 0x188 0x50000 0x18c 0x50000 0x190 0x50000 0x180 0x50000 0x17c 0x50000 0x16c 0x50000 0x170 0x50000 0x174 0x50000 0x178 0x50000 0x168 0x50000 0x164 0x50000>;
				phandle = <0x5b>;
			};

			main-spi1-pins-default {
				pinctrl-single,pins = <0x20 0x50001 0x24 0x50001 0x28 0x50001 0x1c 0x50001>;
				phandle = <0x39>;
			};

			main-spi2-pins-defaults {
				pinctrl-single,pins = <0x1b0 0x50001 0x194 0x50001 0x198 0x50001 0x1ac 0x50001 0x1a4 0x50001 0x19c 0x50001>;
				phandle = <0x3a>;
			};

			main-spi0-pins-default {
				pinctrl-single,pins = <0x1bc 0x50000 0x1c0 0x50000 0x1c4 0x50000 0x1b4 0x50000 0x1b8 0x50000 0x1d0 0x50001 0x1d4 0x20001>;
				phandle = <0x30>;
			};

			main-system-clkout0-pins-default {
				pinctrl-single,pins = <0x1f0 0x20005>;
				phandle = <0x5f>;
			};

			main-system-extint-pins-default {
				pinctrl-single,pins = <0x1f4 0x50000>;
				phandle = <0x2c>;
			};

			main-uart0-pins-default {
				pinctrl-single,pins = <0x1c8 0x60000 0x1cc 0x10000>;
				phandle = <0x1f>;
			};

			main-uart4-pins-default {
				pinctrl-single,pins = <0xb0 0x60003 0xb4 0x10003>;
				phandle = <0x23>;
			};

			main-uart6-pins-default {
				pinctrl-single,pins = <0x118 0x50003 0x244 0x10001>;
				phandle = <0x25>;
			};

			main-uart5-pins-default {
				pinctrl-single,pins = <0x1d8 0x50001 0x78 0x10002>;
				phandle = <0x24>;
			};

			main-uart2-pins-default {
				pinctrl-single,pins = <0x224 0x60003 0x228 0x10003>;
				phandle = <0x21>;
			};

			main-uart3-pins-default {
				pinctrl-single,pins = <0x234 0x60003 0x23c 0x10003>;
				phandle = <0x22>;
			};

			main-uart1-pins-default {
				pinctrl-single,pins = <0x1e8 0x50001 0x1ec 0x10001>;
				phandle = <0x20>;
			};

			main-vout-pins-default {
				pinctrl-single,pins = <0x100 0x10000 0xf8 0x10000 0x104 0x10000 0xfc 0x10000 0xb8 0x10000 0xbc 0x10000 0xc0 0x10000 0xc4 0x10000 0xc8 0x10000 0xcc 0x10000 0xd0 0x10000 0xd4 0x10000 0xd8 0x10000 0xdc 0x10000 0xe0 0x10000 0xe4 0x10000 0xe8 0x10000 0xec 0x10000 0xf0 0x10000 0xf4 0x10000 0x5c 0x10001 0x60 0x10001>;
				phandle = <0x65>;
			};
		};

		timer@2400000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2400000 0x00 0x400>;
			interrupts = <0x00 0x78 0x04>;
			clocks = <0x02 0x24 0x02>;
			clock-names = "fck";
			assigned-clocks = <0x02 0x24 0x02>;
			assigned-clock-parents = <0x02 0x24 0x03>;
			power-domains = <0x03 0x24 0x01>;
			ti,timer-pwm;
			phandle = <0xa6>;
		};

		timer@2410000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2410000 0x00 0x400>;
			interrupts = <0x00 0x79 0x04>;
			clocks = <0x02 0x25 0x02>;
			clock-names = "fck";
			assigned-clocks = <0x02 0x25 0x02>;
			assigned-clock-parents = <0x02 0x25 0x03>;
			power-domains = <0x03 0x25 0x01>;
			ti,timer-pwm;
			phandle = <0xa7>;
		};

		timer@2420000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2420000 0x00 0x400>;
			interrupts = <0x00 0x7a 0x04>;
			clocks = <0x02 0x26 0x02>;
			clock-names = "fck";
			assigned-clocks = <0x02 0x26 0x02>;
			assigned-clock-parents = <0x02 0x26 0x03>;
			power-domains = <0x03 0x26 0x01>;
			ti,timer-pwm;
			phandle = <0xa8>;
		};

		timer@2430000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2430000 0x00 0x400>;
			interrupts = <0x00 0x7b 0x04>;
			clocks = <0x02 0x27 0x02>;
			clock-names = "fck";
			assigned-clocks = <0x02 0x27 0x02>;
			assigned-clock-parents = <0x02 0x27 0x03>;
			power-domains = <0x03 0x27 0x01>;
			ti,timer-pwm;
			phandle = <0xa9>;
		};

		timer@2440000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2440000 0x00 0x400>;
			interrupts = <0x00 0x7c 0x04>;
			clocks = <0x02 0x28 0x02>;
			clock-names = "fck";
			assigned-clocks = <0x02 0x28 0x02>;
			assigned-clock-parents = <0x02 0x28 0x03>;
			power-domains = <0x03 0x28 0x01>;
			ti,timer-pwm;
			phandle = <0xaa>;
		};

		timer@2450000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2450000 0x00 0x400>;
			interrupts = <0x00 0x7d 0x04>;
			clocks = <0x02 0x29 0x02>;
			clock-names = "fck";
			assigned-clocks = <0x02 0x29 0x02>;
			assigned-clock-parents = <0x02 0x29 0x03>;
			power-domains = <0x03 0x29 0x01>;
			ti,timer-pwm;
			phandle = <0xab>;
		};

		timer@2460000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2460000 0x00 0x400>;
			interrupts = <0x00 0x7e 0x04>;
			clocks = <0x02 0x2a 0x02>;
			clock-names = "fck";
			assigned-clocks = <0x02 0x2a 0x02>;
			assigned-clock-parents = <0x02 0x2a 0x03>;
			power-domains = <0x03 0x2a 0x01>;
			ti,timer-pwm;
			phandle = <0xac>;
		};

		timer@2470000 {
			compatible = "ti,am654-timer";
			reg = <0x00 0x2470000 0x00 0x400>;
			interrupts = <0x00 0x7f 0x04>;
			clocks = <0x02 0x2b 0x02>;
			clock-names = "fck";
			assigned-clocks = <0x02 0x2b 0x02>;
			assigned-clock-parents = <0x02 0x2b 0x03>;
			power-domains = <0x03 0x2b 0x01>;
			ti,timer-pwm;
			phandle = <0xad>;
		};

		esm@420000 {
			compatible = "ti,j721e-esm";
			reg = <0x00 0x420000 0x00 0x1000>;
			ti,esm-pins = <0xa0 0xa1 0xa2 0xa3 0xb1 0xb2>;
			phandle = <0xae>;
		};

		serial@2800000 {
			compatible = "ti,am64-uart\0ti,am654-uart";
			reg = <0x00 0x2800000 0x00 0x100>;
			interrupts = <0x00 0xb2 0x04>;
			power-domains = <0x03 0x92 0x01>;
			clocks = <0x02 0x92 0x00>;
			clock-names = "fclk";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x1f>;
			dmas = <0x18 0x4400 0x00 0x18 0xc400 0x00>;
			dma-names = "rx\0tx";
			phandle = <0xaf>;
		};

		serial@2810000 {
			compatible = "ti,am64-uart\0ti,am654-uart";
			reg = <0x00 0x2810000 0x00 0x100>;
			interrupts = <0x00 0xb3 0x04>;
			power-domains = <0x03 0x98 0x01>;
			clocks = <0x02 0x98 0x00>;
			clock-names = "fclk";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x20>;
			dmas = <0x18 0x4401 0x00 0x18 0xc401 0x00>;
			dma-names = "rx\0tx";
			phandle = <0xb0>;
		};

		serial@2820000 {
			compatible = "ti,am64-uart\0ti,am654-uart";
			reg = <0x00 0x2820000 0x00 0x100>;
			interrupts = <0x00 0xb4 0x04>;
			power-domains = <0x03 0x99 0x01>;
			clocks = <0x02 0x99 0x00>;
			clock-names = "fclk";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x21>;
			dmas = <0x18 0x4402 0x00 0x18 0xc402 0x00>;
			dma-names = "rx\0tx";
			phandle = <0xb1>;
		};

		serial@2830000 {
			compatible = "ti,am64-uart\0ti,am654-uart";
			reg = <0x00 0x2830000 0x00 0x100>;
			interrupts = <0x00 0xb5 0x04>;
			power-domains = <0x03 0x9a 0x01>;
			clocks = <0x02 0x9a 0x00>;
			clock-names = "fclk";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x22>;
			dmas = <0x18 0x4403 0x00 0x18 0xc403 0x00>;
			dma-names = "rx\0tx";
			phandle = <0xb2>;
		};

		serial@2840000 {
			compatible = "ti,am64-uart\0ti,am654-uart";
			reg = <0x00 0x2840000 0x00 0x100>;
			interrupts = <0x00 0xb6 0x04>;
			power-domains = <0x03 0x9b 0x01>;
			clocks = <0x02 0x9b 0x00>;
			clock-names = "fclk";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x23>;
			dmas = <0x18 0x4404 0x00 0x18 0xc404 0x00>;
			dma-names = "rx\0tx";
			phandle = <0xb3>;
		};

		serial@2850000 {
			compatible = "ti,am64-uart\0ti,am654-uart";
			reg = <0x00 0x2850000 0x00 0x100>;
			interrupts = <0x00 0xb7 0x04>;
			power-domains = <0x03 0x9c 0x01>;
			clocks = <0x02 0x9c 0x00>;
			clock-names = "fclk";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x24>;
			dmas = <0x18 0x4405 0x00 0x18 0xc405 0x00>;
			dma-names = "rx\0tx";
			phandle = <0xb4>;
		};

		serial@2860000 {
			compatible = "ti,am64-uart\0ti,am654-uart";
			reg = <0x00 0x2860000 0x00 0x100>;
			interrupts = <0x00 0xb8 0x04>;
			power-domains = <0x03 0x9e 0x01>;
			clocks = <0x02 0x9e 0x00>;
			clock-names = "fclk";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x25>;
			dmas = <0x18 0x4406 0x00 0x18 0xc406 0x00>;
			dma-names = "rx\0tx";
			phandle = <0xb5>;
		};

		i2c@20000000 {
			compatible = "ti,am64-i2c\0ti,omap4-i2c";
			reg = <0x00 0x20000000 0x00 0x100>;
			interrupts = <0x00 0xa1 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x03 0x66 0x01>;
			clocks = <0x02 0x66 0x02>;
			clock-names = "fck";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x26>;
			clock-frequency = <0x61a80>;
			phandle = <0xb6>;

			dsi@e {
				compatible = "toshiba,tc358778";
				reg = <0x0e>;
				assigned-clocks = <0x02 0x9d 0x14>;
				assigned-clock-parents = <0x02 0x9d 0x16>;
				assigned-clock-rates = <0x17d7840>;
				pinctrl-names = "default";
				pinctrl-0 = <0x27>;
				clocks = <0x02 0x9d 0x14>;
				clock-names = "refclk";
				reset-gpios = <0x28 0x14 0x01>;
				vddc-supply = <0x29>;
				vddmipi-supply = <0x29>;
				vddio-supply = <0x2a>;
				status = "disabled";
				phandle = <0xb7>;

				ports {
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					phandle = <0xb8>;

					port@0 {
						reg = <0x00>;

						endpoint {
							data-lines = <0x12>;
							remote-endpoint = <0x2b>;
							phandle = <0x66>;
						};
					};

					port@1 {
						reg = <0x01>;
					};
				};
			};

			pmic@30 {
				compatible = "ti,tps65219";
				reg = <0x30>;
				pinctrl-names = "default";
				pinctrl-0 = <0x2c>;
				interrupt-parent = <0x01>;
				interrupts = <0x00 0xe0 0x04>;
				buck1-supply = <0x2d>;
				buck2-supply = <0x2d>;
				buck3-supply = <0x2d>;
				ldo1-supply = <0x2e>;
				ldo2-supply = <0x2f>;
				ldo3-supply = <0x2e>;
				ldo4-supply = <0x2e>;
				system-power-controller;
				ti,power-button;

				regulators {

					buck1 {
						regulator-always-on;
						regulator-boot-on;
						regulator-max-microvolt = <0xcf850>;
						regulator-min-microvolt = <0xb71b0>;
						regulator-name = "+VDD_CORE (PMIC BUCK1)";
						phandle = <0xb9>;
					};

					buck2 {
						regulator-always-on;
						regulator-boot-on;
						regulator-max-microvolt = <0x1b7740>;
						regulator-min-microvolt = <0x1b7740>;
						regulator-name = "+V1.8 (PMIC BUCK2)";
						phandle = <0x2f>;
					};

					buck3 {
						regulator-always-on;
						regulator-boot-on;
						regulator-max-microvolt = <0x10c8e0>;
						regulator-min-microvolt = <0x10c8e0>;
						regulator-name = "+VDD_DDR (PMIC BUCK3)";
						phandle = <0xba>;
					};

					ldo1 {
						regulator-allow-bypass;
						regulator-always-on;
						regulator-boot-on;
						regulator-max-microvolt = <0x325aa0>;
						regulator-min-microvolt = <0x325aa0>;
						regulator-name = "+V3.3_1.8_SD (PMIC LDO1)";
						phandle = <0xbb>;
					};

					ldo2 {
						regulator-always-on;
						regulator-boot-on;
						regulator-max-microvolt = <0xcf850>;
						regulator-min-microvolt = <0xcf850>;
						regulator-name = "+VDDR_CORE (PMIC LDO2)";
						phandle = <0xbc>;
					};

					ldo3 {
						regulator-always-on;
						regulator-boot-on;
						regulator-max-microvolt = <0x1b7740>;
						regulator-min-microvolt = <0x1b7740>;
						regulator-name = "+V1.8A (PMIC LDO3)";
						phandle = <0xbd>;
					};

					ldo4 {
						regulator-always-on;
						regulator-boot-on;
						regulator-max-microvolt = <0x2625a0>;
						regulator-min-microvolt = <0x2625a0>;
						regulator-name = "+V2.5_ETH (PMIC LDO4)";
						phandle = <0xbe>;
					};
				};
			};

			rtc@32 {
				compatible = "epson,rx8130";
				reg = <0x32>;
				phandle = <0xbf>;
			};

			adc@49 {
				compatible = "ti,ads1015";
				reg = <0x49>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				channel@0 {
					reg = <0x00>;
					ti,datarate = <0x04>;
					ti,gain = <0x02>;
				};

				channel@1 {
					reg = <0x01>;
					ti,datarate = <0x04>;
					ti,gain = <0x02>;
				};

				channel@2 {
					reg = <0x02>;
					ti,datarate = <0x04>;
					ti,gain = <0x02>;
				};

				channel@3 {
					reg = <0x03>;
					ti,datarate = <0x04>;
					ti,gain = <0x02>;
				};

				channel@4 {
					reg = <0x04>;
					ti,datarate = <0x04>;
					ti,gain = <0x02>;
				};

				channel@5 {
					reg = <0x05>;
					ti,datarate = <0x04>;
					ti,gain = <0x02>;
				};

				channel@6 {
					reg = <0x06>;
					ti,datarate = <0x04>;
					ti,gain = <0x02>;
				};

				channel@7 {
					reg = <0x07>;
					ti,datarate = <0x04>;
					ti,gain = <0x02>;
				};
			};

			eeprom@50 {
				compatible = "st,24c02\0atmel,24c02";
				pagesize = <0x10>;
				reg = <0x50>;
			};
		};

		i2c@20010000 {
			compatible = "ti,am64-i2c\0ti,omap4-i2c";
			reg = <0x00 0x20010000 0x00 0x100>;
			interrupts = <0x00 0xa2 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x03 0x67 0x01>;
			clocks = <0x02 0x67 0x02>;
			clock-names = "fck";
			status = "disabled";
			phandle = <0xc0>;
		};

		i2c@20020000 {
			compatible = "ti,am64-i2c\0ti,omap4-i2c";
			reg = <0x00 0x20020000 0x00 0x100>;
			interrupts = <0x00 0xa3 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x03 0x68 0x01>;
			clocks = <0x02 0x68 0x02>;
			clock-names = "fck";
			status = "disabled";
			phandle = <0xc1>;
		};

		i2c@20030000 {
			compatible = "ti,am64-i2c\0ti,omap4-i2c";
			reg = <0x00 0x20030000 0x00 0x100>;
			interrupts = <0x00 0xa4 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x03 0x69 0x01>;
			clocks = <0x02 0x69 0x02>;
			clock-names = "fck";
			status = "disabled";
			phandle = <0xc2>;
		};

		spi@20100000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x20100000 0x00 0x400>;
			interrupts = <0x00 0xac 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x03 0x8d 0x01>;
			clocks = <0x02 0x8d 0x00>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x30>;
			ti,pindir-d0-out-d1-in;
			ti,spi-num-cs = <0x04>;
			phandle = <0xc3>;

			spidev@0 {
				compatible = "rohm,dh2228fv";
				reg = <0x00>;
				spi-max-frequency = <0x1e8480>;
			};

			switch@1 {
				compatible = "microchip,lan9374";
				reg = <0x01>;
				spi-max-frequency = <0x29f6300>;
				phandle = <0xc4>;

				ethernet-ports {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					port@0 {
						reg = <0x00>;
						label = "lan1";
						phy-mode = "internal";
						phy-handle = <0x31>;
					};

					port@1 {
						reg = <0x01>;
						label = "lan2";
						phy-mode = "internal";
						phy-handle = <0x32>;
					};

					port@2 {
						reg = <0x02>;
						label = "lan4";
						phy-mode = "internal";
						phy-handle = <0x33>;
					};

					port@3 {
						reg = <0x03>;
						label = "lan6";
						phy-mode = "internal";
						phy-handle = <0x34>;
					};

					port@5 {
						reg = <0x05>;
						phy-mode = "rgmii-id";
						tx-internal-delay-ps = <0x7d0>;
						rx-internal-delay-ps = <0x7d0>;
						ethernet = <0x35>;

						fixed-link {
							speed = <0x3e8>;
							full-duplex;
						};
					};

					port@4 {
						reg = <0x04>;
						phy-mode = "rgmii-id";
						tx-internal-delay-ps = <0x7d0>;
						rx-internal-delay-ps = <0x7d0>;
						label = "lan7";

						fixed-link {
							speed = <0x3e8>;
							full-duplex;
						};
					};

					port@6 {
						reg = <0x06>;
						label = "lan5";
						phy-mode = "internal";
						phy-handle = <0x36>;
					};

					port@7 {
						reg = <0x07>;
						label = "lan3";
						phy-mode = "internal";
						phy-handle = <0x37>;
					};
				};

				mdio {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					ethernet-phy@0 {
						reg = <0x00>;
						phandle = <0x31>;
					};

					ethernet-phy@1 {
						reg = <0x01>;
						phandle = <0x32>;
					};

					ethernet-phy@2 {
						reg = <0x02>;
						phandle = <0x33>;
					};

					ethernet-phy@3 {
						reg = <0x03>;
						phandle = <0x34>;
					};

					ethernet-phy@6 {
						reg = <0x06>;
						phandle = <0x36>;
					};

					ethernet-phy@7 {
						reg = <0x07>;
						phandle = <0x37>;
					};
				};
			};

			spidev@2 {
				compatible = "rohm,dh2228fv";
				reg = <0x02>;
				spi-max-frequency = <0x1e8480>;
			};

			max14830@3 {
				compatible = "maxim,max14830";
				reg = <0x03>;
				spi-max-frequency = <0x4c4b40>;
				clocks = <0x38>;
				clock-names = "xtal";
				interrupt-parent = <0x28>;
				interrupts = <0x47 0x02>;
				gpio-controller;
				#gpio-cells = <0x02>;
				phandle = <0xc5>;
			};
		};

		spi@20110000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x20110000 0x00 0x400>;
			interrupts = <0x00 0xad 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x03 0x8e 0x01>;
			clocks = <0x02 0x8e 0x00>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x39>;
			ti,pindir-d0-out-d1-in;
			phandle = <0xc6>;
		};

		spi@20120000 {
			compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
			reg = <0x00 0x20120000 0x00 0x400>;
			interrupts = <0x00 0xae 0x04>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			power-domains = <0x03 0x8f 0x01>;
			clocks = <0x02 0x8f 0x00>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x3a>;
			ti,pindir-d0-out-d1-in;
			ti,spi-num-cs = <0x02>;
			phandle = <0xc7>;
		};

		interrupt-controller@a00000 {
			compatible = "ti,sci-intr";
			reg = <0x00 0xa00000 0x00 0x800>;
			ti,intr-trigger-type = <0x01>;
			interrupt-controller;
			interrupt-parent = <0x01>;
			#interrupt-cells = <0x01>;
			ti,sci = <0x05>;
			ti,sci-dev-id = <0x03>;
			ti,interrupt-ranges = <0x00 0x20 0x10>;
			phandle = <0x3b>;
		};

		gpio@600000 {
			compatible = "ti,am64-gpio\0ti,keystone-gpio";
			reg = <0x00 0x600000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x3b>;
			interrupts = <0xbe 0xbf 0xc0 0xc1 0xc2 0xc3>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x5c>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x03 0x4d 0x01>;
			clocks = <0x02 0x4d 0x00>;
			clock-names = "gpio";
			gpio-line-names = "SODIMM_52 - DO_1V8_CHARGER_2\0SODIMM 186 - DI_1V8_DIM+\0SODIMM 184 - DO_1V8_ON_OFF_LED\0SODIMM_56 - DIO_1V8_903_1\0SODIMM_58 - DI_1V8_BUSY_AFE_4\0SODIMM_60 - DI_1V8_ISH_LIU_MAINT\0SODIMM_62 - DI_1V8_BUSY_AFE_2\0SODIMM_202 - DO_1V8_NCS_AFE_1\0SODIMM 196 - SPI_1_MASTER_SCLK\0SODIMM 200 - SPI_1_MASTER_MOSI\0SODIMM 198 - SPI_1_MASTER_MISO\0SODIMM_54 - DI_1V8_ISH_LEP\0SODIMM_64\0SODIMM 192 - DO_1V8_NCS_AFE_2\0SODIMM 190- DI_1V8_DIM-\0SODIMM_174\0SODIMM_172-DO_1V8_LIU_J01_SALVO\0\0\0\0\0\0\0\0\0\0\0\0\0SODIMM_76\0SODIMM_21\0SODIMM_256- DO_1V8_FRAM_WP\0SODIMM_252- DI_1V8_ST_NDM\0\0SODIMM_46\0SODIMM_42\0SODIMM_218 - DI_1V8_SW7\0\0SODIMM_189\0\0SODIMM_216 - DI_1V8_SW6\0SODIMM_220 - DI_1V8_SW8\0SODIMM_222 - DI_1V8_ISH_FIRING\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0SODIMM 168 - DO_1V8_CONV_AFE_4\0SODIMM 166 - DO_1V8_CONV_AFE_3\0SODIMM 164 - DO_1V8_CONV_AFE_2\0SODIMM 162 - DO_1V8_CONV_AFE_1\0SODIMM 156-UART_6_RXD\0SODIMM 160 -DO_1V8_BL_EN+DISPLAY_EN\0SODIMM_157-DI_1V8_MAX14830_IRQ\0SODIMM_187\0\0\0\0\0\0\0\0\0\0\0\0\0\0";
			pinctrl-names = "default";
			pinctrl-0 = <0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54>;
			phandle = <0x28>;
		};

		gpio@601000 {
			compatible = "ti,am64-gpio\0ti,keystone-gpio";
			reg = <0x00 0x601000 0x00 0x100>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-parent = <0x3b>;
			interrupts = <0xb4 0xb5 0xb6 0xb7 0xb8 0xb9>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ti,ngpio = <0x34>;
			ti,davinci-gpio-unbanked = <0x00>;
			power-domains = <0x03 0x4e 0x01>;
			clocks = <0x02 0x4e 0x00>;
			clock-names = "gpio";
			gpio-line-names = "\0\0\0\0\0SODIMM 151 - DI_1V8_EPU_SUPPLY\0SODIMM 153 - DI_1V8_BATT_SUPPLY\0\0\0SODIMM_36\0SODIMM_34\0SODIMM_30\0SODIMM_32\0\0\0SODIMM_15 - DO_1V8_FPGA_NCS\0SODIMM_16-DO_1V8_LAN9374_NCS\0SODIMM_19 - SPI_3_MASTER_SOM_SCLK\0SODIMM_66\0SODIMM_161-SPI_3_MASTER_LAN_MISO\0SODIMM 147 - UART_3_RXD\0SODIMM 149-UART_3_TXD\0\0\0SODIMM 20 - UART_5_RXD\0\0\0\0SODIMM 14-UART_1_RXD\0SODIMM 12-UART_1_TXD\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0SODIMM_17 - UART_6_TXD\0SODIMM_155\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0";
			pinctrl-names = "default";
			pinctrl-0 = <0x55 0x56>;
			phandle = <0x76>;
		};

		mmc@fa10000 {
			compatible = "ti,am62-sdhci";
			reg = <0x00 0xfa10000 0x00 0x1000 0x00 0xfa18000 0x00 0x400>;
			interrupts = <0x00 0x85 0x04>;
			power-domains = <0x03 0x39 0x01>;
			clocks = <0x02 0x39 0x05 0x02 0x39 0x06>;
			clock-names = "clk_ahb\0clk_xin";
			assigned-clocks = <0x02 0x39 0x06>;
			assigned-clock-parents = <0x02 0x39 0x08>;
			bus-width = <0x08>;
			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			ti,clkbuf-sel = <0x07>;
			ti,otap-del-sel-legacy = <0x00>;
			ti,otap-del-sel-mmc-hs = <0x00>;
			ti,otap-del-sel-ddr52 = <0x05>;
			ti,otap-del-sel-hs200 = <0x05>;
			ti,itap-del-sel-legacy = <0x0a>;
			ti,itap-del-sel-mmc-hs = <0x01>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x57>;
			non-removable;
			ti,driver-strength-ohm = <0x32>;
			phandle = <0xc8>;
		};

		mmc@fa00000 {
			compatible = "ti,am62-sdhci";
			reg = <0x00 0xfa00000 0x00 0x1000 0x00 0xfa08000 0x00 0x400>;
			interrupts = <0x00 0x53 0x04>;
			power-domains = <0x03 0x3a 0x01>;
			clocks = <0x02 0x3a 0x05 0x02 0x3a 0x06>;
			clock-names = "clk_ahb\0clk_xin";
			bus-width = <0x04>;
			ti,clkbuf-sel = <0x07>;
			ti,otap-del-sel-legacy = <0x08>;
			ti,otap-del-sel-sd-hs = <0x00>;
			ti,otap-del-sel-sdr12 = <0x00>;
			ti,otap-del-sel-sdr25 = <0x00>;
			ti,otap-del-sel-sdr50 = <0x08>;
			ti,otap-del-sel-sdr104 = <0x07>;
			ti,otap-del-sel-ddr50 = <0x04>;
			ti,itap-del-sel-legacy = <0x0a>;
			ti,itap-del-sel-sd-hs = <0x01>;
			ti,itap-del-sel-sdr12 = <0x0a>;
			ti,itap-del-sel-sdr25 = <0x01>;
			status = "disabled";
			phandle = <0xc9>;
		};

		mmc@fa20000 {
			compatible = "ti,am62-sdhci";
			reg = <0x00 0xfa20000 0x00 0x1000 0x00 0xfa28000 0x00 0x400>;
			interrupts = <0x00 0x52 0x04>;
			power-domains = <0x03 0xb8 0x01>;
			clocks = <0x02 0xb8 0x05 0x02 0xb8 0x06>;
			clock-names = "clk_ahb\0clk_xin";
			bus-width = <0x04>;
			ti,clkbuf-sel = <0x07>;
			ti,otap-del-sel-legacy = <0x08>;
			ti,otap-del-sel-sd-hs = <0x00>;
			ti,otap-del-sel-sdr12 = <0x00>;
			ti,otap-del-sel-sdr25 = <0x00>;
			ti,otap-del-sel-sdr50 = <0x08>;
			ti,otap-del-sel-sdr104 = <0x07>;
			ti,otap-del-sel-ddr50 = <0x08>;
			ti,itap-del-sel-legacy = <0x0a>;
			ti,itap-del-sel-sd-hs = <0x0a>;
			ti,itap-del-sel-sdr12 = <0x0a>;
			ti,itap-del-sel-sdr25 = <0x01>;
			status = "disabled";
			phandle = <0xca>;
		};

		gpu@fd00000 {
			compatible = "ti,am62-pvr\0img,pvr-axe116m";
			reg = <0x00 0xfd00000 0x00 0x20000>;
			interrupts = <0x00 0x56 0x04>;
			power-domains = <0x03 0xbb 0x01>;
			clocks = <0x02 0xbb 0x00>;
			phandle = <0xcb>;
		};

		dwc3-usb@f900000 {
			compatible = "ti,am62-usb";
			reg = <0x00 0xf900000 0x00 0x800 0x00 0xf908000 0x00 0x400>;
			clocks = <0x02 0xa1 0x03>;
			clock-names = "ref";
			ti,syscon-phy-pll-refclk = <0x58 0x00>;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			power-domains = <0x03 0xb2 0x01>;
			ranges;
			status = "disabled";
			phandle = <0xcc>;

			usb@31000000 {
				compatible = "snps,dwc3";
				reg = <0x00 0x31000000 0x00 0x50000>;
				interrupts = <0x00 0xbc 0x04 0x00 0xbc 0x04>;
				interrupt-names = "host\0peripheral";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				snps,usb2-gadget-lpm-disable;
				snps,usb2-lpm-disable;
				phandle = <0xcd>;
			};
		};

		dwc3-usb@f910000 {
			compatible = "ti,am62-usb";
			reg = <0x00 0xf910000 0x00 0x800 0x00 0xf918000 0x00 0x400>;
			clocks = <0x02 0xa2 0x03>;
			clock-names = "ref";
			ti,syscon-phy-pll-refclk = <0x59 0x00>;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			power-domains = <0x03 0xb3 0x01>;
			ranges;
			status = "okay";
			ti,vbus-divider;
			phandle = <0xce>;

			usb@31100000 {
				compatible = "snps,dwc3";
				reg = <0x00 0x31100000 0x00 0x50000>;
				interrupts = <0x00 0xe2 0x04 0x00 0xe2 0x04>;
				interrupt-names = "host\0peripheral";
				maximum-speed = "high-speed";
				dr_mode = "host";
				snps,usb2-gadget-lpm-disable;
				snps,usb2-lpm-disable;
				status = "okay";
				phandle = <0xcf>;
			};
		};

		bus@fc00000 {
			compatible = "simple-pm-bus";
			reg = <0x00 0xfc00000 0x00 0x70000>;
			power-domains = <0x03 0x4a 0x01>;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges;
			phandle = <0xd0>;

			spi@fc40000 {
				compatible = "ti,am654-ospi\0cdns,qspi-nor";
				reg = <0x00 0xfc40000 0x00 0x100 0x05 0x00 0x01 0x00>;
				interrupts = <0x00 0x8b 0x04>;
				cdns,fifo-depth = <0x100>;
				cdns,fifo-width = <0x04>;
				cdns,trigger-address = <0x00>;
				clocks = <0x02 0x4b 0x07>;
				assigned-clocks = <0x02 0x4b 0x07>;
				assigned-clock-parents = <0x02 0x4b 0x08>;
				assigned-clock-rates = <0x9ef21aa>;
				power-domains = <0x03 0x4b 0x01>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				status = "disabled";
				phandle = <0xd1>;
			};
		};

		ethernet@8000000 {
			compatible = "ti,am642-cpsw-nuss";
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			reg = <0x00 0x8000000 0x00 0x200000>;
			reg-names = "cpsw_nuss";
			ranges = <0x00 0x00 0x00 0x8000000 0x00 0x200000>;
			clocks = <0x02 0x0d 0x00>;
			assigned-clocks = <0x02 0x0d 0x03>;
			assigned-clock-parents = <0x02 0x0d 0x0b>;
			clock-names = "fck";
			power-domains = <0x03 0x0d 0x01>;
			dmas = <0x18 0xc600 0x0f 0x18 0xc601 0x0f 0x18 0xc602 0x0f 0x18 0xc603 0x0f 0x18 0xc604 0x0f 0x18 0xc605 0x0f 0x18 0xc606 0x0f 0x18 0xc607 0x0f 0x18 0x4600 0x0f>;
			dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";
			pinctrl-names = "default";
			pinctrl-0 = <0x5a 0x5b>;
			status = "okay";
			phandle = <0x35>;

			ethernet-ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@1 {
					reg = <0x01>;
					ti,mac-only;
					label = "port1";
					phys = <0x5c 0x01>;
					mac-address = [00 00 00 00 00 00];
					ti,syscon-efuse = <0x5d 0x200>;
					phy-handle = <0x5e>;
					phy-mode = "rgmii-rxid";
					status = "okay";
					phandle = <0xd2>;
				};

				port@2 {
					reg = <0x02>;
					ti,mac-only;
					label = "port2";
					phys = <0x5c 0x02>;
					mac-address = [00 00 00 00 00 00];
					status = "okay";
					phy-mode = "rgmii-id";
					phandle = <0xd3>;

					fixed-link {
						speed = <0x64>;
						full-duplex;
					};
				};
			};

			mdio@f00 {
				compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
				reg = <0x00 0xf00 0x00 0x100>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clocks = <0x02 0x0d 0x00>;
				clock-names = "fck";
				bus_freq = <0xf4240>;
				status = "okay";
				assigned-clocks = <0x02 0x9d 0x14>;
				assigned-clock-parents = <0x02 0x9d 0x16>;
				assigned-clock-rates = <0x17d7840>;
				pinctrl-names = "default";
				pinctrl-0 = <0x5f 0x60>;
				phandle = <0xd4>;

				ethernet-phy@0 {
					compatible = "ethernet-phy-id2000.a231";
					reg = <0x00>;
					interrupt-parent = <0x28>;
					interrupts = <0x19 0x02>;
					pinctrl-names = "default";
					pinctrl-0 = <0x61 0x62>;
					reset-gpios = <0x28 0x11 0x01>;
					reset-assert-us = <0x0a>;
					reset-deassert-us = <0x3e8>;
					ti,fifo-depth = <0x01>;
					ti,rx-internal-delay = <0x07>;
					phandle = <0x5e>;
				};

				ethernet-phy@1 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <0x01>;
					interrupt-parent = <0x28>;
					interrupts = <0x26 0x02>;
					pinctrl-names = "default";
					pinctrl-0 = <0x63>;
					micrel,led-mode = <0x00>;
					phandle = <0xd5>;
				};
			};

			cpts@3d000 {
				compatible = "ti,j721e-cpts";
				reg = <0x00 0x3d000 0x00 0x400>;
				clocks = <0x02 0x0d 0x03>;
				clock-names = "cpts";
				interrupts-extended = <0x01 0x00 0x66 0x04>;
				interrupt-names = "cpts";
				ti,cpts-ext-ts-inputs = <0x04>;
				ti,cpts-periodic-outputs = <0x02>;
			};
		};

		dss@30200000 {
			compatible = "ti,am625-dss";
			reg = <0x00 0x30200000 0x00 0x1000 0x00 0x30202000 0x00 0x1000 0x00 0x30206000 0x00 0x1000 0x00 0x30207000 0x00 0x1000 0x00 0x30208000 0x00 0x1000 0x00 0x3020a000 0x00 0x1000 0x00 0x3020b000 0x00 0x1000 0x00 0x30201000 0x00 0x1000>;
			reg-names = "common\0vidl1\0vid\0ovr1\0ovr2\0vp1\0vp2\0common1";
			ti,am65x-oldi-io-ctrl = <0x64>;
			power-domains = <0x03 0xba 0x01>;
			clocks = <0x02 0xba 0x06 0x02 0xba 0x00 0x02 0xba 0x02>;
			clock-names = "fck\0vp1\0vp2";
			interrupts = <0x00 0x54 0x04>;
			pinctrl-names = "default";
			pinctrl-0 = <0x65>;
			status = "okay";
			phandle = <0xd6>;

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				phandle = <0xd7>;

				port@1 {
					reg = <0x01>;

					endpoint {
						remote-endpoint = <0x66>;
						phandle = <0x2b>;
					};
				};

				port@0 {
					reg = <0x00>;

					endpoint {
						remote-endpoint = <0x67>;
						phandle = <0x79>;
					};
				};

				port@2 {
					reg = <0x02>;

					endpoint {
						remote-endpoint = <0x68>;
						phandle = <0x7a>;
					};
				};
			};
		};

		pinctrl@a40000 {
			compatible = "pinctrl-single";
			reg = <0x00 0xa40000 0x00 0x800>;
			#pinctrl-cells = <0x01>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x107ff>;
			status = "disabled";
			phandle = <0xd8>;
		};

		spinlock@2a000000 {
			compatible = "ti,am64-hwspinlock";
			reg = <0x00 0x2a000000 0x00 0x1000>;
			#hwlock-cells = <0x01>;
			phandle = <0xd9>;
		};

		mailbox@29000000 {
			compatible = "ti,am64-mailbox";
			reg = <0x00 0x29000000 0x00 0x200>;
			interrupts = <0x00 0x4c 0x04 0x00 0x4d 0x04>;
			#mbox-cells = <0x01>;
			ti,mbox-num-users = <0x04>;
			ti,mbox-num-fifos = <0x10>;
			status = "disabled";
			phandle = <0xda>;
		};

		pwm@23100000 {
			compatible = "ti,am3352-ecap";
			#pwm-cells = <0x03>;
			reg = <0x00 0x23100000 0x00 0x100>;
			power-domains = <0x03 0x33 0x01>;
			clocks = <0x02 0x33 0x00>;
			clock-names = "fck";
			status = "disabled";
			phandle = <0xdb>;
		};

		pwm@23110000 {
			compatible = "ti,am3352-ecap";
			#pwm-cells = <0x03>;
			reg = <0x00 0x23110000 0x00 0x100>;
			power-domains = <0x03 0x34 0x01>;
			clocks = <0x02 0x34 0x00>;
			clock-names = "fck";
			status = "disabled";
			phandle = <0xdc>;
		};

		pwm@23120000 {
			compatible = "ti,am3352-ecap";
			#pwm-cells = <0x03>;
			reg = <0x00 0x23120000 0x00 0x100>;
			power-domains = <0x03 0x35 0x01>;
			clocks = <0x02 0x35 0x00>;
			clock-names = "fck";
			status = "disabled";
			phandle = <0xdd>;
		};

		counter@23200000 {
			compatible = "ti,am3352-eqep";
			reg = <0x00 0x23200000 0x00 0x100>;
			power-domains = <0x03 0x3b 0x01>;
			clocks = <0x02 0x3b 0x00>;
			clock-names = "fck";
			interrupts = <0x00 0x74 0x01>;
			status = "disabled";
			phandle = <0xde>;
		};

		counter@23210000 {
			compatible = "ti,am3352-eqep";
			reg = <0x00 0x23210000 0x00 0x100>;
			power-domains = <0x03 0x3c 0x01>;
			clocks = <0x02 0x3c 0x00>;
			clock-names = "fck";
			interrupts = <0x00 0x75 0x01>;
			status = "disabled";
			phandle = <0xdf>;
		};

		counter@23220000 {
			compatible = "ti,am3352-eqep";
			reg = <0x00 0x23220000 0x00 0x100>;
			power-domains = <0x03 0x3e 0x01>;
			clocks = <0x02 0x3e 0x00>;
			clock-names = "fck";
			interrupts = <0x00 0x76 0x01>;
			status = "disabled";
			phandle = <0xe0>;
		};

		can@20701000 {
			compatible = "bosch,m_can";
			reg = <0x00 0x20701000 0x00 0x200 0x00 0x20708000 0x00 0x8000>;
			reg-names = "m_can\0message_ram";
			power-domains = <0x03 0x62 0x01>;
			clocks = <0x02 0x62 0x06 0x02 0x62 0x01>;
			clock-names = "hclk\0cclk";
			interrupts = <0x00 0x9b 0x04 0x00 0x9c 0x04>;
			interrupt-names = "int0\0int1";
			bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0xe1>;
		};

		watchdog@e000000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x00 0xe000000 0x00 0x100>;
			clocks = <0x02 0x7d 0x00>;
			power-domains = <0x03 0x7d 0x01>;
			assigned-clocks = <0x02 0x7d 0x00>;
			assigned-clock-parents = <0x02 0x7d 0x02>;
			phandle = <0xe2>;
		};

		watchdog@e010000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x00 0xe010000 0x00 0x100>;
			clocks = <0x02 0x7e 0x00>;
			power-domains = <0x03 0x7e 0x01>;
			assigned-clocks = <0x02 0x7e 0x00>;
			assigned-clock-parents = <0x02 0x7e 0x02>;
			phandle = <0xe3>;
		};

		watchdog@e020000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x00 0xe020000 0x00 0x100>;
			clocks = <0x02 0x7f 0x00>;
			power-domains = <0x03 0x7f 0x01>;
			assigned-clocks = <0x02 0x7f 0x00>;
			assigned-clock-parents = <0x02 0x7f 0x02>;
			phandle = <0xe4>;
		};

		watchdog@e030000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x00 0xe030000 0x00 0x100>;
			clocks = <0x02 0x80 0x00>;
			power-domains = <0x03 0x80 0x01>;
			assigned-clocks = <0x02 0x80 0x00>;
			assigned-clock-parents = <0x02 0x80 0x02>;
			phandle = <0xe5>;
		};

		watchdog@e0f0000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x00 0xe0f0000 0x00 0x100>;
			clocks = <0x02 0x82 0x00>;
			power-domains = <0x03 0x82 0x01>;
			assigned-clocks = <0x02 0x82 0x00>;
			assigned-clock-parents = <0x02 0x82 0x02>;
			phandle = <0xe6>;
		};

		pwm@23000000 {
			compatible = "ti,am64-epwm\0ti,am3352-ehrpwm";
			#pwm-cells = <0x03>;
			reg = <0x00 0x23000000 0x00 0x100>;
			power-domains = <0x03 0x56 0x01>;
			clocks = <0x69 0x00 0x02 0x56 0x00>;
			clock-names = "tbclk\0fck";
			status = "disabled";
			phandle = <0xe7>;
		};

		pwm@23010000 {
			compatible = "ti,am64-epwm\0ti,am3352-ehrpwm";
			#pwm-cells = <0x03>;
			reg = <0x00 0x23010000 0x00 0x100>;
			power-domains = <0x03 0x57 0x01>;
			clocks = <0x69 0x01 0x02 0x57 0x00>;
			clock-names = "tbclk\0fck";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x6a>;
			phandle = <0x77>;
		};

		pwm@23020000 {
			compatible = "ti,am64-epwm\0ti,am3352-ehrpwm";
			#pwm-cells = <0x03>;
			reg = <0x00 0x23020000 0x00 0x100>;
			power-domains = <0x03 0x58 0x01>;
			clocks = <0x69 0x02 0x02 0x58 0x00>;
			clock-names = "tbclk\0fck";
			status = "disabled";
			phandle = <0xe8>;
		};

		audio-controller@2b00000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b00000 0x00 0x2000 0x00 0x2b08000 0x00 0x400>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0xec 0x04 0x00 0xeb 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x17 0x00 0xc500 0x00 0x17 0x00 0x4500 0x00>;
			dma-names = "tx\0rx";
			clocks = <0x02 0xbe 0x00>;
			clock-names = "fck";
			assigned-clocks = <0x02 0xbe 0x00>;
			assigned-clock-parents = <0x02 0xbe 0x02>;
			power-domains = <0x03 0xbe 0x01>;
			status = "disabled";
			phandle = <0xe9>;
		};

		audio-controller@2b10000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b10000 0x00 0x2000 0x00 0x2b18000 0x00 0x400>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0xee 0x04 0x00 0xed 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x17 0x00 0xc501 0x00 0x17 0x00 0x4501 0x00>;
			dma-names = "tx\0rx";
			clocks = <0x02 0xbf 0x00>;
			clock-names = "fck";
			assigned-clocks = <0x02 0xbf 0x00>;
			assigned-clock-parents = <0x02 0xbf 0x02>;
			power-domains = <0x03 0xbf 0x01>;
			status = "disabled";
			phandle = <0xea>;
		};

		audio-controller@2b20000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x00 0x2b20000 0x00 0x2000 0x00 0x2b28000 0x00 0x400>;
			reg-names = "mpu\0dat";
			interrupts = <0x00 0xf0 0x04 0x00 0xef 0x04>;
			interrupt-names = "tx\0rx";
			dmas = <0x17 0x00 0xc502 0x00 0x17 0x00 0x4502 0x00>;
			dma-names = "tx\0rx";
			clocks = <0x02 0xc0 0x00>;
			clock-names = "fck";
			assigned-clocks = <0x02 0xc0 0x00>;
			assigned-clock-parents = <0x02 0xc0 0x02>;
			power-domains = <0x03 0xc0 0x01>;
			status = "disabled";
			phandle = <0xeb>;
		};

		ticsi2rx@30102000 {
			compatible = "ti,j721e-csi2rx";
			dmas = <0x17 0x00 0x4700 0x00 0x17 0x00 0x4701 0x00 0x17 0x00 0x4702 0x00 0x17 0x00 0x4703 0x00>;
			dma-names = "rx0\0rx1\0rx2\0rx3";
			reg = <0x00 0x30102000 0x00 0x1000>;
			power-domains = <0x03 0xb6 0x01>;
			#address-cells = <0x02>;
			#size-cells = <0x02>;
			ranges;
			status = "disabled";
			phandle = <0xec>;

			csi-bridge@30101000 {
				compatible = "cdns,csi2rx";
				reg = <0x00 0x30101000 0x00 0x1000>;
				clocks = <0x02 0xb6 0x00 0x02 0xb6 0x03 0x02 0xb6 0x00 0x02 0xb6 0x00 0x02 0xb6 0x04 0x02 0xb6 0x04>;
				clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";
				phys = <0x6b>;
				phy-names = "dphy";
				power-domains = <0x03 0xb6 0x01>;
				phandle = <0xed>;

				ports {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					port@0 {
						reg = <0x00>;
						status = "disabled";
						phandle = <0xee>;
					};

					port@1 {
						reg = <0x01>;
						status = "disabled";
						phandle = <0xef>;
					};

					port@2 {
						reg = <0x02>;
						status = "disabled";
						phandle = <0xf0>;
					};

					port@3 {
						reg = <0x03>;
						status = "disabled";
						phandle = <0xf1>;
					};

					port@4 {
						reg = <0x04>;
						status = "disabled";
						phandle = <0xf2>;
					};
				};
			};
		};

		phy@30110000 {
			compatible = "cdns,dphy-rx";
			reg = <0x00 0x30110000 0x00 0x1100>;
			#phy-cells = <0x00>;
			power-domains = <0x03 0xb9 0x01>;
			status = "disabled";
			phandle = <0x6b>;
		};

		memory-controller@3b000000 {
			status = "disabled";
			compatible = "ti,am64-gpmc";
			power-domains = <0x03 0x50 0x01>;
			clocks = <0x02 0x50 0x00>;
			clock-names = "fck";
			reg = <0x00 0x3b000000 0x00 0x400 0x00 0x50000000 0x00 0x8000000>;
			reg-names = "cfg\0data";
			interrupts = <0x00 0x6a 0x04>;
			gpmc,num-cs = <0x03>;
			gpmc,num-waitpins = <0x02>;
			#address-cells = <0x02>;
			#size-cells = <0x01>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			gpio-controller;
			#gpio-cells = <0x02>;
			phandle = <0xf3>;
		};

		ecc@25010000 {
			status = "disabled";
			compatible = "ti,am3352-elm";
			reg = <0x00 0x25010000 0x00 0x2000>;
			interrupts = <0x00 0x84 0x04>;
			power-domains = <0x03 0x36 0x01>;
			clocks = <0x02 0x36 0x00>;
			clock-names = "fck";
			phandle = <0xf4>;
		};

		pruss@30040000 {
			compatible = "ti,am625-pruss";
			reg = <0x00 0x30040000 0x00 0x80000>;
			power-domains = <0x03 0x51 0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x00 0x30040000 0x80000>;
			phandle = <0xf5>;

			memories@0 {
				reg = <0x00 0x2000 0x2000 0x2000 0x10000 0x10000>;
				reg-names = "dram0\0dram1\0shrdram2";
				phandle = <0xf6>;
			};

			cfg@26000 {
				compatible = "ti,pruss-cfg\0syscon";
				reg = <0x26000 0x200>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x26000 0x2000>;
				phandle = <0xf7>;

				clocks {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					coreclk-mux@3c {
						reg = <0x3c>;
						#clock-cells = <0x00>;
						clocks = <0x02 0x51 0x00 0x02 0x51 0x14>;
						assigned-clocks = <0x6c>;
						assigned-clock-parents = <0x02 0x51 0x14>;
						phandle = <0x6c>;
					};

					iepclk-mux@30 {
						reg = <0x30>;
						#clock-cells = <0x00>;
						clocks = <0x02 0x51 0x03 0x6c>;
						assigned-clocks = <0x6d>;
						assigned-clock-parents = <0x6c>;
						phandle = <0x6d>;
					};
				};
			};

			interrupt-controller@20000 {
				compatible = "ti,pruss-intc";
				reg = <0x20000 0x2000>;
				interrupt-controller;
				#interrupt-cells = <0x03>;
				interrupts = <0x00 0x58 0x04 0x00 0x59 0x04 0x00 0x5a 0x04 0x00 0x5b 0x04 0x00 0x5c 0x04 0x00 0x5d 0x04 0x00 0x5e 0x04 0x00 0x5f 0x04>;
				interrupt-names = "host_intr0\0host_intr1\0host_intr2\0host_intr3\0host_intr4\0host_intr5\0host_intr6\0host_intr7";
				phandle = <0x6e>;
			};

			pru@34000 {
				compatible = "ti,am625-pru";
				reg = <0x34000 0x3000 0x22000 0x100 0x22400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "am62x-pru0-fw";
				interrupt-parent = <0x6e>;
				interrupts = <0x10 0x02 0x02>;
				interrupt-names = "vring";
				phandle = <0xf8>;
			};

			pru@38000 {
				compatible = "ti,am625-pru";
				reg = <0x38000 0x3000 0x24000 0x100 0x24400 0x100>;
				reg-names = "iram\0control\0debug";
				firmware-name = "am62x-pru1-fw";
				interrupt-parent = <0x6e>;
				interrupts = <0x12 0x03 0x03>;
				interrupt-names = "vring";
				phandle = <0xf9>;
			};
		};
	};

	thermal-zones {
		phandle = <0xfa>;

		main0-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x6f 0x00>;
			phandle = <0xfb>;

			trips {

				main0-crit {
					temperature = <0x19a28>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0xfc>;
				};
			};
		};

		main1-thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x6f 0x01>;
			phandle = <0xfd>;

			trips {

				main1-crit {
					temperature = <0x19a28>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0xfe>;
				};
			};
		};
	};

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		cpu-map {

			cluster0 {
				phandle = <0xff>;

				core0 {
					cpu = <0x70>;
				};

				core1 {
					cpu = <0x71>;
				};

				core2 {
					cpu = <0x72>;
				};

				core3 {
					cpu = <0x73>;
				};
			};
		};

		cpu@0 {
			compatible = "arm,cortex-a53";
			reg = <0x00>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x80>;
			next-level-cache = <0x74>;
			operating-points-v2 = <0x75>;
			clocks = <0x02 0x87 0x00>;
			phandle = <0x70>;
		};

		cpu@1 {
			compatible = "arm,cortex-a53";
			reg = <0x01>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x80>;
			next-level-cache = <0x74>;
			operating-points-v2 = <0x75>;
			clocks = <0x02 0x88 0x00>;
			phandle = <0x71>;
		};

		cpu@2 {
			compatible = "arm,cortex-a53";
			reg = <0x02>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x80>;
			next-level-cache = <0x74>;
			operating-points-v2 = <0x75>;
			clocks = <0x02 0x89 0x00>;
			phandle = <0x72>;
		};

		cpu@3 {
			compatible = "arm,cortex-a53";
			reg = <0x03>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x80>;
			next-level-cache = <0x74>;
			operating-points-v2 = <0x75>;
			clocks = <0x02 0x8a 0x00>;
			phandle = <0x73>;
		};
	};

	opp-table {
		compatible = "operating-points-v2-ti-cpu";
		opp-shared;
		syscon = <0x5d>;
		phandle = <0x75>;

		opp-200000000 {
			opp-hz = <0x00 0xbebc200>;
			opp-supported-hw = <0x01 0x07>;
			clock-latency-ns = <0x5b8d80>;
		};

		opp-400000000 {
			opp-hz = <0x00 0x17d78400>;
			opp-supported-hw = <0x01 0x07>;
			clock-latency-ns = <0x5b8d80>;
		};

		opp-600000000 {
			opp-hz = <0x00 0x23c34600>;
			opp-supported-hw = <0x01 0x07>;
			clock-latency-ns = <0x5b8d80>;
		};

		opp-800000000 {
			opp-hz = <0x00 0x2faf0800>;
			opp-supported-hw = <0x01 0x07>;
			clock-latency-ns = <0x5b8d80>;
		};

		opp-1000000000 {
			opp-hz = <0x00 0x3b9aca00>;
			opp-supported-hw = <0x01 0x06>;
			clock-latency-ns = <0x5b8d80>;
		};

		opp-1250000000 {
			opp-hz = <0x00 0x4a817c80>;
			opp-supported-hw = <0x01 0x04>;
			clock-latency-ns = <0x5b8d80>;
			opp-suspend;
		};

		opp-1400000000 {
			opp-hz = <0x00 0x53724e00>;
			opp-supported-hw = <0x01 0x04>;
			clock-latency-ns = <0x5b8d80>;
		};
	};

	l2-cache0 {
		compatible = "cache";
		cache-unified;
		cache-level = <0x02>;
		cache-size = <0x80000>;
		cache-line-size = <0x40>;
		cache-sets = <0x200>;
		phandle = <0x74>;
	};

	aliases {
		ethernet0 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@1";
		ethernet1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2";
		i2c0 = "/bus@f0000/i2c@20000000";
		i2c1 = "/bus@f0000/i2c@20010000";
		mmc0 = "/bus@f0000/mmc@fa10000";
		mmc1 = "/bus@f0000/mmc@fa00000";
		mmc2 = "/bus@f0000/mmc@fa20000";
		rtc0 = "/bus@f0000/i2c@20000000/rtc@32";
		rtc1 = "/bus@f0000/bus@b00000/rtc@2b1f0000";
		serial0 = "/bus@f0000/serial@2810000";
		serial1 = "/bus@f0000/bus@b00000/target-module@2b300050/serial@0";
		serial2 = "/bus@f0000/serial@2800000";
		serial3 = "/bus@f0000/serial@2820000";
		serial4 = "/bus@f0000/serial@2850000";
		serial5 = "/bus@f0000/serial@2830000";
		serial6 = "/bus@f0000/serial@2840000";
		serial7 = "/bus@f0000/serial@2860000";
		usb0 = "/bus@f0000/dwc3-usb@f900000/usb@31000000";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00 0x80000000 0x00 0x40000000>;
	};

	regulator-5v {
		compatible = "regulator-fixed";
		regulator-name = "5v-dummy-regulator";
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		phandle = <0x100>;
	};

	regulator-vref {
		compatible = "regulator-fixed";
		regulator-name = "4V095 dummy";
		regulator-min-microvolt = <0x2625a0>;
		regulator-max-microvolt = <0x2625a0>;
		regulator-always-on;
		phandle = <0x101>;
	};

	regulator-delay {
		compatible = "regulator-fixed";
		regulator-name = "delay-reg";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		startup-delay-us = <0x30d40>;
		regulator-always-on;
		phandle = <0x102>;
	};

	regulator-vsodimm {
		compatible = "regulator-fixed";
		regulator-name = "+V_SODIMM";
		phandle = <0x2d>;
	};

	regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <0x325aa0>;
		regulator-min-microvolt = <0x325aa0>;
		regulator-name = "On-module +V3.3";
		vin-supply = <0x2d>;
		phandle = <0x2e>;
	};

	regulator-1v2-dsi {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <0x124f80>;
		regulator-min-microvolt = <0x124f80>;
		regulator-name = "On-module +V1.2_DSI";
		vin-supply = <0x2f>;
		phandle = <0x29>;
	};

	regulator-1v8-dsi {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <0x1b7740>;
		regulator-min-microvolt = <0x1b7740>;
		regulator-name = "On-module +V1.8_DSI";
		vin-supply = <0x2f>;
		phandle = <0x2a>;
	};

	regulator-1v0-eth {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <0xf4240>;
		regulator-min-microvolt = <0xf4240>;
		regulator-name = "On-module +V1.0_ETH";
		vin-supply = <0x2f>;
		phandle = <0x103>;
	};

	regulator-1v8-eth {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <0x1b7740>;
		regulator-min-microvolt = <0x1b7740>;
		regulator-name = "On-module +V1.8_ETH";
		vin-supply = <0x2f>;
		phandle = <0x104>;
	};

	reserved-memory {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		tfa@9e780000 {
			reg = <0x00 0x9e780000 0x00 0x80000>;
			alignment = <0x1000>;
			no-map;
			phandle = <0x105>;
		};

		optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x1800000>;
			alignment = <0x1000>;
			no-map;
			phandle = <0x106>;
		};

		r5f-memory@9db00000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9db00000 0x00 0xc00000>;
			no-map;
			phandle = <0x107>;
		};
	};

	clk16m0 {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0x384000>;
		clock-accuracy = <0x64>;
		phandle = <0x38>;
	};

	backlight-mezzanine {
		compatible = "pwm-backlight";
		brightness-levels = <0x00 0x03 0x05 0x08 0x0a 0x0d 0x0f 0x12 0x14 0x17 0x1a 0x1c 0x1f 0x21 0x24 0x26 0x29 0x2b 0x2e 0x30 0x33 0x36 0x38 0x3b 0x3d 0x40 0x42 0x45 0x47 0x4a 0x4d 0x4f 0x52 0x54 0x57 0x59 0x5c 0x5e 0x61 0x64 0x66 0x69 0x6b 0x6e 0x70 0x73 0x75 0x78 0x7b 0x7d 0x80 0x82 0x85 0x87 0x8a 0x8c 0x8f 0x91 0x94 0x97 0x99 0x9c 0x9e 0xa1 0xa3 0xa6 0xa8 0xab 0xad 0xb0 0xb2 0xb5 0xb8 0xba 0xbd 0xbf 0xc2 0xc4 0xc7 0xc9 0xcc 0xce 0xd1 0xd3 0xd6 0xd9 0xdb 0xde 0xe0 0xe3 0xe5 0xe8 0xea 0xed 0xef 0xf2 0xf4 0xf7 0xfa 0xfc 0xff>;
		default-brightness-level = <0x32>;
		enable-gpios = <0x76 0x33 0x00>;
		pwms = <0x77 0x01 0x65b9ab 0x01>;
		phandle = <0x78>;
	};

	panel-lvds-mez {
		compatible = "panel-lvds";
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		backlight = <0x78>;
		data-mapping = "vesa-24";
		height-mm = <0x7f>;
		width-mm = <0xe1>;

		panel-timing {
			clock-frequency = <0x7f1ff20 0x8075be0 0x81b3200>;
			hactive = <0x780>;
			hback-porch = <0x0a 0x32 0x8c>;
			hfront-porch = <0x14 0x50 0x82>;
			hsync-len = <0x10>;
			pixelclk-active = <0x00>;
			vactive = <0x438>;
			vback-porch = <0x01 0x05 0x0a>;
			vfront-porch = <0x04 0x05 0x0a>;
			vsync-len = <0x05>;
		};

		port@0 {
			reg = <0x00>;
			dual-lvds-odd-pixels;

			endpoint {
				remote-endpoint = <0x79>;
				phandle = <0x67>;
			};
		};

		port@1 {
			reg = <0x01>;
			dual-lvds-even-pixels;

			endpoint {
				remote-endpoint = <0x7a>;
				phandle = <0x68>;
			};
		};
	};

	__symbols__ {
		psci = "/firmware/psci";
		a53_timer0 = "/timer-cl0-cpu0";
		pmu = "/pmu";
		cbass_main = "/bus@f0000";
		cbass_mcu = "/bus@f0000/bus@4000000";
		mcu_pmx0 = "/bus@f0000/bus@4000000/pinctrl@4084000";
		pinctrl_gpio_mcu_0 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio0-0-pins-default";
		pinctrl_gpio_mcu_1 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio0-1-pins-default";
		pinctrl_gpio_mcu_2 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio0-2-pins-default";
		pinctrl_gpio_mcu_3 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio0-3-pins-default";
		pinctrl_gpio_mcu_4 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio0-4-pins-default";
		pinctrl_gpio_mcu_5 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio-5-default";
		pinctrl_gpio_mcu_6 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio-6-default";
		pinctrl_gpio_mcu_7 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio-7-default";
		pinctrl_gpio_mcu_8 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio-8-default";
		pinctrl_gpio_mcu_11 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio-11-default";
		pinctrl_gpio_mcu_12 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio-12-default";
		pinctrl_gpio_mcu_13 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio0-13-pins-default";
		pinctrl_gpio_mcu_14 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio0-14-pins-default";
		pinctrl_gpio_mcu_15 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio0-15-pins-default";
		pinctrl_gpio_mcu_16 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio0-16-pins-default";
		pinctrl_gpio_mcu_23 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-gpio-23-default";
		pinctrl_wkup_uart0 = "/bus@f0000/bus@4000000/pinctrl@4084000/wkup-uart0-pins-default";
		pinctrl_mcu_i2c0 = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-i2c0-pins-default";
		mcu_timer0 = "/bus@f0000/bus@4000000/timer@4800000";
		mcu_timer1 = "/bus@f0000/bus@4000000/timer@4810000";
		mcu_timer2 = "/bus@f0000/bus@4000000/timer@4820000";
		mcu_timer3 = "/bus@f0000/bus@4000000/timer@4830000";
		mcu_esm = "/bus@f0000/bus@4000000/esm@4100000";
		mcu_uart0 = "/bus@f0000/bus@4000000/serial@4a00000";
		mcu_i2c0 = "/bus@f0000/bus@4000000/i2c@4900000";
		mcu_spi0 = "/bus@f0000/bus@4000000/spi@4b00000";
		mcu_spi1 = "/bus@f0000/bus@4000000/spi@4b10000";
		mcu_gpio_intr = "/bus@f0000/bus@4000000/interrupt-controller@4210000";
		mcu_gpio0 = "/bus@f0000/bus@4000000/gpio@4201000";
		mcu_rti0 = "/bus@f0000/bus@4000000/watchdog@4880000";
		mcu_m4fss = "/bus@f0000/bus@4000000/m4fss@5000000";
		mcu_mcan0 = "/bus@f0000/bus@4000000/can@4e08000";
		mcu_mcan1 = "/bus@f0000/bus@4000000/can@4e18000";
		cbass_wakeup = "/bus@f0000/bus@b00000";
		wkup_conf = "/bus@f0000/bus@b00000/syscon@43000000";
		chipid = "/bus@f0000/bus@b00000/syscon@43000000/chipid@14";
		usb0_phy_ctrl = "/bus@f0000/bus@b00000/syscon@43000000/syscon@4008";
		usb1_phy_ctrl = "/bus@f0000/bus@b00000/syscon@43000000/syscon@4018";
		wkup_uart0 = "/bus@f0000/bus@b00000/target-module@2b300050/serial@0";
		wkup_i2c0 = "/bus@f0000/bus@b00000/i2c@2b200000";
		wkup_rtc0 = "/bus@f0000/bus@b00000/rtc@2b1f0000";
		wkup_rti0 = "/bus@f0000/bus@b00000/watchdog@2b000000";
		wkup_r5fss0 = "/bus@f0000/bus@b00000/r5fss@78000000";
		wkup_r5fss0_core0 = "/bus@f0000/bus@b00000/r5fss@78000000/r5f@78000000";
		wkup_vtm0 = "/bus@f0000/bus@b00000/temperature-sensor@b00000";
		oc_sram = "/bus@f0000/sram@70000000";
		gic500 = "/bus@f0000/interrupt-controller@1800000";
		gic_its = "/bus@f0000/interrupt-controller@1800000/msi-controller@1820000";
		main_conf = "/bus@f0000/syscon@100000";
		phy_gmii_sel = "/bus@f0000/syscon@100000/phy@4044";
		epwm_tbclk = "/bus@f0000/syscon@100000/clock@4130";
		dss_oldi_io_ctrl = "/bus@f0000/syscon@100000/dss-oldi-io-ctrl@8600";
		audio_refclk0 = "/bus@f0000/syscon@100000/clock@82e0";
		audio_refclk1 = "/bus@f0000/syscon@100000/clock@82e4";
		dmss = "/bus@f0000/bus@48000000";
		secure_proxy_main = "/bus@f0000/bus@48000000/mailbox@4d000000";
		inta_main_dmss = "/bus@f0000/bus@48000000/interrupt-controller@48000000";
		main_bcdma = "/bus@f0000/bus@48000000/dma-controller@485c0100";
		main_pktdma = "/bus@f0000/bus@48000000/dma-controller@485c0000";
		dmsc = "/bus@f0000/system-controller@44043000";
		k3_pds = "/bus@f0000/system-controller@44043000/power-controller";
		k3_clks = "/bus@f0000/system-controller@44043000/clock-controller";
		k3_reset = "/bus@f0000/system-controller@44043000/reset-controller";
		crypto = "/bus@f0000/crypto@40900000";
		mcrc = "/bus@f0000/mcrc@30300000";
		secure_proxy_sa3 = "/bus@f0000/mailbox@43600000";
		main_pmx0 = "/bus@f0000/pinctrl@f4000";
		pinctrl_gpio0_0 = "/bus@f0000/pinctrl@f4000/main-gpio0-0-pins-default";
		pinctrl_gpio0_3 = "/bus@f0000/pinctrl@f4000/main-gpio0-3-pins-default";
		pinctrl_gpio0_4 = "/bus@f0000/pinctrl@f4000/main-gpio0-4-pins-default";
		pinctrl_gpio0_5 = "/bus@f0000/pinctrl@f4000/main-gpio0-5-pins-default";
		pinctrl_gpio0_6 = "/bus@f0000/pinctrl@f4000/main-gpio0-6-pins-default";
		pinctrl_gpio0_12 = "/bus@f0000/pinctrl@f4000/main-gpio0-12-pins-default";
		pinctrl_gpio0_11 = "/bus@f0000/pinctrl@f4000/main-gpio0-11-pins-default";
		pinctrl_gpio0_18 = "/bus@f0000/pinctrl@f4000/main-gpio0-18-pins-default";
		pinctrl_gpio0_70 = "/bus@f0000/pinctrl@f4000/main-gpio0-70-pins-default";
		pinctrl_gpio0_68 = "/bus@f0000/pinctrl@f4000/main-gpio0-68-pins-default";
		pinctrl_gpio0_67 = "/bus@f0000/pinctrl@f4000/main-gpio0-67-pins-default";
		pinctrl_gpio0_66 = "/bus@f0000/pinctrl@f4000/main-gpio0-66-pins-default";
		pinctrl_gpio0_65 = "/bus@f0000/pinctrl@f4000/main-gpio0-65-pins-default";
		pinctrl_gpio0_16 = "/bus@f0000/pinctrl@f4000/main-gpio0-16-pins-default";
		pinctrl_gpio0_2 = "/bus@f0000/pinctrl@f4000/main-gpio0-2-pins-default";
		pinctrl_gpio0_1 = "/bus@f0000/pinctrl@f4000/main-gpio0-1-pins-default";
		pinctrl_gpio0_14 = "/bus@f0000/pinctrl@f4000/main-gpio0-14-pins-default";
		pinctrl_gpio0_33 = "/bus@f0000/pinctrl@f4000/main-gpio0-33-pins-default";
		pinctrl_gpio0_34 = "/bus@f0000/pinctrl@f4000/main-gpio0-34-pins-default";
		pinctrl_gpio0_35 = "/bus@f0000/pinctrl@f4000/main-gpio0-35-pins-default";
		pinctrl_gpio0_37 = "/bus@f0000/pinctrl@f4000/main-gpio0-37-pins-default";
		pinctrl_gpio1_12 = "/bus@f0000/pinctrl@f4000/main-gpio1-12-pins-default";
		pinctrl_gpio1_10 = "/bus@f0000/pinctrl@f4000/main-gpio1-10-pins-default";
		pinctrl_gpio0_71 = "/bus@f0000/pinctrl@f4000/main-gpio0-71-pins-default";
		pinctrl__gpio1_51 = "/bus@f0000/pinctrl@f4000/main-gpio1-51-pins-default";
		pinctrl_eth_reset = "/bus@f0000/pinctrl@f4000/main-gpio0-17-pins-default";
		pinctrl_bridge_reset = "/bus@f0000/pinctrl@f4000/main-gpio0-20-pins-default";
		pinctrl_vsel_sd = "/bus@f0000/pinctrl@f4000/main-gpio0-21-pins-default";
		pinctrl_wifi_en = "/bus@f0000/pinctrl@f4000/main-gpio0-22-pins-default";
		pinctrl_eth_int = "/bus@f0000/pinctrl@f4000/main-gpio0-25-pins-default";
		pinctrl_wifi_wkup_bt = "/bus@f0000/pinctrl@f4000/main-gpio0-26-pins-default";
		pinctrl_wifi_wkup_wlan = "/bus@f0000/pinctrl@f4000/main-gpio0-27-pins-default";
		pinctrl_gpio0_31 = "/bus@f0000/pinctrl@f4000/main-gpio0-31-pins-default";
		pinctrl_gpio0_32 = "/bus@f0000/pinctrl@f4000/main-gpio0-32-pins-default";
		pinctrl_eth2_rgmii_int = "/bus@f0000/pinctrl@f4000/main-gpio0-38-pins-default";
		pinctrl_gpio0_36 = "/bus@f0000/pinctrl@f4000/main-gpio0-36-pins-default";
		pinctrl_gpio0_40 = "/bus@f0000/pinctrl@f4000/main-gpio0-40-pins-default";
		pinctrl_gpio0_41 = "/bus@f0000/pinctrl@f4000/main-gpio0-41-pins-default";
		pinctrl_gpio0_42 = "/bus@f0000/pinctrl@f4000/main-gpio0-42-pins-default";
		pinctrl_i2c0 = "/bus@f0000/pinctrl@f4000/main-i2c0-pins-default";
		pinctrl_mdio = "/bus@f0000/pinctrl@f4000/main-mdio1-pins-default";
		pinctrl_sdhci0 = "/bus@f0000/pinctrl@f4000/main-mmc0-pins-default";
		pinctrl_rgmii1 = "/bus@f0000/pinctrl@f4000/main-rgmii1-pins-default";
		pinctrl_rgmii2 = "/bus@f0000/pinctrl@f4000/main-rgmii2-pins-default";
		pinctrl_spi1 = "/bus@f0000/pinctrl@f4000/main-spi1-pins-default";
		pinctrl_spi2 = "/bus@f0000/pinctrl@f4000/main-spi2-pins-defaults";
		pinctrl_spi0 = "/bus@f0000/pinctrl@f4000/main-spi0-pins-default";
		pinctrl_eth_clock = "/bus@f0000/pinctrl@f4000/main-system-clkout0-pins-default";
		pinctrl_pmic_extint = "/bus@f0000/pinctrl@f4000/main-system-extint-pins-default";
		pinctrl_uart0 = "/bus@f0000/pinctrl@f4000/main-uart0-pins-default";
		pinctrl_uart4 = "/bus@f0000/pinctrl@f4000/main-uart4-pins-default";
		pinctrl_uart6 = "/bus@f0000/pinctrl@f4000/main-uart6-pins-default";
		pinctrl_uart5 = "/bus@f0000/pinctrl@f4000/main-uart5-pins-default";
		pinctrl_uart2 = "/bus@f0000/pinctrl@f4000/main-uart2-pins-default";
		pinctrl_uart3 = "/bus@f0000/pinctrl@f4000/main-uart3-pins-default";
		pinctrl_uart1 = "/bus@f0000/pinctrl@f4000/main-uart1-pins-default";
		pinctrl_parallel_rgb = "/bus@f0000/pinctrl@f4000/main-vout-pins-default";
		main_timer0 = "/bus@f0000/timer@2400000";
		main_timer1 = "/bus@f0000/timer@2410000";
		main_timer2 = "/bus@f0000/timer@2420000";
		main_timer3 = "/bus@f0000/timer@2430000";
		main_timer4 = "/bus@f0000/timer@2440000";
		main_timer5 = "/bus@f0000/timer@2450000";
		main_timer6 = "/bus@f0000/timer@2460000";
		main_timer7 = "/bus@f0000/timer@2470000";
		main_esm = "/bus@f0000/esm@420000";
		main_uart0 = "/bus@f0000/serial@2800000";
		main_uart1 = "/bus@f0000/serial@2810000";
		main_uart2 = "/bus@f0000/serial@2820000";
		main_uart3 = "/bus@f0000/serial@2830000";
		main_uart4 = "/bus@f0000/serial@2840000";
		main_uart5 = "/bus@f0000/serial@2850000";
		main_uart6 = "/bus@f0000/serial@2860000";
		main_i2c0 = "/bus@f0000/i2c@20000000";
		dsi_bridge = "/bus@f0000/i2c@20000000/dsi@e";
		dsi_bridge_ports = "/bus@f0000/i2c@20000000/dsi@e/ports";
		rgb_in = "/bus@f0000/i2c@20000000/dsi@e/ports/port@0/endpoint";
		reg_vdd_core = "/bus@f0000/i2c@20000000/pmic@30/regulators/buck1";
		reg_1v8 = "/bus@f0000/i2c@20000000/pmic@30/regulators/buck2";
		reg_vdd_ddr = "/bus@f0000/i2c@20000000/pmic@30/regulators/buck3";
		reg_sd_3v3_1v8 = "/bus@f0000/i2c@20000000/pmic@30/regulators/ldo1";
		reg_vddr_core = "/bus@f0000/i2c@20000000/pmic@30/regulators/ldo2";
		reg_1v8a = "/bus@f0000/i2c@20000000/pmic@30/regulators/ldo3";
		reg_eth_2v5 = "/bus@f0000/i2c@20000000/pmic@30/regulators/ldo4";
		rtc_i2c = "/bus@f0000/i2c@20000000/rtc@32";
		main_i2c1 = "/bus@f0000/i2c@20010000";
		main_i2c2 = "/bus@f0000/i2c@20020000";
		main_i2c3 = "/bus@f0000/i2c@20030000";
		main_spi0 = "/bus@f0000/spi@20100000";
		lan9374 = "/bus@f0000/spi@20100000/switch@1";
		t1phy0 = "/bus@f0000/spi@20100000/switch@1/mdio/ethernet-phy@0";
		t1phy1 = "/bus@f0000/spi@20100000/switch@1/mdio/ethernet-phy@1";
		t1phy2 = "/bus@f0000/spi@20100000/switch@1/mdio/ethernet-phy@2";
		t1phy3 = "/bus@f0000/spi@20100000/switch@1/mdio/ethernet-phy@3";
		t1phy6 = "/bus@f0000/spi@20100000/switch@1/mdio/ethernet-phy@6";
		t1phy7 = "/bus@f0000/spi@20100000/switch@1/mdio/ethernet-phy@7";
		max14830 = "/bus@f0000/spi@20100000/max14830@3";
		main_spi1 = "/bus@f0000/spi@20110000";
		main_spi2 = "/bus@f0000/spi@20120000";
		main_gpio_intr = "/bus@f0000/interrupt-controller@a00000";
		main_gpio0 = "/bus@f0000/gpio@600000";
		main_gpio1 = "/bus@f0000/gpio@601000";
		sdhci0 = "/bus@f0000/mmc@fa10000";
		sdhci1 = "/bus@f0000/mmc@fa00000";
		sdhci2 = "/bus@f0000/mmc@fa20000";
		gpu = "/bus@f0000/gpu@fd00000";
		usbss0 = "/bus@f0000/dwc3-usb@f900000";
		usb0 = "/bus@f0000/dwc3-usb@f900000/usb@31000000";
		usbss1 = "/bus@f0000/dwc3-usb@f910000";
		usb1 = "/bus@f0000/dwc3-usb@f910000/usb@31100000";
		fss = "/bus@f0000/bus@fc00000";
		ospi0 = "/bus@f0000/bus@fc00000/spi@fc40000";
		cpsw3g = "/bus@f0000/ethernet@8000000";
		cpsw_port1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@1";
		cpsw_port2 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2";
		cpsw3g_mdio = "/bus@f0000/ethernet@8000000/mdio@f00";
		cpsw3g_phy0 = "/bus@f0000/ethernet@8000000/mdio@f00/ethernet-phy@0";
		cpsw3g_phy1 = "/bus@f0000/ethernet@8000000/mdio@f00/ethernet-phy@1";
		dss = "/bus@f0000/dss@30200000";
		dss_ports = "/bus@f0000/dss@30200000/ports";
		dpi_out = "/bus@f0000/dss@30200000/ports/port@1/endpoint";
		oldi_out0 = "/bus@f0000/dss@30200000/ports/port@0/endpoint";
		oldi_out1 = "/bus@f0000/dss@30200000/ports/port@2/endpoint";
		timesync_router = "/bus@f0000/pinctrl@a40000";
		hwspinlock = "/bus@f0000/spinlock@2a000000";
		mailbox0_cluster0 = "/bus@f0000/mailbox@29000000";
		ecap0 = "/bus@f0000/pwm@23100000";
		ecap1 = "/bus@f0000/pwm@23110000";
		ecap2 = "/bus@f0000/pwm@23120000";
		eqep0 = "/bus@f0000/counter@23200000";
		eqep1 = "/bus@f0000/counter@23210000";
		eqep2 = "/bus@f0000/counter@23220000";
		main_mcan0 = "/bus@f0000/can@20701000";
		main_rti0 = "/bus@f0000/watchdog@e000000";
		main_rti1 = "/bus@f0000/watchdog@e010000";
		main_rti2 = "/bus@f0000/watchdog@e020000";
		main_rti3 = "/bus@f0000/watchdog@e030000";
		main_rti15 = "/bus@f0000/watchdog@e0f0000";
		epwm0 = "/bus@f0000/pwm@23000000";
		epwm1 = "/bus@f0000/pwm@23010000";
		epwm2 = "/bus@f0000/pwm@23020000";
		mcasp0 = "/bus@f0000/audio-controller@2b00000";
		mcasp1 = "/bus@f0000/audio-controller@2b10000";
		mcasp2 = "/bus@f0000/audio-controller@2b20000";
		ti_csi2rx0 = "/bus@f0000/ticsi2rx@30102000";
		cdns_csi2rx0 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000";
		csi0_port0 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@0";
		csi0_port1 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@1";
		csi0_port2 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@2";
		csi0_port3 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@3";
		csi0_port4 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@4";
		dphy0 = "/bus@f0000/phy@30110000";
		gpmc0 = "/bus@f0000/memory-controller@3b000000";
		elm0 = "/bus@f0000/ecc@25010000";
		pruss = "/bus@f0000/pruss@30040000";
		pruss_mem = "/bus@f0000/pruss@30040000/memories@0";
		pruss_cfg = "/bus@f0000/pruss@30040000/cfg@26000";
		pruss_coreclk_mux = "/bus@f0000/pruss@30040000/cfg@26000/clocks/coreclk-mux@3c";
		pruss_iepclk_mux = "/bus@f0000/pruss@30040000/cfg@26000/clocks/iepclk-mux@30";
		pruss_intc = "/bus@f0000/pruss@30040000/interrupt-controller@20000";
		pru0 = "/bus@f0000/pruss@30040000/pru@34000";
		pru1 = "/bus@f0000/pruss@30040000/pru@38000";
		thermal_zones = "/thermal-zones";
		main0_thermal = "/thermal-zones/main0-thermal";
		main0_crit = "/thermal-zones/main0-thermal/trips/main0-crit";
		main1_thermal = "/thermal-zones/main1-thermal";
		main1_crit = "/thermal-zones/main1-thermal/trips/main1-crit";
		cluster0 = "/cpus/cpu-map/cluster0";
		cpu0 = "/cpus/cpu@0";
		cpu1 = "/cpus/cpu@1";
		cpu2 = "/cpus/cpu@2";
		cpu3 = "/cpus/cpu@3";
		a53_opp_table = "/opp-table";
		L2_0 = "/l2-cache0";
		reg_5v_dummy = "/regulator-5v";
		vref_4v095_reg = "/regulator-vref";
		delay_reg = "/regulator-delay";
		reg_vsodimm = "/regulator-vsodimm";
		reg_3v3 = "/regulator-3v3";
		reg_1v2_dsi = "/regulator-1v2-dsi";
		reg_1v8_dsi = "/regulator-1v8-dsi";
		reg_1v0_eth = "/regulator-1v0-eth";
		reg_1v8_eth = "/regulator-1v8-eth";
		secure_tfa_ddr = "/reserved-memory/tfa@9e780000";
		secure_ddr = "/reserved-memory/optee@9e800000";
		wkup_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@9db00000";
		clk16m0 = "/clk16m0";
		backlight_mezzanine = "/backlight-mezzanine";
		panel_lvds_in0 = "/panel-lvds-mez/port@0/endpoint";
		panel_lvds_in1 = "/panel-lvds-mez/port@1/endpoint";
	};
};

Hi Naveenkumar, 

Just an experiment but could you try putting a reference to your switch in the &cpsw_port2 node in your DTS?

/* Verdin ETH_2_RGMII */
&cpsw_port2 {

	status = "okay";
	phy-mode = "rgmii-rxid";
	
	phy-handle = <&lan9374>; <--- something like this
	
	fixed-link {
		speed = <100>;
		full-duplex;
	};
};

I'm also having our CPSW developer take a look at your DTS; however, this may take some time. Unfortunately, since we have no way to implementing an external switch on TI EVMs, we have no way of replicating your issue which makes it difficult to provide a solution. We can only offer suggestions as we think of them.

-Daolin

Hi Daolin Qiu,

we have tried this, but we did not see any ping. if you have any updates kindly let me know.

Hi Naveenkumar,

Looking closer at your decompiled DTB and the latest DTS you sent via E2E direct message, I'm seeing both "cpsw3g_phy0" and "cpsw3g_phy1" are defined under the cpsw3g_mdio node. From my understanding, "cpsw3g_phy0" should be the phy attached to AM62x RGMII1. However, what is the purpose of "cpsw3g_phy1"? cpsw3g_phy1 also appears to have a "micrel,led-mode" property which implies it is related to the LAN9374? However, it looks like your LAN9374 should be communicating with the AM62x via SPI and not MDIO, according to your DTS configuration. 

-Daolin

Hi Daolin Qiu,

yes, you are right, LAN9374 is configured through SPI and not MDIO.

Hi Naveenkumar, 

Daolin Qiu said:

From my understanding, "cpsw3g_phy0" should be the phy attached to AM62x RGMII1. However, what is the purpose of "cpsw3g_phy1"? cpsw3g_phy1 also appears to have a "micrel,led-mode" property which implies it is related to the LAN9374?

Thanks for confirming that LAN9374 communicates with AM62x via SPI. However, if that is the case, why do you have "cpsw3g_phy1" under the cpsw3g_mdio node? Can you clarify this part (quoted) of my question?

-Daolin

Hi Daolin Qiu,

we have removed the cpsw3g_phy1 property from our device tree and we are no longer using it, we are using only LAN9374.

is there any updates regarding the changes needed for cpsw3g, as you mentioned your cpsw expert is looking in to the issue, any inputs from the experts regarding this issue?

Hi Naveenkumar, 

Daolin Qiu said:

I'm also having our CPSW developer take a look at your DTS; however, this may take some time. Unfortunately, since we have no way to implementing an external switch on TI EVMs, we have no way of replicating your issue which makes it difficult to provide a solution. We can only offer suggestions as we think of them.

Thanks for checking in. I'm meeting with CPSW developer tomorrow, as I have said, we can only offer suggestions as we think of them as we cannot directly test nor replicate this issue directly on our TI EVMs.

-Daolin

Hi Daolin Qiu,

Thanks for the support, any help regarding this would be appreciated.

Hi Naveenkumar, 

Unfortunately, we don't have any further suggestions at this point in time. From my personal prospective, I think using "cpsw3g" instead of "cpsw_port2" should be correct because comparing with past customer use cases, "cpsw3g" was used so the DSA driver is initialized. Unfortunately, when it comes to the DSA driver, we are not the experts on the Linux DSA driver since it is not a TI specific driver. 

Currently, as we cannot reproduce this issue, we cannot prioritize it/give a direct solution, we can only provide suggestions as we think of them.

-Daolin

Hi Daolin Qiu,

Thanks for the update.

If i disable the cpsw_port1 and if i reassign ethernet0  = cpsw_port2, will the system make eth1 as eth0.

i made below changes in the device tree

 {
	chosen {
		stdout-path = "serial2:115200n8";
	};

	aliases {
		ethernet0 = &cpsw_port2;
		//ethernet1 = &cpsw_port1;
		i2c0 = &main_i2c0;
		i2c1 = &main_i2c1;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
		mmc2 = &sdhci2;
		rtc0 = &rtc_i2c;
		rtc1 = &wkup_rtc0;
		serial0 = &main_uart1;
		serial1 = &wkup_uart0;
		serial2 = &main_uart0;
		serial3 = &main_uart2;
		serial4 = &main_uart5;
		serial5 = &main_uart3;
		serial6 = &main_uart4;
		serial7 = &main_uart6;
		usb0 = &usb0;
	};
};

&cpsw3g {
	pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_rgmii2>;
	//pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
	status = "disabled";
};

/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
	phy-handle = <&cpsw3g_phy0>;
	phy-mode = "rgmii-rxid";
	status = "disabled";
};

/* Verdin ETH_2_RGMII */
&cpsw_port2 {
	status = "disabled";
};

/* Verdin ETHs */
&cpsw3g {
	pinctrl-names = "default";
	status = "okay";
};

/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
	status = "okay";
#if 0
	cpsw3g_phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
		micrel,led-mode = <0>;
	};
#endif
};

/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
	status = "disabled";
};

/* Verdin ETH_2_RGMII */
&cpsw_port2 {
	phy-mode = "rgmii-id";
	status = "okay";
	fixed-link {
                    speed = <1000>;
                    full-duplex;
                   }; 
	
};

by doing the above changes will it make eth1 as eth0?

Hi Naveenkumar, 

naveenkumar Muthusamy said:

by doing the above changes will it make eth1 as eth0?

I know that the aliases property in the DTS should be how the interface name (i.e. "eth0", "eth1", etc) once in the Linux userspace gets linked with the physical port (e.g. port associated with &cpsw_port1 or &cpsw_port2). So my understanding is that your change should make "eth0" be linked with &cpsw_port2. That being said, I personally have not tested it out to verify if my understanding is correct so I encourage you test out your change to see if indeed does what I described.

-Daolin

Unlocking this thread so the conversation in  AM625: Ethernet switch LAN9374 bring up with the AM625 can be continued here.

-Daolin 

tv310 

For traceability, can you please attach the latest DTS you are using for the switch integration?

Since this thread is several months old, can you please inform us on the latest status this issue? 

After a quick glance at your latest DTS it looks like you changed the fixed-link configuration from the &cpsw3g node back to &cpsw_port2 node? From what I understood, this causes problems with switch initialization. However if fixed-link is used in &cpsw3g node at least switch initialization works. 

-Daolin

Hi Daolin Qiu , we have tried having fixed link in cpsw3g as well and tried using cpsw_port2 as a reference for LAN9374. in this case the initialization fails but when we use cpsw3g as a reference node LAN9374, the initialization works but it always binds to eth0 instead of eth1. since this is not the expected use case for us, this is not helpful and we are stuck at this point with no more further steps to be done. we even tried the kernel driver changes that you have suggested earlier, still no communication with switch.

Hi Naveenkumar, 

Apologies if this might be a repeat but by kernel driver changes did you mean applying the below suggestion on the device tree when the cpsw3g node was used as a reference in the configuration for LAN9374? Just wanted to clarify that it was not the case when cpsw_port2 was used as the reference node.

Daolin Qiu said:

I know that the aliases property in the DTS should be how the interface name (i.e. "eth0", "eth1", etc) once in the Linux userspace gets linked with the physical port (e.g. port associated with &cpsw_port1 or &cpsw_port2). So my understanding is that your change should make "eth0" be linked with &cpsw_port2. That being said, I personally have not tested it out to verify if my understanding is correct so I encourage you test out your change to see if indeed does what I described.

-Daolin

Hi Daolin Qiu ,

Daolin Qiu said:

Since the patch was made by the other customer, it will be hard for me to comment on what changes are needed. Additionally, the DSA driver is not a TI specific driver so our support on making modifications on the DSA driver is limited. I proposed looking at that patch made by the other customer as a starting point for you in case helps you but I won't be able to provide specific steps on how to fix any issues you may see as result of trying the patch out.

to clear your doubt, i was referring the above reply from you to make the changes in the kernel dsa drivers. i made the changes suggested in the above post, when doing this i was able see that LAN9374 was getting connected to the eth1. but still no communication.

Hi Naveenkumar, 

Have you double checked that the device tree settings for your LAN9374 is configured correctly?

Also, I don't have any visibility in the driver for your LAN9374 switch, but have you looked into its driver to see if it assumes the switch is connected to the primary Ethernet interface (or cpsw_port1)?

-Daolin

Update:

I dove deeper into the DTS files shared in  https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1557237/am625-ethernet-switch-lan9374-bring-up-with-the-am625 

Below are my comments/suggestions

1) Pinmux configuration for RGMII1 and RGMII2 match that of AM6254 Quad Core A53, Features G. Base features from the Sysconfig tool

2) &cpsw_port2

• past customers have used "phy-handle" to point to the label of the switch node, for your case it would be "&lan9374", I would try adding a "phy-handle" pointing to "&lan9374"
• phy-mode is "rgmii-id" and not "rgmii-rxid", is this intentional?
• fixed-link had speed of "100" and not "1000", is this intentional?
• please fix the indentation for the fixed-link configuration, there are extra indents for the "speed" and "full-duplex configuration"

3) &main_spi0

• I'm not an expert on SPI DTS configuration nor can I comment on the LAN9374 DTS settings; however past customers have mentioned that when referencing the specific cpsw port, "&cpsw3g" must be used and not (in your case) "&cpsw_port2" otherwise the DSA driver is not initiated at all. I would suggest referencing "&cpsw3g" here but make sure the equivalent "fixed-link" configuration still stays with "&cpsw_port2".
• Please fix the formatting of the indents for better readability.

Please let me know if you have questions about my suggestions.

-Daolin