This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3352: Frame Sync to 8 kHz in AM3352 Device Tree Configuration

Part Number: AM3352

Tool/software:

Hi Experts,

I am currently working on interfacing the AM3352 with a modem device designed to operate as a PCM Slave with a 2048 kHz clock and 8 kHz frame sync. The connection between the SoC and the modem does not involve an audio codec, and the configuration is as follows:

The goal is to play an audio file on the Linux side and hear the audio stream when a phone call is answered. In this case, I need the AM3352 to function as the PCM master. I have already configured the PCM interface on the AM3352, and it successfully generates a 2 MHz clock. However, with this setup, the frame sync is set to 62.5 kHz, which is not what I need.

Could you please assist me in adjusting my device tree to achieve an 8 kHz frame sync?

Below is my current device tree configuration with audio-related nodes:

sound {
compatible = "simple-audio-card";
simple-audio-card,name = "TI AM335x";
simple-audio-card,format = "i2s";

/* MCASP is master, Quectel is slave */
simple-audio-card,bitclock-master = <&cpu_dai>;
simple-audio-card,frame-master = <&cpu_dai>;

cpu_dai: simple-audio-card,cpu {
sound-dai = <&mcasp0>;
system-clock-frequency = <3072000>;
system-clock-direction-out;
};

simple-audio-card,codec {
sound-dai = <&dummy_codec>;
};
};

dummy_codec: dummy_codec {
#sound-dai-cells = <0>;
compatible = "ti,wilink8_bt";
status = "okay";
};

/* Audio interface */
mcasp0_pins: mcasp0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx - COM_AUD_CLK */
AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx - COM_AUD_FSYNC */
AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0 - COM_AUD_IN */
AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 - COM_AUD_OUT */
>;
};

/* Audio interface */
&mcasp0 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcasp0_pins>;
status = "okay";
op-mode = <0>; /* MCASP_I2S_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
2 0 1 0 /* ARX0, ARX1, ARX2 & ARX3 */
>;
tx-num-evt = <32>;
rx-num-evt = <32>;

auxclk-fs-ratio = <256>;
};

Issue:

According to the documentation, I understand that the auxclk-fs-ratio property should be used to adjust the frame sync. However, modifying this value does not seem to change the behavior of the frame sync, which remains at 62.5 kHz.

Note: I am using ti,wilink8_bt as the dummy codec because the snd-soc-dummy driver is not functioning correctly, but I believe this is not the root cause of the issue, as it pertains to frame sync adjustment, not the codec.

I would greatly appreciate your assistance in helping me adjust the device tree so that the frame sync is set to 8 kHz as required.

Thank you for your support.

   

  • Hello,

    What version of Linux is being used?

    Regards,

    Nick

  • Hello Nestor,

    Can you provide the above detail that Nick is asking? Along with that, can you also provide, if AM3352 is the clock intiator, are you using the internal AUXCLK to configure the BCLK? 

    Also bear in mind: McASP only has integer dividers so we are limited on the frequencies that could be supported. For example, 48khz/16bit/2channel configuration will not work when using an internal AUX clock: 24000000/(48000*2*16)=15.625 (not an integer divider). In this case, our application would request a 48khz frequency but the output will be different and we would see underflow warning messages. 

    Hope this helps.

    Best Regards,

    Suren

  • Hi Nick,

    I am using a Linux Yocto based distribution with 5.4.20-g738552d0b0 Kernel.

    Regards,

  • Hi Suren,

    Yes, the AM3352 is indeed the clock initiator in our configuration. However, in my current setup, I am not using the AUXCLK to configure the BCLK. Could you please provide an example of how to configure AUXCLK for the BCLK in the device tree? This will help me ensure the clocking is properly set up.

    Regarding the frequency limitations, I understand that McASP uses integer dividers. Given this, I would adjust the BCLK configuration for 2000 kHz and the Frame SYNC to 7812.5 kHz as the best possible option.

    This setup avoids the issue of non-integer divisors (e.g., the 48 kHz configuration you mentioned), which would lead to underflow warnings.

    Looking forward to your guidance on the configuration to reach the MCASP clock to 2000kHz and Frame SYNC to 7.8125 kHz

    Regards, 

  • Hi Nestor,

    You mentioned seeing 2MHz clock? Where are you seeing this clock?

    . I have already configured the PCM interface on the AM3352, and it successfully generates a 2 MHz clock. However, with this setup, the frame sync is set to 62.5 kHz, which is not what I need.

    Also can you change the system-clock-frequency to 24000000 instead of 3072000 and try once?

    Also you can refer the below thread:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/607500/linux-processor-sdk-am335x-mcasp-master-mode-configuration

    Best Regards,

    Suren

  • Hi Suren,

    I am seeing the 2 MHz clock on the MCASP_ACLKX pin. Below is the oscilloscope image showing the signal:

    With the same setup, I measured the signal on the MCASP_FSX pin, which is currently at 62.5 kHz:

    After changing the system-clock-frequency to 24000000 instead of 3072000, I observed the following:

    MCASP_ACLKX is now at 258.078KHz:

    MCASP_FSX is now at 8.06KHz:

    The clock signal begins when I start playing an audio file and stops once the file finishes playing.

    Thank you for the reference to the thread. It was very helpful while I was trying to generate the clock. I’ll review it again to make sure I haven’t missed anything.

    Regards,  

  • Hi Nestor,

    Do you still require support here? If not, I will go ahead and close the thread now that you have been able to achieve 8KHz Frame sync.

    Best Regards,

    Suren

  • Hi Suren,

    Yes please. I achieve 8KHz frame sync with a 256KHz clock. The PCM slave that it is connected to the AM3352 MCASP interface needs 8KHz frame sync with a 2048KHz clock.

    Any other advice?  

  • Hi Suren,

    The modem manufacturer helped me to configure the PCM slave to work with the configuration mentioned above. However, we require a short frame synchronization format instead of the current long frame sync format.

    Could you please advise if there is a way to change the frame sync from long synchronization to short synchronization on the SOC side?

    Best Regards,

  • Hi Nestor,

    I am checking it internally with the team. Please give me a day/two to respond back.

    Best Regards,

    Suren