DRA821U: Failed to connect J7200 EVM with Blackhawk USB560v2 System Tracer debugger (BH-USB-560v2)

FYI, the on-board XDS110 debugger has no this connection problem. SW3.2 on EVM is in ON position. I have the same connection problem to my custom board and this is why I'd like to verify on EVM first. 

See if the below thread help:

https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/887187/ccs-blackhawk-usb560v2-system-trace-stuck-in-safe-mode

https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/666125/ccs-tms320vc5509a-xds560v2-bh-usb-560v2-stuck-in-bootup-mode-usb-red-mode-flashing-green/2450162#2450162

Thanks.

Also this --> https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1178240/faq-sk-tda4vm-how-do-i-connect-the-external-debugger-blackhawk-usb560v2-xds560v2-usb-system-trace-to-the-jtag-on-the-board

Thanks.

Hi Praveen,

Thanks for sharing the information, but they don't apply to my case. Both LEDs on my USB560v2 are green so the situation in the first two threads is different from my issue. I also tried on Linux machine, lsusb correctly detected the debugger but the test connection still failed. The logs are attached below.

edr@RHLX0001:~$ lsusb
Bus 002 Device 002: ID 0bda:0328 Realtek Semiconductor Corp. USB3.0-CRW
Bus 002 Device 003: ID 0bda:0411 Realtek Semiconductor Corp. Hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 002: ID 0bda:818b Realtek Semiconductor Corp. RTL8192EU 802.11b/g/n WLAN Adapter
Bus 001 Device 006: ID 0b1e:0009 Electronic Warfare Assoc., Inc. (EWA) Blackhawk USB560v2 System Trace Emulator
Bus 001 Device 003: ID 0bda:5411 Realtek Semiconductor Corp. RTS5411 Hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

CCS Test Connection Log:

[Start: Blackhawk XDS560v2-USB System Trace Emulator_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]

-----[Print the board config pathname(s)]------------------------------------

/home/edr/.ti/ccs1281/0/0/BrdDat/testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'libbh560v2u.out'.
Loaded FPGA Image: /home/edr/ti/ccs1281/ccs/ccs_base/common/uscif/./dtc_top.jbc
The library build date was 'Sep 26 2024'.
The library build time was '10:02:16'.
The library package version is '20.0.0.3178'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.

An error occurred while hard opening the controller.

[End: Blackhawk XDS560v2-USB System Trace Emulator_0]

Okay, can you tell us why you're not using the onboard XDS110 interface?

Also, how are you connecting your USB560v2 to the J7200 EVM?

We generally use the onboard XDS110 interface. Based on your above answers, we may need to check and try at our end to see if we encounter the same issue you mentioned. 

Thanks.

Hi Praveen,

I actually want to debug my custom board which doesn't have XDS110, but I found USB560v2 doesn't work with our custom board. So I tried it with EVM and found it doesn't work either. I connect USB560v2 to EVM through MIPI 60 connector.

We gave it a try with the Blackhawk XDS5560v2, and we are able to connect successfully with the TI EVM. The test connection log is below. Do you have an extra XDS560v2 that you could try?

[Start: Blackhawk XDS560v2-USB System Trace Emulator_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

/home/a0389345local/.ti/ccs1250/0/0/BrdDat/
    testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'libbh560v2u.out'.
Loaded FPGA Image: /home/a0389345local/ti/ccs1250/ccs/ccs_base/common/uscif/./dtc_top.jbc
The library build date was 'Sep  6 2023'.
The library build time was '14:41:42'.
The library package version is '9.13.0.00201'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '6' (0x00000006).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: /home/a0389345local/ti/ccs1250/ccs/ccs_base/common/uscif/./dtc_top.jbc

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

  Test  Size   Coord      MHz    Flag  Result       Description
  ~~~~  ~~~~  ~~~~~~~  ~~~~~~~~  ~~~~  ~~~~~~~~~~~  ~~~~~~~~~~~~~~~~~~~
    1   none  - 01 00  500.0kHz   -    similar      isit internal clock
    2   none  - 01 09  570.3kHz   -    similar      isit internal clock
    3     64  - 01 00  500.0kHz   O    good value   measure path length
    4     16  - 01 00  500.0kHz   O    good value   auto step initial
    5     16  - 01 0D  601.6kHz   O    good value   auto step delta
    6     16  - 01 1C  718.8kHz   O    good value   auto step delta
    7     16  - 01 2E  859.4kHz   O    good value   auto step delta
    8     16  + 00 02  1.031MHz   O    good value   auto step delta
    9     16  + 00 0F  1.234MHz   O    good value   auto step delta
   10     16  + 00 1F  1.484MHz   O    good value   auto step delta
   11     16  + 00 32  1.781MHz   O    good value   auto step delta
   12     16  + 01 04  2.125MHz   O    good value   auto step delta
   13     16  + 01 11  2.531MHz   O    good value   auto step delta
   14     16  + 01 21  3.031MHz   O    good value   auto step delta
   15     16  + 01 34  3.625MHz   O    good value   auto step delta
   16     16  + 02 05  4.312MHz   O    good value   auto step delta
   17     16  + 02 13  5.188MHz   O    good value   auto step delta
   18     16  + 02 23  6.188MHz   O    good value   auto step delta
   19     16  + 02 37  7.438MHz   O    good value   auto step delta
   20     16  + 03 07  8.875MHz   O    good value   auto step delta
   21     16  + 03 15  10.62MHz   O    good value   auto step delta
   22     16  + 03 1E  11.75MHz  {O}   good value   auto step delta
   23     64  + 02 3E  7.875MHz   O    good value   auto power initial
   24     64  + 03 0E  9.750MHz   O    good value   auto power delta
   25     64  + 03 16  10.75MHz   O    good value   auto power delta
   26     64  + 03 1A  11.25MHz   O    good value   auto power delta
   27     64  + 03 1C  11.50MHz   O    good value   auto power delta
   28     64  + 03 1D  11.62MHz   O    good value   auto power delta
   29     64  + 03 1D  11.62MHz   O    good value   auto power delta
   30     64  + 03 13  10.38MHz  {O}   good value   auto margin initial

The first internal/external clock test resuts are:
The expect frequency was 500000Hz.
The actual frequency was 499872Hz.
The delta frequency was 128Hz.

The second internal/external clock test resuts are:
The expect frequency was 570312Hz.
The actual frequency was 569976Hz.
The delta frequency was 336Hz.

In the scan-path tests:
The test length was 2048 bits.
The JTAG IR length was 4 bits.
The JTAG DR length was 1 bits.

The IR/DR scan-path tests used 30 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 11.75MHz as the highest frequency.
The IR/DR scan-path tests used 10.38MHz as the final frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

The frequency of the JTAG TCLKR input is measured as 10.37MHz.

The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
The target system likely uses the TCLKO output from the emulator PLL.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 4 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

Hi Praveen,

Thanks for checking. I don't have any spare around but I will get another one and try it again.