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AM6442: EtherCAT master cant be able to connect slave device

Part Number: AM6442
Other Parts Discussed in Thread: DP83869

Tool/software:

sdk 9.2, Debian docker system, IGH Ethercat protocol

 root@am64xx-evm:/home/ethercat/examples/user# uname -a
Linux am64xx-evm 6.1.80-k3 #1 SMP PREEMPT Thu Mar 21 15:44:28 UTC 2024 aarch64 GNU/Linux
root@am64xx-evm:/home/ethercat/examples/user#

AM243 slave is connected to am6442:

------------------------------

root@am64xx-evm:/home/ethercat/examples/user# uname -a
Linux am64xx-evm 6.1.80-k3 #1 SMP PREEMPT Thu Mar 21 15:44:28 UTC 2024 aarch64 GNU/Linux
structm64xx-evm:/home/ethercat/examples/user# /usr/local/bin/ethercat/ethercat c
/* Master 0, Slave 0, "TI EtherCAT Toolkit for AM243X.R5F"
* Vendor ID: 0xe000059d
* Product code: 0x54490025
* Revision number: 0x00010000
*/

ec_pdo_entry_info_t slave_0_pdo_entries[] = {
{0x2000, 0x02, 8},
{0x2000, 0x03, 8},
{0x2000, 0x04, 16},
{0x2000, 0x01, 32},
{0x2002, 0x02, 8},
{0x2002, 0x04, 16},
{0x2002, 0x03, 8},
{0x2002, 0x01, 32},
};

ec_pdo_info_t slave_0_pdos[] = {
{0x1600, 3, slave_0_pdo_entries + 0},
{0x1601, 1, slave_0_pdo_entries + 3},
{0x1a00, 3, slave_0_pdo_entries + 4},
{0x1a01, 1, slave_0_pdo_entries + 7},
};

ec_sync_info_t slave_0_syncs[] = {
{0, EC_DIR_OUTPUT, 0, NULL, EC_WD_DISABLE},
{1, EC_DIR_INPUT, 0, NULL, EC_WD_DISABLE},
{2, EC_DIR_OUTPUT, 2, slave_0_pdos + 0, EC_WD_ENABLE},
{3, EC_DIR_INPUT, 2, slave_0_pdos + 2, EC_WD_DISABLE},
{0xff}
};

---------------------------------------

modify main.c in ethercat/example/user/main.c

----------------------------------

/*****************************************************************************
*
* Copyright (C) 2007-2009 Florian Pose, Ingenieurgemeinschaft IgH
*
* This file is part of the IgH EtherCAT Master.
*
* The IgH EtherCAT Master is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
* The IgH EtherCAT Master is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
* Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with the IgH EtherCAT Master; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
****************************************************************************/

#include <errno.h>
#include <signal.h>
#include <stdio.h>
#include <string.h>
#include <sys/resource.h>
#include <sys/time.h>
#include <sys/types.h>
#include <unistd.h>
#include <time.h> /* clock_gettime() */
#include <sys/mman.h> /* mlockall() */
#include <sched.h> /* sched_setscheduler() */

/****************************************************************************/

#include "ecrt.h"

/****************************************************************************/

/** Task period in ns. */
#define PERIOD_NS (1000000)

#define MAX_SAFE_STACK (8 * 1024) /* The maximum stack size which is
guranteed safe to access without
faulting */

/****************************************************************************/

/* Constants */
#define NSEC_PER_SEC (1000000000)
#define FREQUENCY (NSEC_PER_SEC / PERIOD_NS)

/****************************************************************************/
#define TEST 0, 0
#define AM243X 0xe000059d, 0x54490025

static unsigned int led;

const static ec_pdo_entry_reg_t domain1_regs[] = {
{TEST,AM243X,0x2000,0x02, &led}
};

ec_pdo_entry_info_t slave_0_pdo_entries[] = {
{0x2000, 0x02, 8},
{0x2000, 0x03, 8},
{0x2000, 0x04, 16},
{0x2000, 0x01, 32},
{0x2002, 0x02, 8},
{0x2002, 0x04, 16},
{0x2002, 0x03, 8},
{0x2002, 0x01, 32},
};

ec_pdo_info_t slave_0_pdos[] = {
{0x1600, 3, slave_0_pdo_entries + 0},
{0x1601, 1, slave_0_pdo_entries + 3},
{0x1a00, 3, slave_0_pdo_entries + 4},
{0x1a01, 1, slave_0_pdo_entries + 7},
};

ec_sync_info_t slave_0_syncs[] = {
{0, EC_DIR_OUTPUT, 0, NULL, EC_WD_DISABLE},
{1, EC_DIR_INPUT, 0, NULL, EC_WD_DISABLE},
{2, EC_DIR_OUTPUT, 2, slave_0_pdos + 0, EC_WD_ENABLE},
{3, EC_DIR_INPUT, 2, slave_0_pdos + 2, EC_WD_DISABLE},
{0xff}
};

// EtherCAT
static ec_master_t *master = NULL;
static ec_master_state_t master_state = {};

static ec_domain_t *domain1 = NULL;
static ec_domain_state_t domain1_state = {};

static ec_slave_config_t *sc_ana_in = NULL;
static ec_slave_config_state_t sc_ana_in_state = {};

/****************************************************************************/

// process data
static uint8_t *domain1_pd = NULL;

#define BusCouplerPos 0, 0
#define DigOutSlavePos 0, 2
#define AnaInSlavePos 0, 3
#define AnaOutSlavePos 0, 4

#define Beckhoff_EK1100 0x00000002, 0x044c2c52
#define Beckhoff_EL2004 0x00000002, 0x07d43052
#define Beckhoff_EL2032 0x00000002, 0x07f03052
#define Beckhoff_EL3152 0x00000002, 0x0c503052
#define Beckhoff_EL3102 0x00000002, 0x0c1e3052
#define Beckhoff_EL4102 0x00000002, 0x10063052

// offsets for PDO entries
static unsigned int off_ana_in_status;
static unsigned int off_ana_in_value;
static unsigned int off_ana_out;
static unsigned int off_dig_out;

/*const static ec_pdo_entry_reg_t domain1_regs[] = {
{AnaInSlavePos, Beckhoff_EL3102, 0x3101, 1, &off_ana_in_status},
{AnaInSlavePos, Beckhoff_EL3102, 0x3101, 2, &off_ana_in_value},
{AnaOutSlavePos, Beckhoff_EL4102, 0x3001, 1, &off_ana_out},
{DigOutSlavePos, Beckhoff_EL2032, 0x3001, 1, &off_dig_out},
{}
};*/

static unsigned int counter = 0;
static unsigned int blink = 0;

/****************************************************************************/

// Analog in --------------------------

static const ec_pdo_entry_info_t el3102_pdo_entries[] = {
{0x3101, 1, 8}, // channel 1 status
{0x3101, 2, 16}, // channel 1 value
{0x3102, 1, 8}, // channel 2 status
{0x3102, 2, 16}, // channel 2 value
{0x6401, 1, 16}, // channel 1 value (alt.)
{0x6401, 2, 16} // channel 2 value (alt.)
};

static const ec_pdo_info_t el3102_pdos[] = {
{0x1A00, 2, el3102_pdo_entries},
{0x1A01, 2, el3102_pdo_entries + 2}
};

static const ec_sync_info_t el3102_syncs[] = {
{2, EC_DIR_OUTPUT},
{3, EC_DIR_INPUT, 2, el3102_pdos},
{0xff}
};

// Analog out -------------------------

static const ec_pdo_entry_info_t el4102_pdo_entries[] = {
{0x3001, 1, 16}, // channel 1 value
{0x3002, 1, 16}, // channel 2 value
};

static const ec_pdo_info_t el4102_pdos[] = {
{0x1600, 1, el4102_pdo_entries},
{0x1601, 1, el4102_pdo_entries + 1}
};

static const ec_sync_info_t el4102_syncs[] = {
{2, EC_DIR_OUTPUT, 2, el4102_pdos},
{3, EC_DIR_INPUT},
{0xff}
};

// Digital out ------------------------

static const ec_pdo_entry_info_t el2004_channels[] = {
{0x3001, 1, 1}, // Value 1
{0x3001, 2, 1}, // Value 2
{0x3001, 3, 1}, // Value 3
{0x3001, 4, 1} // Value 4
};

static const ec_pdo_info_t el2004_pdos[] = {
{0x1600, 1, &el2004_channels[0]},
{0x1601, 1, &el2004_channels[1]},
{0x1602, 1, &el2004_channels[2]},
{0x1603, 1, &el2004_channels[3]}
};

static const ec_sync_info_t el2004_syncs[] = {
{0, EC_DIR_OUTPUT, 4, el2004_pdos},
{1, EC_DIR_INPUT},
{0xff}
};

/****************************************************************************/

void check_domain1_state(void)
{
ec_domain_state_t ds;

ecrt_domain_state(domain1, &ds);

if (ds.working_counter != domain1_state.working_counter) {
printf("Domain1: WC %u.\n", ds.working_counter);
}
if (ds.wc_state != domain1_state.wc_state) {
printf("Domain1: State %u.\n", ds.wc_state);
}

domain1_state = ds;
}

/****************************************************************************/

void check_master_state(void)
{
ec_master_state_t ms;

ecrt_master_state(master, &ms);

if (ms.slaves_responding != master_state.slaves_responding) {
printf("%u slave(s).\n", ms.slaves_responding);
}
if (ms.al_states != master_state.al_states) {
printf("AL states: 0x%02X.\n", ms.al_states);
}
if (ms.link_up != master_state.link_up) {
printf("Link is %s.\n", ms.link_up ? "up" : "down");
}

master_state = ms;
}

/****************************************************************************/

void check_slave_config_states(void)
{
ec_slave_config_state_t s;

ecrt_slave_config_state(sc_ana_in, &s);

if (s.al_state != sc_ana_in_state.al_state) {
printf("AnaIn: State 0x%02X.\n", s.al_state);
}
if (s.online != sc_ana_in_state.online) {
printf("AnaIn: %s.\n", s.online ? "online" : "offline");
}
if (s.operational != sc_ana_in_state.operational) {
printf("AnaIn: %soperational.\n", s.operational ? "" : "Not ");
}

sc_ana_in_state = s;
}

/****************************************************************************/

void cyclic_task()
{
// receive process data
ecrt_master_receive(master);
ecrt_domain_process(domain1);

// check process data state
check_domain1_state();

if (counter) {
counter--;
} else { // do this at 1 Hz
counter = FREQUENCY;

// calculate new process data
blink = !blink;

// check for master state (optional)
check_master_state();

// check for slave configuration state(s) (optional)
check_slave_config_states();
}

#if 0
// read process data
printf("AnaIn: state %u value %u\n",
EC_READ_U8(domain1_pd + off_ana_in_status),
EC_READ_U16(domain1_pd + off_ana_in_value));
#endif

#if 1
// write process data
//EC_WRITE_U8(domain1_pd + off_dig_out, blink ? 0x06 : 0x09);
#endif

EC_WRITE_U8(domain1_pd + led, 0xff);

// send process data
ecrt_domain_queue(domain1);
ecrt_master_send(master);
}

/****************************************************************************/

void stack_prefault(void)
{
unsigned char dummy[MAX_SAFE_STACK];

memset(dummy, 0, MAX_SAFE_STACK);
}

/****************************************************************************/

int main(int argc, char **argv)
{
ec_slave_config_t *sc;
struct timespec wakeup_time;
int ret = 0;

master = ecrt_request_master(0);
if (!master) {
return -1;
}

domain1 = ecrt_master_create_domain(master);
if (!domain1) {
return -1;
}

if (!(sc_ana_in = ecrt_master_slave_config(
master, TEST, AM243X))) {
fprintf(stderr, "Failed to get slave configuration.\n");
return -1;
}

printf("Configuring PDOs...\n");
if (ecrt_slave_config_pdos(sc_ana_in, EC_END, slave_0_syncs)) {
fprintf(stderr, "Failed to configure PDOs.\n");
return -1;
}

// Create configuration for bus coupler
sc = ecrt_master_slave_config(master, TEST, AM243X);
if (!sc) {
return -1;
}

if (ecrt_domain_reg_pdo_entry_list(domain1, domain1_regs)) {
fprintf(stderr, "PDO entry registration failed!\n");
return -1;
}

printf("Activating master...\n");
if (ecrt_master_activate(master)) {
return -1;
}

if (!(domain1_pd = ecrt_domain_data(domain1))) {
return -1;
}

/* Set priority */

struct sched_param param = {};
param.sched_priority = sched_get_priority_max(SCHED_FIFO);

printf("Using priority %i.\n", param.sched_priority);
if (sched_setscheduler(0, SCHED_FIFO, &param) == -1) {
perror("sched_setscheduler failed");
}

/* Lock memory */

if (mlockall(MCL_CURRENT | MCL_FUTURE) == -1) {
fprintf(stderr, "Warning: Failed to lock memory: %s\n",
strerror(errno));
}

stack_prefault();

printf("Starting RT task with dt=%u ns.\n", PERIOD_NS);

clock_gettime(CLOCK_MONOTONIC, &wakeup_time);
wakeup_time.tv_sec += 1; /* start in future */
wakeup_time.tv_nsec = 0;

while (1) {
ret = clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME,
&wakeup_time, NULL);
if (ret) {
fprintf(stderr, "clock_nanosleep(): %s\n", strerror(ret));
break;
}

cyclic_task();

wakeup_time.tv_nsec += PERIOD_NS;
while (wakeup_time.tv_nsec >= NSEC_PER_SEC) {
wakeup_time.tv_nsec -= NSEC_PER_SEC;
wakeup_time.tv_sec++;
}
}

return ret;
}

----------------------------------------

the dmesg log is here:

---------------------------------------

root@am64xx-evm:/home/ethercat/examples/user# dmesg | grep Ether
[ 256.393064] EtherCAT: Master driver 1.6.4 1.6.4
[ 256.398279] EtherCAT: 1 master waiting for devices.
[ 277.205722] ec_generic: EtherCAT master generic Ethernet device module 1.6.4 1.6.4
[ 277.213500] EtherCAT: Accepting 1C:63:49:1A:DA:1A as main device for master 0.
[ 277.238903] EtherCAT 0: Starting EtherCAT-IDLE thread.
[ 318.010872] EtherCAT 0: Link state of ecm0 changed to UP.
[ 318.047016] EtherCAT 0: 1 slave(s) responding on main device. Re-scanning on next possibility.
[ 318.058037] EtherCAT 0: Slave states on main device: INIT.
[ 318.064691] EtherCAT 0: Re-scanning now.
[ 318.069846] EtherCAT 0: Scanning bus.
[ 319.024005] EtherCAT 0: Bus scanning completed in 956 ms.
[ 319.031096] EtherCAT 0: Using slave 0 as DC reference clock.
[ 319.042991] EtherCAT ERROR 0: Failed to calculate bus topology.
[ 319.049060] EtherCAT 0: Starting EoE thread.
[ 319.063069] EtherCAT 0: Slave states on main device: PREOP.
[ 322.175194] EtherCAT ERROR 0-0: Mailbox error response received - Unknown error reply code 0x0000.
[ 322.182863] EtherCAT WARNING 0: 1 datagram TIMED OUT!
[ 322.184308] EtherCAT WARNING 0-0: Invalid mailbox response for eoe0s0.
[ 322.211189] EtherCAT ERROR 0-0: Mailbox error response received - Unknown error reply code 0x0000.
[ 322.220825] EtherCAT WARNING 0-0: Invalid mailbox response for eoe0s0.
[ 322.323196] EtherCAT ERROR 0-0: Mailbox error response received - Unknown error reply code 0x0000.
[ 322.332956] EtherCAT WARNING 0-0: Invalid mailbox response for eoe0s0.
[ 322.355148] EtherCAT ERROR 0-0: Mailbox error response received - Unknown error reply code 0x0000.
[ 322.364923] EtherCAT WARNING 0-0: Invalid mailbox response for eoe0s0.
[ 322.403091] EtherCAT ERROR 0-0: Mailbox error response received - Unknown error reply code 0x0000.
[ 322.413245] EtherCAT WARNING 0-0: Invalid mailbox response for eoe0s0.
[ 322.419896] EtherCAT ERROR 0-0: Reception of CoE SDO description response failed: No response.
root@am64xx-evm:/home/ethercat/examples/user#

-----------------------------

what's wrong here?

Thanks

   Semon

  • Hi Semon Zhang,

    I would like to know some additional information on the AM243x EtherCAT SubDevice at first.
    1. Have tried connecting AM243x EtherCAT SubDevice to TwinCAT or Conformance Test Tool (CTT)? Able to scan in TwinCAT and connect?
    2. Which EtherCAT SubDevice example have been flashed onto AM243x target?
    3. Found any error messages in the debug log on the AM243x target?

    Kind Regards,

  • 1. Have tried connecting AM243x EtherCAT SubDevice to TwinCAT or Conformance Test Tool (CTT)? Able to scan in TwinCAT and connect?
    2. Which EtherCAT SubDevice example have been flashed onto AM243x target?
    3. Found any error messages in the debug log on the AM243x target?

    Hi Harsha

         I use this Example:

          /home/semon/am243/ind_comms_sdk_am243x_09_02_00_24/examples/industrial_comms/ethercat_slave_demo/device_profiles/401_simple/am243x-lp/r5fss0-0_freertos/ti-arm-clang/ethercat_slave_simple_demo.release.appimage.hs_fs

        here is the AM243X log:

         ------------------------------------------

    DMSC Firmware Version 9.2.7--v09.02.07 (Kool Koala)
    DMSC Firmware revision 0x9
    DMSC ABI revision 3.1

    [BOOTLOADER_PROFILE] Boot Media : NOR SPI FLASH
    KPI_DATA: [BOOTLOADER_PROFILE] Boot Media Clock : 100.000 MHz
    KPI_DATA: [BOOTLOADER_PROFILE] Boot Image Size : 275 KB
    [BOOTLOADER_PROFILE] Cores present :
    r5f0-0
    KPI_DATA: [BOOTLOADER PROFILE] SYSFW init : 11797us
    KPI_DATA: [BOOTLOADER PROFILE] System_init : 13319us
    KPI_DATA: [BOOTLOADER PROFILE] Drivers_open : 283us
    KPI_DATA: [BOOTLOADER PROFILE] Board_driversOpen : 133146us
    KPI_DATA: [BOOTLOADER PROFILE] Sciclient Get Version : 9848us
    KPI_DATA: [BOOTLOADER PROFILE] CPU load : 34498us
    KPI_DATA: [BOOTLOADER_PROFILE] SBL Total Time Taken : 202895us

    Image loading done, switching to application ...

    Local Implementation
    Pruicss max =3 selected PRU:3
    Phy Reset: 0.28
    Phy Reset: 0.20
    pRegPerm = 0x30082000, dram1=0x30082000, offset = 0x00000000, size = 0x00001400
    PRU ESC: Rev 0690 | Bld 0532 | INTC base: 0x300a0000 , id = 0x4e82a900
    INTC.HIDISR addr: 0x300a0038
    RxPDO created 0x1600: 0x7013b860
    RxPDO created 0x1601: 0x7013b968
    TxPDO created 0x1A00: 0x7013ba00
    TxPDO created 0x1A01: 0x7013bb08
    EC_SLV_APP_SS_populateDescriptionObjectValues:1650 PDO Out Len: 0x40
    Phy Reset: 0.28
    Phy Reset: 0.20
    Phy UnReset: 0.28
    Phy UnReset: 0.20
    Configure Phy bits: PhyAddr:3, LinPol:HIGH, PhyAddr:15, LinPol:HIGH, (0x0)
    DP83869 detected
    DP83869 detected
    PRU_PHY_detect:160 Phy 3 alive
    PRU_PHY_detect:160 Phy 15 alive
    Phy 3 : Disable RGMII mode
    Phy 3 : Disable GBit ANEG
    Phy 15 : Disable RGMII mode
    Phy 15 : Disable GBit ANEG
    PHY Disable Magnetics
    PHY Enable Magnetics
    TI EtherCAT Toolkit for AM243X.R5F - e000059dh / 54490025h
    Explicit Device ID : 0x 5

    ****EC Slave*********************************************************
    Numeric Version: 0x00020005
    Source Id: <00418212cbc503521f58f7b42f61b68417c05ab7>
    ****HWAL*************************************************************
    Numeric Version: 0x00020003
    Friendly Version: <KB HWAL v00.02.00.03>
    Source Id: <1f04544766fd96127082c96057077a930b964c39>
    ****OSAL*************************************************************
    Numeric Version: 0x00010202
    Friendly Version: <KB OSAL v00.01.02.02>
    Source Id: <5e1ebb0ccfdbbbe7667ebf41c1452faab7e5228b>
    *********************************************************************
    State change: 0x0 -> 0x1
    SSC_checkTimer:MaxD:9342685 (9)
    SSC_checkTimer:MaxET:7
    SSC_checkTimer:MaxD:11999615 (11)
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x1
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x1
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x12
    State change: 0x12 -> 0x2

    --------------------------------------------

    and AM6442 LInux log is here:

    =========================

    [ 3124.158750] EtherCAT 0-0: Acknowledged state PREOP.
    [ 3125.085033] EtherCAT 0: Releasing master...
    [ 3125.089348] EtherCAT 0: Master thread exited.
    [ 3125.093729] EtherCAT 0: Stopping EoE thread.
    [ 3125.098063] EtherCAT 0: EoE thread exited.
    [ 3125.102220] EtherCAT 0: Starting EoE thread.
    [ 3125.106835] EtherCAT 0: Starting EtherCAT-IDLE thread.
    [ 3125.112216] EtherCAT 0: Released.
    [ 3125.134758] EtherCAT 0: Slave states on main device: OP.
    [ 3166.906738] EtherCAT WARNING 0: 1 datagram TIMED OUT!
    [ 3166.911837] EtherCAT WARNING 0-0: Failed to receive mbox check datagram for eoe0s0.
    [ 3166.934730] EtherCAT WARNING 0-0: Failed to receive mbox check datagram for eoe0s0.
    [ 3166.934730] EtherCAT 0: 0 slave(s) responding on main device. Re-scanning on next possibility.
    [ 3166.934749] EtherCAT 0: Re-scanning now.
    [ 3166.934753] EtherCAT 0: Stopping EoE thread.
    [ 3166.954741] EtherCAT WARNING 0-0: Failed to receive mbox check datagram for eoe0s0.
    [ 3166.966938] EtherCAT 0: EoE thread exited.
    [ 3167.347742] am65-cpsw-nuss 8000000.ethernet eth0: Link is Down
    [ 3167.353652] EtherCAT 0: Link state of ecm0 changed to [ 3268.958761] EtherCAT WARNING 0: 8 datagrams UNMATCHED!
    DOWN.
    [ 3204.219446] EtherCAT 0: Link state of ecm0 changed to UP.
    [ 3204.221040] am65-cpsw-nuss 8000000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off
    [ 3204.230848] EtherCAT WARNING 0: 52 datagrams TIMED OUT!
    [ 3204.246910] EtherCAT 0: 1 slave(s) responding on main device. Re-scanning on next possibility.
    [ 3204.262851] EtherCAT 0: Slave states on main device: INIT.
    [ 3204.270496] EtherCAT 0: Re-scanning now.
    [ 3204.279133] EtherCAT 0: Scanning bus.
    [ 3205.244613] EtherCAT 0: Bus scanning completed in 968 ms.
    [ 3205.250171] EtherCAT 0: Using slave 0 as DC reference clock.
    [ 3205.259213] EtherCAT ERROR 0: Failed to calculate bus topology.
    [ 3205.269098] EtherCAT 0: Starting EoE thread.
    [ 3205.282901] EtherCAT 0: Slave states on main device: PREOP.
    [ 3208.848901] EtherCAT ERROR 0-0: Mailbox error response received - Unknown error reply code 0x0000.
    [ 3208.859282] EtherCAT WARNING 0-0: Invalid mailbox response for eoe0s0.
    [ 3208.879048] EtherCAT ERROR 0-0: Mailbox error response received - Unknown error reply code 0x0000.
    [ 3208.889033] EtherCAT WARNING 0-0: Invalid mailbox response for eoe0s0.
    [ 3208.894724] EtherCAT WARNING 0: 1 datagram TIMED OUT!
    [ 3208.900641] EtherCAT WARNING 0: 1 datagram UNMATCHED!
    [ 3208.906440] EtherCAT ERROR 0-0: Mailbox error response received - Unknown error reply code 0x0000.
    [ 3208.916335] EtherCAT WARNING 0-0: Invalid mailbox response for eoe0s0.
    [ 3208.979336] EtherCAT WARNING 0-0: Other mailbox protocol response for eoe0s0.
    [ 3209.974744] EtherCAT ERROR 0-0: Timeout while waiting for SDO entry 0x1c32:8 description response.
    [ 3236.816534] EtherCAT: Requesting master 0...
    [ 3236.820933] EtherCAT: Successfully requested master 0.
    [ 3236.826799] EtherCAT 0: Domain0: Logical address 0x00000000, 8 byte, expected working counter 1.
    [ 3236.837390] EtherCAT 0: Datagram domain0-0-main: Logical offset 0x00000000, 8 byte, type LWR.
    [ 3236.848136] EtherCAT 0: Master thread exited.
    [ 3236.852600] EtherCAT 0: Stopping EoE thread.
    [ 3236.857051] EtherCAT 0: EoE thread exited.
    [ 3236.861210] EtherCAT 0: Starting EoE thread.
    [ 3236.865784] EtherCAT 0: Starting EtherCAT-OP thread.
    [ 3236.871115] EtherCAT WARNING 0: 1 datagram TIMED OUT!
    [ 3236.876240] EtherCAT WARNING 0: 2 datagrams UNMATCHED!
    [ 3236.881600] EtherCAT WARNING 0: No application time received up to now, but master already active.
    [ 3237.106862] EtherCAT WARNING 0-0: Other mailbox protocol response for eoe0s0.
    [ 3237.114170] EtherCAT ERROR 0-0: Reception of CoE download response failed: No response.
    [ 3237.122228] EtherCAT WARNING 0-0: Failed to clear PDO mapping.
    [ 3237.128078] EtherCAT WARNING 0-0: Currently mapped PDO entries: 0x2000:02/8 0x2000:03/8 0x2000:04/16. Entries to map: 0x2000:02/8 0x2000:03/8 0x2000:04/16
    [ 3237.141966] EtherCAT WARNING 0-0: Failed to configure mapping of PDO 0x1600.
    [ 3237.166943] EtherCAT ERROR 0-0: Mailbox error response received - Unknown error reply code 0x0000.
    [ 3237.177426] EtherCAT WARNING 0-0: Invalid mailbox response for eoe0s0.
    [ 3237.184861] EtherCAT ERROR 0-0: Reception of CoE download response failed: No response.
    [ 3237.193237] EtherCAT WARNING 0-0: Failed to clear PDO mapping.
    [ 3237.199302] EtherCAT WARNING 0-0: Currently mapped PDO entries: 0x2002:02/8 0x2002:04/16 0x2002:03/8. Entries to map: 0x2002:02/8 0x2002:04/16 0x2002:03/8
    [ 3237.213765] EtherCAT WARNING 0-0: Failed to configure mapping of PDO 0x1A00.
    [ 3237.243742] EtherCAT ERROR 0-0: Failed to set SAFEOP state, slave refused state change (PREOP + ERROR).
    [ 3237.254767] Et[ 3269.274724] EtherCAT WARNING: Datagram 000000003073d9d9 (domain0-0-main) was SKIPPED 17 times.
    herCAT ERROR 0-0: AL status message 0x001E: "Invalid input configuration".
    [ 3237.266772] EtherCAT 0-0: Acknowledged state PREOP.
    [ 3237.870782] EtherCAT WARNING 0: 2 datagrams TIMED OUT!
    [ 3237.876046] EtherCAT WARNING 0: 57 datagrams UNMATCHED!
    [ 3238.150727] EtherCAT WARNING: Datagram 000000003073d9d9 (domain0-0-main) was SKIPPED 63 times.
    [ 3238.870728] EtherCAT WARNING 0: 9 datagrams UNMATCHED!
    [ 3239.154722] EtherCAT WARNING: Datagram 000000003073d9d9 (domain0-0-main) was SKIPPED 9 times.
    [ 3239.874795] EtherCAT WARNING 0: 11 datagrams UNMATCHED!
    [ 3240.158724] EtherCAT WARNING: Datagram 000000003073d9d9 (domain0-0-main) was SKIPPED 11 times.
    [ 3240.878728] EtherCAT WARNING 0: 11 datagrams UNMATCHED!
    [ 3241.162722] EtherCAT WARNING: Datagram 000000003073d9d9 (domain0-0-main) was SKIPPED 11 times

    -------------------------------------

        

    Regards

       Semon

  • Hello Semon Zhang,

    Thanks for the logs. I see no error message in the log from AM243x target running EtherCAT SubDevice. But there are some error messages in the EtherCAT MainDevice log. May be this is due to invalid SM configurations.

    I will forward this ticket to the concerned team for further support.

    Kind Regards,

  • Hello Semon, 

    Just to clarify, do you only have in your EtherCAT network, AM64x EVM (EtherCAT Master/MainDevice) connected to just one AM243x EVM (EtherCAT SubDevice)? Or do you have other EtherCAT SubDevices in your network (I noticed there were Beckhoff devices also defined in your main.c file).

    Are you testing on a TI AM64x EVM or a custom built AM64x EVM?

    -Daolin

  • Just to clarify, do you only have in your EtherCAT network, AM64x EVM (EtherCAT Master/MainDevice) connected to just one AM243x EVM (EtherCAT SubDevice)? Or do you have other EtherCAT SubDevices in your network (I noticed there were Beckhoff devices also defined in your main.c file).

    Are you testing on a TI AM64x EVM or a custom built AM64x EVM?

    Hi Daolin

        there is just one AM243x connected to AM6442, I just created the main.c file based on the example to add am243x and not delete the other device completely.

       I am testing on AM6442 EVM board, for customer is using this chipset to development their Ethercat system

    Regards

       Semon

  • Hi Semon,

    Please note that I am not an expert in the IgH EtherCAT master and since it is a 3rd party open-source stack, I will only be able to offer suggestions, but not all suggestions would be fully tested.

    there is just one AM243x connected to AM6442, I just created the main.c file based on the example to add am243x and not delete the other device completely.

    Is it possible for you to try removing the other devices and keep just the AM243x configuration? I'm not entirely sure if this is the case but I think having the other devices in your main.c might be related to the "EtherCAT ERROR 0: Failed to calculate bus topology" error. 

    -Daolin

  • Is it possible for you to try removing the other devices and keep just the AM243x configuration? I'm not entirely sure if this is the case but I think having the other devices in your main.c might be related to the "EtherCAT ERROR 0: Failed to calculate bus topology" error. 

    Hi Daolin

         I have also tried to remove all unused devices, it failed yet, see the attached file used in my test.

         

    /*****************************************************************************
     *
     *  Copyright (C) 2007-2009  Florian Pose, Ingenieurgemeinschaft IgH
     *
     *  This file is part of the IgH EtherCAT Master.
     *
     *  The IgH EtherCAT Master is free software; you can redistribute it and/or
     *  modify it under the terms of the GNU General Public License version 2, as
     *  published by the Free Software Foundation.
     *
     *  The IgH EtherCAT Master is distributed in the hope that it will be useful,
     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
     *  Public License for more details.
     *
     *  You should have received a copy of the GNU General Public License along
     *  with the IgH EtherCAT Master; if not, write to the Free Software
     *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
     *
     ****************************************************************************/
    
    #include <errno.h>
    #include <signal.h>
    #include <stdio.h>
    #include <string.h>
    #include <sys/resource.h>
    #include <sys/time.h>
    #include <sys/types.h>
    #include <unistd.h>
    #include <time.h> /* clock_gettime() */
    #include <sys/mman.h> /* mlockall() */
    #include <sched.h> /* sched_setscheduler() */
    
    /****************************************************************************/
    
    #include "ecrt.h"
    
    /****************************************************************************/
    
    /** Task period in ns. */
    #define PERIOD_NS   (1000000)
    
    #define MAX_SAFE_STACK (8 * 1024) /* The maximum stack size which is
                                         guranteed safe to access without
                                         faulting */
    
    /****************************************************************************/
    
    /* Constants */
    #define NSEC_PER_SEC (1000000000)
    #define FREQUENCY (NSEC_PER_SEC / PERIOD_NS)
    
    /****************************************************************************/
    
    // EtherCAT
    static ec_master_t *master = NULL;
    static ec_master_state_t master_state = {};
    
    static ec_domain_t *domain1 = NULL;
    static ec_domain_state_t domain1_state = {};
    
    static ec_slave_config_t *sc_ana_in = NULL;
    static ec_slave_config_state_t sc_ana_in_state = {};
    
    /****************************************************************************/
    
    // process data
    static uint8_t *domain1_pd = NULL;
    
    #define TEST  0, 0
    #define AM243X 0xe000059d, 0x54490025
    
    // offsets for PDO entries
    static unsigned int led;
    static unsigned int counter = 0;
    static unsigned int blink = 0;
    
    const static ec_pdo_entry_reg_t domain1_regs[] = {
        {TEST,AM243X,0x2000,0x02, &led}
    };
    
    
    
    /****************************************************************************/
    
    /* Master 0, Slave 0, "TI EtherCAT Toolkit for AM243X.R5F"                                   
     * Vendor ID:       0xe000059d                                                               
     * Product code:    0x54490025                                                               
     * Revision number: 0x00010000                                                               
     */                                                                                          
                                                                                                 
    ec_pdo_entry_info_t slave_0_pdo_entries[] = {                                                
        {0x2000, 0x02, 8}, /* i2c-leds */                                                        
        {0x2000, 0x03, 8}, /* SubIndex 3 */                                                      
        {0x2000, 0x04, 16}, /* SubIndex 4 */                                                     
        {0x2000, 0x01, 32}, /* SubIndex 1 */                                                     
        {0x2002, 0x02, 8}, /* SubIndex 2 */                                                      
        {0x2002, 0x04, 16}, /* SubIndex 4 */                                                     
        {0x2002, 0x03, 8}, /* SubIndex 3 */                                                      
        {0x2002, 0x01, 32}, /* SubIndex 1 */                                                     
    };                                                                                           
                                                                                                 
    ec_pdo_info_t slave_0_pdos[] = {                                                             
        {0x1600, 3, slave_0_pdo_entries + 0}, /* RxPDO */                                        
        {0x1601, 1, slave_0_pdo_entries + 3}, /* RxPDO2 */                                       
        {0x1a00, 3, slave_0_pdo_entries + 4}, /* TxPDO */                                        
        {0x1a01, 1, slave_0_pdo_entries + 7}, /* TxPDO2 */                                       
    };                                                                                           
                                                                                                 
    ec_sync_info_t slave_0_syncs[] = {                                                           
        {0, EC_DIR_OUTPUT, 0, NULL, EC_WD_DISABLE},                                              
        {1, EC_DIR_INPUT, 0, NULL, EC_WD_DISABLE},                                               
        {2, EC_DIR_OUTPUT, 2, slave_0_pdos + 0, EC_WD_ENABLE},                                   
        {3, EC_DIR_INPUT, 2, slave_0_pdos + 2, EC_WD_DISABLE},                                   
        {0xff}                                                                                   
    }; 
    
    /****************************************************************************/
    
    void check_domain1_state(void)
    {
        ec_domain_state_t ds;
    
        ecrt_domain_state(domain1, &ds);
    
        if (ds.working_counter != domain1_state.working_counter) {
            printf("Domain1: WC %u.\n", ds.working_counter);
        }
        if (ds.wc_state != domain1_state.wc_state) {
            printf("Domain1: State %u.\n", ds.wc_state);
        }
    
        domain1_state = ds;
    }
    
    /****************************************************************************/
    
    void check_master_state(void)
    {
        ec_master_state_t ms;
    
        ecrt_master_state(master, &ms);
    
        if (ms.slaves_responding != master_state.slaves_responding) {
            printf("%u slave(s).\n", ms.slaves_responding);
        }
        if (ms.al_states != master_state.al_states) {
            printf("AL states: 0x%02X.\n", ms.al_states);
        }
        if (ms.link_up != master_state.link_up) {
            printf("Link is %s.\n", ms.link_up ? "up" : "down");
        }
    
        master_state = ms;
    }
    
    /****************************************************************************/
    
    void check_slave_config_states(void)
    {
        ec_slave_config_state_t s;
    
        ecrt_slave_config_state(sc_ana_in, &s);
    
        if (s.al_state != sc_ana_in_state.al_state) {
            printf("AnaIn: State 0x%02X.\n", s.al_state);
        }
        if (s.online != sc_ana_in_state.online) {
            printf("AnaIn: %s.\n", s.online ? "online" : "offline");
        }
        if (s.operational != sc_ana_in_state.operational) {
            printf("AnaIn: %soperational.\n", s.operational ? "" : "Not ");
        }
    
        sc_ana_in_state = s;
    }
    
    /****************************************************************************/
    
    void cyclic_task()
    {
        // receive process data
        ecrt_master_receive(master);
        ecrt_domain_process(domain1);
    
        // check process data state
        check_domain1_state();
    
        if (counter) {
            counter--;
        } else { // do this at 1 Hz
            counter = FREQUENCY;
    
            // check for master state (optional)
            check_master_state();
    
            // check for slave configuration state(s) (optional)
            check_slave_config_states();
        }
    
        // write process data
        //EC_WRITE_U8(domain1_pd + led, 0xff);
        EC_WRITE_U8(domain1_pd + led, 0x7);
        //EC_WRITE_U8(domain1_pd + led, 0x3);
        //EC_WRITE_U8(domain1_pd + led, 0x1);
        //EC_WRITE_U8(domain1_pd + led, 0x0);
        
        
    
        // send process data
        ecrt_domain_queue(domain1);
        ecrt_master_send(master);
    }
    
    /****************************************************************************/
    
    void stack_prefault(void)
    {
        unsigned char dummy[MAX_SAFE_STACK];
    
        memset(dummy, 0, MAX_SAFE_STACK);
    }
    
    /****************************************************************************/
    
    int main(int argc, char **argv)
    {
        ec_slave_config_t *sc;
        struct timespec wakeup_time;
        int ret = 0;
    
        master = ecrt_request_master(0);
        if (!master) {
            return -1;
        }
    
        domain1 = ecrt_master_create_domain(master);
        if (!domain1) {
            return -1;
        }
    
        if (!(sc_ana_in = ecrt_master_slave_config(
                        master, TEST, AM243X))) {
            fprintf(stderr, "Failed to get slave configuration.\n");
            return -1;
        }
    
        printf("Configuring PDOs...\n");
        if (ecrt_slave_config_pdos(sc_ana_in, EC_END, slave_0_syncs)) {
            fprintf(stderr, "Failed to configure PDOs.\n");
            return -1;
        }
    
    
        if (ecrt_domain_reg_pdo_entry_list(domain1, domain1_regs)) {
            fprintf(stderr, "PDO entry registration failed!\n");
            return -1;
        }
    
        printf("Activating master...\n");
        if (ecrt_master_activate(master)) {
            return -1;
        }
    
        if (!(domain1_pd = ecrt_domain_data(domain1))) {
            return -1;
        }
    
        /* Set priority */
    
        struct sched_param param = {};
        param.sched_priority = sched_get_priority_max(SCHED_FIFO);
    
        printf("Using priority %i.\n", param.sched_priority);
        if (sched_setscheduler(0, SCHED_FIFO, &param) == -1) {
            perror("sched_setscheduler failed");
        }
    
        /* Lock memory */
    
        if (mlockall(MCL_CURRENT | MCL_FUTURE) == -1) {
            fprintf(stderr, "Warning: Failed to lock memory: %s\n",
                    strerror(errno));
        }
    
        stack_prefault();
    
        printf("Starting RT task with dt=%u ns.\n", PERIOD_NS);
    
        clock_gettime(CLOCK_MONOTONIC, &wakeup_time);
        wakeup_time.tv_sec += 1; /* start in future */
        wakeup_time.tv_nsec = 0;
    
        while (1){
            ret = clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME,
                    &wakeup_time, NULL);
            if (ret) {
                fprintf(stderr, "clock_nanosleep(): %s\n", strerror(ret));
                break;
            }
            cyclic_task();
    
            wakeup_time.tv_nsec += PERIOD_NS;
            while (wakeup_time.tv_nsec >= NSEC_PER_SEC) {
                wakeup_time.tv_nsec -= NSEC_PER_SEC;
                wakeup_time.tv_sec++;
            }
        }
    
        return ret;
    }
    
    /****************************************************************************/
    

        is there any file you can share that is ok for the test?

    Thanks

       Semon

  • Hi Semon,

    Was the failure the same "EtherCAT ERROR 0: Failed to calculate bus topology" error?

    The following main file was what I last was able to get working with the generic IgH EtherCAT master stack running on AM62x EVM as EtherCAT master/maindevice connected to a single AM64x EVM as the EtherCAT slave/subdevice.

    Please note, I haven't tested this again in a long time and I'm not positive it will work for you but feel free to give it a try.

    Also, from what I remember, I had to use this version of the main file, which I modified from ethercat/examples/dc_user/main.c because it seems like in my original setup, the AM64x EVM EtherCAT slave/subdevice required the ecrt_master_application_time function to run, otherwise the EtherCAT master will not receive any response from the EtherCAT subdevice.

    mainv4_dc.c 

    /*****************************************************************************
     *
     *  $Id$
     *
     *  Copyright (C) 2007-2009  Florian Pose, Ingenieurgemeinschaft IgH
     *
     *  This file is part of the IgH EtherCAT Master.
     *
     *  The IgH EtherCAT Master is free software; you can redistribute it and/or
     *  modify it under the terms of the GNU General Public License version 2, as
     *  published by the Free Software Foundation.
     *
     *  The IgH EtherCAT Master is distributed in the hope that it will be useful,
     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
     *  Public License for more details.
     *
     *  You should have received a copy of the GNU General Public License along
     *  with the IgH EtherCAT Master; if not, write to the Free Software
     *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
     *
     *  ---
     *
     *  The license mentioned above concerns the source code only. Using the
     *  EtherCAT technology and brand is only permitted in compliance with the
     *  industrial property and similar rights of Beckhoff Automation GmbH.
     *
     ****************************************************************************/
    
    #include <errno.h>
    #include <signal.h>
    #include <stdio.h>
    #include <string.h>
    #include <sys/resource.h>
    #include <sys/time.h>
    #include <sys/types.h>
    #include <unistd.h>
    #include <time.h>
    #include <sys/mman.h>
    #include <malloc.h>
    
    /****************************************************************************/
    
    #include "ecrt.h"
    
    /****************************************************************************/
    
    // Application parameters
    #define FREQUENCY 1000
    #define CLOCK_TO_USE CLOCK_REALTIME
    #define MEASURE_TIMING
    
    /****************************************************************************/
    
    #define NSEC_PER_SEC (1000000000L)
    #define PERIOD_NS (NSEC_PER_SEC / FREQUENCY)
    
    #define DIFF_NS(A, B) (((B).tv_sec - (A).tv_sec) * NSEC_PER_SEC + \
    	(B).tv_nsec - (A).tv_nsec)
    
    #define TIMESPEC2NS(T) ((uint64_t) (T).tv_sec * NSEC_PER_SEC + (T).tv_nsec)
    
    /****************************************************************************/
    
    // EtherCAT
    static ec_master_t *master = NULL;
    static ec_master_state_t master_state = {};
    
    static ec_domain_t *domain1 = NULL;
    static ec_domain_state_t domain1_state = {};
    
    /****************************************************************************/
    
    // process data
    static uint8_t *domain1_pd = NULL;
    
    #define DigOutSlavePos 0, 0
    
    #define AM64X    0x0000059D, 0x54490022     //--> was 0xE000059D in mainv2.c but both work
    
    // offsets for PDO entries
    static int off_dig_out;
    
    static unsigned int counter = 0;
    static unsigned int blink = 0;
    static unsigned int sync_ref_counter = 0;
    const struct timespec cycletime = {0, PERIOD_NS};
    
    /*****************************************************************************/
    
    struct timespec timespec_add(struct timespec time1, struct timespec time2)
    {
    	struct timespec result;
    
    	if ((time1.tv_nsec + time2.tv_nsec) >= NSEC_PER_SEC) {
    		result.tv_sec = time1.tv_sec + time2.tv_sec + 1;
    		result.tv_nsec = time1.tv_nsec + time2.tv_nsec - NSEC_PER_SEC;
    	} else {
    		result.tv_sec = time1.tv_sec + time2.tv_sec;
    		result.tv_nsec = time1.tv_nsec + time2.tv_nsec;
    	}
    
    	return result;
    }
    
    /*****************************************************************************/
    
    void check_domain1_state(void)
    {
        ec_domain_state_t ds;
    
        ecrt_domain_state(domain1, &ds);
    
        if (ds.working_counter != domain1_state.working_counter)
            printf("Domain1: WC %u.\n", ds.working_counter);
        if (ds.wc_state != domain1_state.wc_state)
            printf("Domain1: State %u.\n", ds.wc_state);
    
        domain1_state = ds;
    }
    
    /*****************************************************************************/
    
    void check_master_state(void)
    {
        ec_master_state_t ms;
    
        ecrt_master_state(master, &ms);
    
    	if (ms.slaves_responding != master_state.slaves_responding)
            printf("%u slave(s).\n", ms.slaves_responding);
        if (ms.al_states != master_state.al_states)
            printf("AL states: 0x%02X.\n", ms.al_states);
        if (ms.link_up != master_state.link_up)
            printf("Link is %s.\n", ms.link_up ? "up" : "down");
    
        master_state = ms;
    }
    
    /****************************************************************************/
    
    void cyclic_task()
    {
        struct timespec wakeupTime, time;
    #ifdef MEASURE_TIMING
        struct timespec startTime, endTime, lastStartTime = {};
        uint32_t period_ns = 0, exec_ns = 0, latency_ns = 0,
                 latency_min_ns = 0, latency_max_ns = 0,
                 period_min_ns = 0, period_max_ns = 0,
                 exec_min_ns = 0, exec_max_ns = 0;
    #endif
    
        // get current time
        clock_gettime(CLOCK_TO_USE, &wakeupTime);
    
    	while(1) {
    		wakeupTime = timespec_add(wakeupTime, cycletime);
            clock_nanosleep(CLOCK_TO_USE, TIMER_ABSTIME, &wakeupTime, NULL);
    
    #ifdef MEASURE_TIMING
            clock_gettime(CLOCK_TO_USE, &startTime);
            latency_ns = DIFF_NS(wakeupTime, startTime);
            period_ns = DIFF_NS(lastStartTime, startTime);
            exec_ns = DIFF_NS(lastStartTime, endTime);
            lastStartTime = startTime;
    
            if (latency_ns > latency_max_ns) {
                latency_max_ns = latency_ns;
            }
            if (latency_ns < latency_min_ns) {
                latency_min_ns = latency_ns;
            }
            if (period_ns > period_max_ns) {
                period_max_ns = period_ns;
            }
            if (period_ns < period_min_ns) {
                period_min_ns = period_ns;
            }
            if (exec_ns > exec_max_ns) {
                exec_max_ns = exec_ns;
            }
            if (exec_ns < exec_min_ns) {
                exec_min_ns = exec_ns;
            }
    #endif
    
    		// receive process data
    		ecrt_master_receive(master);
    		ecrt_domain_process(domain1);
    
    		// check process data state (optional)
    		check_domain1_state();
    
    		if (counter) {
    			counter--;
    		} else { // do this at 1 Hz
    			counter = FREQUENCY;
    
    			// check for master state (optional)
    			check_master_state();
    
    #ifdef MEASURE_TIMING
                // output timing stats
                printf("period     %10u ... %10u\n",
                        period_min_ns, period_max_ns);
                printf("exec       %10u ... %10u\n",
                        exec_min_ns, exec_max_ns);
                printf("latency    %10u ... %10u\n",
                        latency_min_ns, latency_max_ns);
                period_max_ns = 0;
                period_min_ns = 0xffffffff;
                exec_max_ns = 0;
                exec_min_ns = 0xffffffff;
                latency_max_ns = 0;
                latency_min_ns = 0xffffffff;
    #endif
    
    			// calculate new process data
    			blink = !blink;
    		}
    
    		// write process data
    		EC_WRITE_U8(domain1_pd + off_dig_out, blink ? 0x66 : 0x99); //--> domain1_pd pointer + off_dig_out (an offset)
    
    		// write application time to master
    		clock_gettime(CLOCK_TO_USE, &time);
    		ecrt_master_application_time(master, TIMESPEC2NS(time));
    
    		if (sync_ref_counter) {
    			sync_ref_counter--;
    		} else {
    			sync_ref_counter = 1; // sync every cycle
    			ecrt_master_sync_reference_clock(master);
    		}
    		ecrt_master_sync_slave_clocks(master);
    
    		// send process data
    		ecrt_domain_queue(domain1);
    		ecrt_master_send(master);
    
    #ifdef MEASURE_TIMING
            clock_gettime(CLOCK_TO_USE, &endTime);
    #endif
    	}
    }
    
    /****************************************************************************/
    
    int main(int argc, char **argv)
    {
        ec_slave_config_t *sc;
    
    	if (mlockall(MCL_CURRENT | MCL_FUTURE) == -1) {
    		perror("mlockall failed");
    		return -1;
    	}
    
        master = ecrt_request_master(0);
        if (!master)
            return -1;
    
        domain1 = ecrt_master_create_domain(master);
        if (!domain1)
            return -1;
    
        if (!(sc = ecrt_master_slave_config(
                        master, DigOutSlavePos, AM64X))) {
            fprintf(stderr, "Failed to get slave configuration.\n");
            return -1;
        }
    
        off_dig_out = ecrt_slave_config_reg_pdo_entry(sc,
                0x2000, 0x02, domain1, NULL);
        if (off_dig_out < 0)
            return -1;
    
        // configure SYNC signals for this slave
    	ecrt_slave_config_dc(sc, 0x2000, PERIOD_NS, 4400000, 0, 0);
    
        printf("Activating master...\n");
        if (ecrt_master_activate(master))
            return -1;
    
        if (!(domain1_pd = ecrt_domain_data(domain1))) {
            return -1;
        }
    
        pid_t pid = getpid();
        if (setpriority(PRIO_PROCESS, pid, -19))
            fprintf(stderr, "Warning: Failed to set priority: %s\n",
                    strerror(errno));
    
    	printf("Starting cyclic function.\n");
        cyclic_task();
    
        return 0;
    }
    
    /****************************************************************************/
    

    -Daolin

  • Was the failure the same "EtherCAT ERROR 0: Failed to calculate bus topology" error?

    The following main file was what I last was able to get working with the generic IgH EtherCAT master stack running on AM62x EVM as EtherCAT master/maindevice connected to a single AM64x EVM as the EtherCAT slave/subdevice.

    Please note, I haven't tested this again in a long time and I'm not positive it will work for you but feel free to give it a try.

    Also, from what I remember, I had to use this version of the main file, which I modified from ethercat/examples/dc_user/main.c because it seems like in my original setup, the AM64x EVM EtherCAT slave/subdevice required the ecrt_master_application_time function to run, otherwise the EtherCAT master will not receive any response from the EtherCAT subdevice.

    Hi Daolin

         I will try it,

         is it possible that I used the wrong app in AM243x LP board?

         I use this demo:

        -----------------------------------------------------------------------------------------------------

         ./ind_comms_sdk_am243x_09_02_00_24/examples/industrial_comms/ethercat_slave_demo/device_profiles/401_simple/am243x-lp/r5fss0-0_freertos/ti-arm-clang/ethercat_slave_simple_demo.release.out

       is it correct?

       here are another two examples:

          ./ind_comms_sdk_am243x_09_02_00_24/examples/industrial_comms/ethercat_slave_demo/device_profiles/ctt/am243x-lp/r5fss0-0_freertos/ti-arm-clang//ethercat_slave_simple_demo.release.out

       and

             ./ind_comms_sdk_am243x_09_02_00_24/examples/industrial_comms/ethercat_slave_demo/device_profiles/402_cia/am243x-lp/r5fss0-0_freertos/ti-arm-clang//ethercat_slave_simple_demo.release.out

      ------------------------

    which one is correct?

    Thanks

       Semon

  • Hi Semon,

       is it possible that I used the wrong app in AM243x LP board?

    To my knowledge, as long as there is no error on the EtherCAT slave simple example you are using on AM243x LP, EtherCAT slave side, I don't think it really should impact the EtherCAT maindevice/master side with IgH. 

    If I remember correctly, there should just be that vendor ID number that the EtherCAT slave side should have so that the EtherCAT maindevice/master can identify the correct subdevices when scanning the connected devices.

    I don't remember specifically which app/EtherCAT slave simple demp I ran but I think it might have been 401_simple. 

    -Daolin

  • To my knowledge, as long as there is no error on the EtherCAT slave simple example you are using on AM243x LP, EtherCAT slave side, I don't think it really should impact the EtherCAT maindevice/master side with IgH. 

    If I remember correctly, there should just be that vendor ID number that the EtherCAT slave side should have so that the EtherCAT maindevice/master can identify the correct subdevices when scanning the connected devices.

    I don't remember specifically which app/EtherCAT slave simple demp I ran but I think it might have been 401_simple. 

    Hello Daolin

         seems it works now, 

    ----------------------------------------

    omain1: State 2.
    Domain1: WC 0.
    Domain1: State 0.
    Domain1: W[ 676.633015] EtherCAT 0: Slave states on main device: SAFEOP + ERROR.
    C 1.
    Domain1: State 2.
    Domain1: WC 0.
    Domain1: State 0.
    Domain1: WC 1.
    Domain1: State 2.
    Domain1: WC 0.
    Domain1: State 0.[ 676.647065] EtherCAT 0: Re-scanning now.

    Domain1: WC 1.
    Domain1: State 2.
    Domain1: WC 0.
    Domain1: State 0.
    Domain1: WC 1.
    Domain1: State 2.
    Domain1: WC 0.
    Domain1: State 0.
    Domain1: WC 1.
    Domain1: State 2.
    [ 676.668017] EtherCAT 0: Scanning bus.

    Domain1: State 0.
    Domain1: WC 1.
    Domain1: State 2.
    Domain1: [ 676.675970] EtherCAT WARNING 0-0: Slave has state error bit set (SAFEOP + ERROR)!
    WC 0.
    Domain1: State 0.
    Domain1: WC 1.
    Domain1: State 2.
    Domain1: WC 0.
    Domain1: State 0.
    Domain1: WC 1.
    Domain1: State 2.
    Domain1: WC 0.
    Domain1: State 0.

    -----------------------------------------

         thanks for your help

    Regards

       Semon

  • HI, I encountered the same problem, how did you solve it?

  • HI, I encountered the same problem, how did you solve it?

    Hi Wang Tao

         please check which port is enabled for EtherCAT in your master device, and connect the cable correctly, or enable all port for EtherCAT

    Regards

       Semon

  • Can the following phenomenon prove that there is no problem with the network cable connection?

    1、

    AM243X logs:

    State change: 0x2 -> 0x12
    State change: 0x12 -> 0x2
    State change: 0x2 -> 0x1
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x12
    State change: 0x12 -> 0x2

    slave receive master message.

    The strange thing is that there is no 0x12 status in the am243x sdk

    /// EC_STATE_T EtherCAT State Machine states.
    typedef enum EC_API_SLV_EEsmState
    {
        EC_API_SLV_eESM_uninit    = 0x00,           ///< Uninitialized State
        EC_API_SLV_eESM_init      = 0x01,           ///< Init State
        EC_API_SLV_eESM_preop     = 0x02,           ///< PreOP State
        EC_API_SLV_eESM_bootstrap = 0x03,           ///< BootStrap State
        EC_API_SLV_eESM_safeop    = 0x04,           ///< SafeOP State
        EC_API_SLV_eESM_op        = 0x08,           ///< Operational State
        EC_API_SLV_eESM_errState  = 0x10,           ///< Error Flag
        EC_API_SLV_eESM_errDevId  = 0x20,           ///< Explicit Device ID
    } EC_API_SLV_EEsmState_t;

    2、

    root@lubancat:/home/cat# ethercat master
    Master0
    Phase: Idle
    Active: no
    Slaves: 1
    Ethernet devices:
    Main: ca:89:93:42:a5:3a (attached)
    Link: UP
    Tx frames: 670878
    Tx bytes: 41289851
    Rx frames: 670877
    Rx bytes: 41289791
    Tx errors: 0
    Tx frame rate [1/s]: 143 144 145
    Tx rate [KByte/s]: 8.4 8.4 8.5
    Rx frame rate [1/s]: 143 144 145
    Rx rate [KByte/s]: 8.4 8.4 8.5
    Common:
    Tx frames: 670878
    Tx bytes: 41289851
    Rx frames: 670877
    Rx bytes: 41289791
    Lost frames: 0
    Tx frame rate [1/s]: 143 144 145
    Tx rate [KByte/s]: 8.4 8.4 8.5
    Rx frame rate [1/s]: 143 144 145
    Rx rate [KByte/s]: 8.4 8.4 8.5
    Loss rate [1/s]: 0 -0 0
    Frame loss [%]: 0.0 -0.0 0.0
    Distributed clocks:
    Reference clock: Slave 0
    DC reference time: 0
    Application time: 0
    2000-01-01 00:00:00.000000000
    root@lubancat:/home/cat#

    3、

    root@lubancat:/home/cat# ethercat pdos
    SM0: PhysAddr 0x1000, DefaultSize 1024, ControlRegister 0x26, Enable 1
    SM1: PhysAddr 0x1400, DefaultSize 1024, ControlRegister 0x22, Enable 1
    SM2: PhysAddr 0x1800, DefaultSize 0, ControlRegister 0x64, Enable 1
    RxPDO 0x1600 ""
    PDO entry 0x2000:02, 8 bit, ""
    PDO entry 0x2000:03, 8 bit, ""
    PDO entry 0x2000:04, 16 bit, ""
    RxPDO 0x1601 ""
    PDO entry 0x2000:01, 32 bit, ""
    SM3: PhysAddr 0x2400, DefaultSize 0, ControlRegister 0x20, Enable 1
    TxPDO 0x1a00 ""
    PDO entry 0x2002:02, 8 bit, ""
    PDO entry 0x2002:04, 16 bit, ""
    PDO entry 0x2002:03, 8 bit, ""
    TxPDO 0x1a01 ""
    PDO entry 0x2002:01, 32 bit, ""
    root@lubancat:/home/cat#