OpenMP problem on C6678L

Hi Sayan,

The error you described have no business with your cfg file. It should be caused in the process of connecting to the core.

So just check the connection of JTAG and whether you attached the correct GEL file in your Target Configuration File for every COREx.

If the problem remains, you can have a look at http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/131875.aspx for reference.

Allen

Thank you for answering. I thought of trying out building without CCS by using xdctools (following the User_Guide document in the omp package); and now I am stuck with a different error related to memory mapping. I have attached my project files from repo, in case someone could advice me in general (about bugs, potential flaws, etc) about *.bld and *cfg files then it would be great.

The linking error that I am having currently is:

"package/cfg/omp_matvec_pe66.xdl", line 209: error: run placement fails for

  object ".localfar", size 0x2aa98 (page 0).  Available ranges:

   L2SRAM       size: 0x80000      unused: 0x0          max hole: 0x0       

"package/cfg/omp_matvec_pe66.xdl", line 307: error: run placement fails for

   object "GROUP_1", size 0x3e (page 0).  Available ranges:

   L2SRAM       size: 0x80000      unused: 0x0          max hole: 0x0 

Following are the relevant portions of my project.cfg file:

Program.sectMap[".localfar"]= new Program.SectionSpec();

Program.sectMap[".localfar"].loadSegment = "L2SRAM";

Program.sectMap[".localfar"].runAddress =  0x00804000;

...

Program.sectMap["GROUP_1"]= new Program.SectionSpec();

Program.sectMap["GROUP_1"].loadSegment = "L2SRAM";

Program.sectMap["GROUP_1"].runAddress =   0x00808000;

Do I need to mention different Global offsets per core? If yes, then please let me know how it could be done.

Thanks,

Sayan

1072.myRepoOMP.zip

Hi Sayan,

The new issue is caused by your available L2SRAM is too small to locate the big section such as localfar.

Two ways you can try:

1. Place the big-size section in DDR3, and open the L2 Cache(this can be done by using CSL API or edit the RTSC platform) to keep the performance.

2.If you indeed want localfar placed in L2SRAM, then you must make sure there is more than 0x2aa98 space, of course as the cost, other sections must be evicted into DDR3. 

Normally, the first way is usually-used.

Allen

Thanks, I have tried out the first option. I have moved the two sections to DDR3, but I am still getting the same error as displayed below. I have also set the Cache as you've mentioned (snippet below), I took help from this forum post to do that, but still I am getting the same error.

"package/cfg/omp_matvec_pe66.xdl", line 209: error: run placement fails for

   object ".localfar", size 0x2aa98 (page 0).  Available ranges:

   L2SRAM       size: 0x80000      unused: 0x0          max hole: 0x0       

"package/cfg/omp_matvec_pe66.xdl", line 307: error: run placement fails for

   object "GROUP_1", size 0x3e (page 0).  Available ranges:

   L2SRAM       size: 0x80000      unused: 0x0          max hole: 0x0 

 undefined first referenced                

  symbol       in file                     

 --------- ----------------                

 main      package/cfg/omp_matvec_pe66.oe66

error: unresolved symbols remain

error: errors encountered during linking; "omp_matvec.xe66" not built

Changes in omp_matvec.cfg:

Cache = xdc.useModule('ti.sysbios.family.c66.Cache');

Cache.setMarMeta(0x80000000, 0x20000000, Cache.PC | Cache.PCX | Cache.PFX | Cache.WTE );

...

Program.sectMap[".localfar"]= new Program.SectionSpec();

Program.sectMap[".localfar"].loadSegment = "DDR3";

...

Program.sectMap["GROUP_1"]= new Program.SectionSpec();

Program.sectMap["GROUP_1"].loadSegment = "DDR3";

I am also getting the exactly same error when I try doing the same using CCS...somehow memory allocation for .localfar and GROUP_1 fails.

Thanks,

Sayan

Hi Sayan,

First, according to the error message, the localfar section seems remains in L2 and your cfg didn't take effect. Because I don't know the function of that section, so I suggest to change the default platform configuration by: CCS->Tools->RTSC Tools->Platform->Edit/View, then browse to the XDCTools packages directory and choose ti.platforms.evm6670 and go to next sheet. You will see in the below of window 3 options to choose the default segment to place the stack,data and code. I suppose they will be L2SRAM now, so change all to DDR3 to have a try.

Second, you seems only make the DDR region as cachable and L2 cache should be opened using:

#include<ti/csl/csl_cache.h>
#include<ti/csl/csl_cacheAux.h>

void main()

{

   ……

CACHE_setL2Size(CACHE_256KCACHE); //Set L2 cache to 256K for example

   ……

}

This is API from PDK's CSL, so you also need include 'MCSDK PDK TMS320C6670' package in your project->Property->CCS build->RTSC.

After do that, the second half of L2SRAM is cache and cannot be located with any sections in your cfg or cmd. You can check for Debug\xx.map file to see the sections allocation map for details.

Allen

Hi,

A quick question : how do I obtain/ install the omp_1_00_00_34_eng package you mention?

I have a standard installation of SYS/BIOS for CCS5 / 5.1 and I don't see this package in the CCS directory. OpenMP would be very useful. Also, is the example you mention and documentation on using OpenMP with SYS/BIOS part of the omp_1_00_00_34_eng  package?

Thanks in advance,

Simon

It should come with the CCS installation...perhaps you didn't do a full install. Yes, in the "omp_1_00_00_34_eng" package folder, there is a User_Guide doc (and links to other docs) which I found to be helpful. 

//Sayan

Sayan,

Thanks, I have a full install of CCS 5.1.0.09 on Linux, with bios_mcsdk_02_00_05_17 and SYS/BIOS 6_33_00_19 but I still can't see omp_1_00_00_34_eng in the installation directory.

Did you install any packages in addition to these?

Simon

Hello,

Didn't read completely, since you have already installed MCSDK, so can you see "OpenMP DSP BIOS Runtime Lib" in "Product and Repo" when you go to "Build Options - > General" of  a project? May be a path related problem?

//Sayan

No the option isn't there. MCSDK appears to be installed OK because I get options in the "Products and Repositories" for MCSDK, MCSDK PDK TMS320C6678 etc.

I would also expect a dirctory in /opt/ti named (say) omp_1_00_00_34_eng but there isn't one. In fact if I search the whole TI install directory I still can't see it. I tried it on Windows too but still not there.

Simon

(I've started this as a separate post because it's a bit of a deviation from your original post, see:  http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/154075.aspx )

Thank you for your directions Allen. I changed the default segment to DDR3 for target C6670, but I am getting this error while launching:

C66xx_0: Trouble Writing Memory Block at 0x880000 on Page 0 of Length 0x7ff0: (Error -1190 @ 0x880000) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.520.0) 

C66xx_0: GEL: File: /home/c7364u07/workspace_v5_1/OMP_6670/Release/OMP_6670.out: Load failed.

The Memory Configuration section of Debug/xx.map of my project is as follows:

MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill

----------------------  --------  ---------  --------  --------  ----  --------

  L2SRAM                00800000   00100000  000dca68  00023598  RW X

  MSMCSRAM              0c000000   00200000  00000000  00200000  RW X

  DDR3                  80000000   20000000  00000000  20000000  RWIX

I also attach a screenshot of the Platform update window, where I just changed the default segment from L2SRAM to DDR3. But I still see some segments allocated to L2SRAM and MSMCSRAM above, so I am not sure if I was able to do exactly what you suggested.

I am using CCS v5.1 on Ubuntu 10.0.04.

Thanks,

Sayan

Sayan,

Have you try with the latest Emulation drivers.

http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html

Hello Varada,

I tried with the latest drivers as you suggested - BIOS-MCSDK 2.0.5.17 and rebuilt my project, but I get the same errors. Here is my memory map,

I've modified the ti.evm.6670 platform to place code, data and text sections in DDR3, but I still see L2SRAM and MSMCSRAM:

MEMORY CONFIGURATION

 name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
 L2SRAM 00800000 00100000 000dca68 00023598 RW X
 MSMCSRAM 0c000000 00200000 00000000 00200000 RW X
 DDR3 80000000 20000000 00000000 20000000 RWIX

Here is how I am modifying the memory map of the platform:

1. File -> New -> Other -> "Select" Edit/View RTSC Platform

2. Select package name as ti.platforms.evm6670

3. The "Edit Platform" window appears, modify the "Memory Sections" in the bottom part to DDR3.

Instead of Edit/View RTSC platform, I'd also tried with new RTSC platform, but the same error persists.

I am selecting the GEL files from the following location:

./../CCS5.1.0/ccsv5/ccs_base/emulation/boards/evmc6670l/gel/evmc6670l.gel

Please note that the device that I have is actually C6678L, but following Allen's suggestion, I tried to change the target to C6670. Changing 

to C6678 as the target gives a build error (related to incorrect memory mapping) mentioned in previous posts. In this post whatever I mention 

is w.r.t ti.platforms.6670 as the target.

   Following is the Console output when I try to run the Debug configuration: 

C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_1: GEL Output: Setup_Memory_Map...
C66xx_1: GEL Output: Setup_Memory_Map... Done.
C66xx_2: GEL Output: Setup_Memory_Map...
C66xx_2: GEL Output: Setup_Memory_Map... Done.
C66xx_3: GEL Output: Setup_Memory_Map...
C66xx_3: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: C6670L GEL file Ver is 1.3 
C66xx_0: GEL Output: Setup Cache... 
C66xx_0: GEL Output: L1P = 32K 
C66xx_0: GEL Output: L1D = 32K 
C66xx_0: GEL Output: L2 = ALL SRAM 
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: PLL1 Setup... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 983.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 327.6667 MHz, SYSCLK5 = 196.6 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.35938 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... 
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=13, md=23!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=14, md=24!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=14, md=25!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=15, md=26!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=15, md=27!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=16, md=28!
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=29!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PLL3 Setup... 
C66xx_0: GEL Output: PLL3 Setup for PASSCLK @ 1044.5 MHz... 
C66xx_0: GEL Output: PLL3 Setup... Done.
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL Output: 
SGMII SERDES has been configured.
C66xx_0: GEL Output: Set Board and DSP IO/Timers Pins... 
C66xx_0: GEL Output: Set Board and DSP IO/Timers Pins... Done.
C66xx_0: GEL Output: Configuring CPSW ...
C66xx_0: GEL Output: Configuring CPSW ...Done 
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: 2: XMC setup complete.
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: Global Default Setup... Done.
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: DSP Reset CPU...
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DSP Reset CPU... Done.
C66xx_0: Trouble Writing Memory Block at 0x880000 on Page 0 of Length 0x7ff0: (Error -1190 @ 0x880000) Unable to access device 

memory. 

Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable 

JTAG settings (e.g. lower TCLK). (Emulation package 5.0.520.0) 
C66xx_0: GEL: File: /home/c7364u07/workspace_v5_1/OMP_mem_mgd_6670/Debug/OMP_mem_mgd_6670.out: Load failed.

I think I am not able to do the memory mapping correctly (since even after editing RTSC platform to only DDR3, I see L2SRAM in the 

memory map),  any help appreciated....Thanks!

Sayan

I just checked that If I change my target to "ti.omp.examples.platforms.evm6678" in Build Options, then I get correct output on my simple program, which does nothing but prints "Hello World" from 8 threads (8 cores). However, I am yet to test with this setting against real world examples.

Can someone please confirm that for OpenMP programs, whether one would need to have "ti.omp.examples.platforms.*" as target platform?