TDA4VM: J7200] Could you explain Watchdog sequence ?

Hello Jace,

I am assuming you are asking about SoC RTI watchdog reset.

There are 3 parts to it:

1. RTI Module which has the timer expiry.
2. SOC ESM - This is the error signaling module that needs to catch the watchdog RTI timer expiry.
3. ESM PMIC which is PMIC part to trigger a SoC reset upon ESM event.

1 --> is taken care by the RTI watchdog driver: https://github.com/torvalds/linux/blob/master/drivers/watchdog/rti_wdt.c

2 --> Is done as part of R5 SPL repo: https://github.com/u-boot/u-boot/blob/master/drivers/misc/k3_esm.c

3 --> Is done as part of R5 SPL in U-Boot repo: https://github.com/u-boot/u-boot/blob/master/drivers/misc/esm_pmic.c

This is functional in 9.2 SDK.

- Keerthy