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Original question:

AM6442: CLKOUT0 frequency

AM6442: Clarification on CLKOUT0 (A19) Usage for Custom 10 MHz Clock Output

Nishanthkumar Sakthivel
Prodigy 60 points

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Dear TI Team,

We are planning to use the AM6442 SoC in a 5-port RGMII Ethernet configuration leveraging the following interfaces:

  • CPSW_RGMII1

  • CPSW_RGMII2

  • PRU1_RGMII1

  • PRU1_RGMII2

  • PRU0_RGMII1

In addition to the Ethernet setup, we require a 10 MHz clock output from the SoC to interface with another onboard device. For this purpose, we are considering using CLKOUT0 (pin A19) to provide the required 10 MHz clock.

Upon reviewing the AM64x EVM schematic, we noted that pin A19 (CLKOUT0) is connected to a clock buffer that supplies clock pulses to the X1 inputs of the Ethernet PHYs. Based on our understanding, if we opt to use discrete 25 MHz crystals for the X1 inputs of each PHY, this would allow us to decouple pin A19 from PHY-related clocking and repurpose it as a general-purpose clock output.

We would like to confirm whether this approach is valid and supported:

  1. Is it possible to use independent 25 MHz crystals for the PHYs instead of relying on CLKOUT0?

  2. Once freed, can CLKOUT0 (A19) be reliably configured via software to output a 10 MHz clock for use by another onboard device?

  3. Are there any known limitations or considerations with configuring CLKOUT0 for custom clock output in this scenario?

We would appreciate your guidance and confirmation to proceed with this approach in our design.

Thank you for your support in advance

  • 0
    TI__Guru**** 226535 points

    Hello Nishanthkumar,

    Thank you for the query.

    The common use case for CLKOUT0 is to source 25MHz or 50MHz.

    I suspect we use an external oscillator in the AM64x EVM and you can continue to use the same.

    In case you understand the challenges with using x5 25M crystals for EPHY and x1 crystal for SOC you could use the same.

    Please ensure the clock specs follow the SOC data sheet and the EPHY reset.

    Nishanthkumar Sakthivel said:

    • Once freed, can CLKOUT0 (A19) be reliably configured via software to output a 10 MHz clock for use by another onboard device?

    • Are there any known limitations or considerations with configuring CLKOUT0 for custom clock output in this scenario?

    This may not be a use case that we may have tested.

    You should use the clock tree tool to understand how to configure the internal clock paths.  The clock tree tool is part of the SYSCONFIG tool.  Select clock tree tool in the software select dropdown and select the appropriate device after launching the SYSCONFIG tool. 

    Regards,

    Sreenivasa

  • 0
    TI__Guru 64655 points

    1. The answer to this question depends on your product requirements. I have been told some of our customers using the PRU_ICSSG subsystem in AM64x may need a common clock source to all Ethernet PHYs when implementing a Time-Sensitivity Network. The common clock source eliminates PPM error differences associated with multiple reference clock sources. You will need to research your product requirements and understand how to implement the appropriate clocking topology to achieve the requirement.

    2. No. The CLKOUT0 signal function can only be configured to source a 25MHz or 50MHz clock. The intended function of this clock output was to be used with an Ethernet PHY, where it can be configured to source a 50MHz clock for the RMII peripheral, or a 25MHz clock in lieu of a crystal circuit. I suggest you use the clock tree tool that is part of the SYSCONFIG tool to understand the internal clocking topology of AM64x devices.

    3. The CLKOUT0 signal function is not selected by default. Software must configure the appropriate multiplexers in the signal path to select either 25MHz or 50MHz, configure the respective PADCONFIG register to select the CLKOUT0 signal function, and enable the output buffer associated with the pin being used for this signal function. Note: The internal multiplexers and pin multiplexing logic which selects and enables the signal function may create a short clock pulse (glitch) since the registers which control these operations are not synchronous to the clock signal. This means the device you are source with this clock should be held in reset until software has initialized the entire signal path and the clock is stable. We also do not define performance of the clock output because it can be system dependent. You should validate the clock output performance meets the clock input requirements for the attached device across all operating conditions before deciding to use it.

    Regards,
    Paul