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TDA4VH-Q1: Ask the CPSW9G Native Linux Driver with SGMII

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Hi TI expert,

We using tda4vh custom board and using the internal switch cpsw9g with marvell PHY 88xx,
=> custom device tree with our PHY and eth0 link up, but we cannot ping in LAN connection

&serdes_ln_ctrl {
	idle-states = <J784S4_SERDES1_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
		<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
		<J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
};

&serdes_wiz2 {
	status = "okay";
};

&serdes2 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	serdes2_qsgmii_link: phy@0 {
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_QSGMII>;
		resets = <&serdes_wiz2 3>;
	};
};

&main_gpio0 {
	status = "okay";
};

&main_cpsw0 {
	status = "okay";
};

&main_cpsw0_port5 {
	status = "okay";
	phy-handle = <&cpsw9g_phy2>;
	phy-mode = "sgmii";
	mac-address = [c2 b7 ed f2 87 ab];
	phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
	phy-names = "mac", "serdes";
	reset-post-delay-us = <120000>;
};

&main_cpsw0_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins_default>;
	bus_freq = <1000000>;
	reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw9g_phy2: ethernet-phy@6 {
		reg = <6>;
	};
};

&serdes_refclk {
	clock-frequency = <100000000>;
};

  • Hi,

    custom device tree with our PHY and eth0 link up, but we cannot ping in LAN connection

    Link can be up based on PHY Link stats.

    Can you check the PLL lock status by reading the SGMII5 control register?

    You need to define all SerDes lanes under "serdes_ln_ctrl"

    Also, use phy@2 in the below for readability and usability.
    serdes2_qsgmii_link: phy@0 {


    Best Regards,
    Sudheer

  • Hi Sudheer,

    Thank you for your quick support.
    "Can you check the PLL lock status by reading the SGMII5 control register?"
    Can you give some command or guideline to read it.

    Best Regards,
    Vuong Huynh

  • Hi,

    "Can you check the PLL lock status by reading the SGMII5 control register?"
    Can you give some command or guideline to read it.

    You can use the devmem2 tool to read registers.
    Also, refer to the TRM for the Register details, which are shared in an Excel file. 

    MAC PORT-5 SGMII Status register.
    #devmem2 0x0C000514

    Best Regards,
    Sudheer

  • Hi Sudheer, 

    Follow you comment, we check MAC PORT-5 SGMII Status register.
    Lock status is 1, Link indicator is 0. But we don't know the status is good or not.




    We already define all SerDes lanes under "serdes_ln_ctrl"

    &serdes_ln_ctrl {
        idle-states = <J784S4_SERDES0_LANE0_IP1_UNUSED>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
                  <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_IP4_UNUSED>,
                  <J784S4_SERDES1_LANE0_IP3_UNUSED>, <J784S4_SERDES1_LANE1_IP3_UNUSED>,
                  <J784S4_SERDES1_LANE2_IP4_UNUSED>, <J784S4_SERDES1_LANE3_IP4_UNUSED>,
                  <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
                  <J784S4_SERDES2_LANE2_IP3_UNUSED>, <J784S4_SERDES2_LANE3_IP3_UNUSED>;        
    };


    &serdes_wiz2 {
        status = "okay";
    };

    &serdes2 {
        status = "okay";
        #address-cells = <1>;
        #size-cells = <0>;

        serdes2_sgmii_link: phy@2 {
            reg = <0>;
            cdns,num-lanes = <1>;
            #phy-cells = <0>;
            cdns,phy-type = <PHY_TYPE_SGMII>;
            resets = <&serdes_wiz2 1>;
        };
    };

    &main_gpio0 {
        status = "okay";
    };

    &main_cpsw0 {
        status = "okay";
    };

    &main_cpsw0_port5 {
        status = "okay";
        phy-handle = <&cpsw9g_phy2>;
        phy-mode = "sgmii";
        mac-address = [c2 b7 ed f2 87 ab];
        phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
        phy-names = "mac", "serdes";
    };

    &main_cpsw0_mdio {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&mdio0_pins_default>;
        bus_freq = <1000000>;
        reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>;
        reset-post-delay-us = <120000>;
        #address-cells = <1>;
        #size-cells = <0>;

        cpsw9g_phy2: ethernet-phy@6 {
            reg = <6>;
        };
    };

    &serdes_refclk {
        clock-frequency = <100000000>;
    };

    Could you help to check again our device tree?

  • Hi Sudheer, 

    We have already network for SGMII work well.
    But the link speed unstable sometime it is 10Mb sometime 1Gb.
    Could you have some resigter or tunning value for this? 

    Best Regards,
    Vuong Huynh

  • Hi,

    Can you please confirm, have you disabled ETHFW running on MCU2_0 core?

    But the link speed unstable sometime it is 10Mb sometime 1Gb.

    Whenever Link is down it might be showing the default speed of 10Mbps.
    Also, can you please check if any Link down observed on peer side?

    Best Regards,
    Sudheer

  • Hi Sudheer,

    As I checked, the Link is Up both side board and my PC (connect to board)

    "Can you please confirm, have you disabled ETHFW running on MCU2_0 core?"
    Could you please give me command or something to check it?

    Best Regards,

    Vuong Huynh

  • Hi,

    "Can you please confirm, have you disabled ETHFW running on MCU2_0 core?"
    Could you please give me command or something to check it?

    You can check which binary is loaded into the MCU2_0 core?

    The below command will point out the firmware soft-linked to the MCU2_0 core if you use the SPL boot flow.
    # ls -l /lib/firmware

    If you use the SBL boot flow with a multi-core app, check which binary is mapped to the MCU2_0 core.

    Best Regards,
    Sudheer

  • Hi,
    May I need to unlink MCU2_0 or do something?

    Best Regards,
    VH

  • Hi,

    May I need to unlink MCU2_0 or do something?

    You can softlink ipc_echo test instead of vx_app_rtos to main_r5f_0_0 if you are not interested in vision applications.
     
    # cd /lib/firmware
    # ln -s -f /lib/firmware/ti-ipc/j784s4/ipc_echo_test_mcu2_0_release_strip.xer5f j784s4-main-r5f0_0-fw

    Also, remove the vision apps overlay from the uEnv.txt file in the boot partition of the SD card.

    If you want to run vision apps, then you can rebuild a vision application without ETHFW and use it.
    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j784s4/latest/exports/docs/vision_apps/docs/user_guide/ETHFW_DEMOS.html#ETHFW_HOWTO_DISABLE


    Best Regards,
    Sudheer