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Original question:

AM6442: AM6442BSFGHAALV

AM6442: RE - Clarification for range to perform SI analysis

Fhamitha M
Prodigy 155 points
Part Number: AM6442
Other Parts Discussed in Thread: DP83869HM

Tool/software:

Hi,

We are performing signal integrity (SI) analysis for an RGMII interface operating at 25 MHz using the AM6442BSFGHAALV processor and DP83869HMRGZT PHY. We have followed certain ranges for Vmax, Vmin, and rise/fall time, which I have summarized in the table below.

I have a few questions:

1. Could you please confirm whether the Vmax, Vmin, and rise/fall time ranges we've used (as shown in the table) are appropriate for this setup?
2. We are treating the TX signals (driven by the AM6442 processor) and RX signals (driven by the DP83869HM PHY) separately in our simulation.
➤ Should we consider different rise/fall time values for the processor and PHY drivers, since their output characteristics are different?
➤ If so, what are the recommended or typical rise/fall time values we should use for each?
3. For RGMII, a typical rise/fall time of 0.75 ns is often referenced. Is this value only applicable for 125 MHz operation?
Since we are operating at 25 MHz, is it acceptable to allow longer rise/fall times (e.g., 5×0.75 ns = 3.75 ns)?
Is this scaling method valid, or should we still aim for 0.75 ns regardless of the interface speed?

Regards, 

Fhamitha M

  • 0
    TI__Guru 62855 points

    Are you expecting the Vmax and Vmin values to represent absolute maximum rating or recommended operating conditions? The DC limits defined in the Absolute Maximum Rating table should never be applied to a device during normal operation. Therefore, you should be using the DC levels defined in the Recommended Operating Conditions table as the DC values in your signal simulations. The "Transient overshoot and undershoot at IO pin" parameter in the Absolute Maximum Ratings table defines the absolute dynamic voltage limits.

    The AM64x datasheet defines a minimum slew rate that is equivalent to a rise/fall time of 0.75ns. Note: the AM64x datasheet currently found on ti.com shows a minimum input slew rate value of 2.64V/ns. This applies to 3.3V operation. The next revision of the datasheet will also show a value of 1.44V/ns which will apply to 1.8V operation. The input slew rate limits defined in the CPSW3G RGMII Timing Conditions table were used by the design team during timing closure of the peripheral operating at its highest operating frequency. The minimum limit is based on a maximum rise/fall time requirement of 0.75ns defined in the RGMII standard. We do not support any violation of datasheet limits even at reduced frequency because the design was not validated under those operating conditions. However, we are more concerned with the clock and data delay relationship on RGMII. The data is transmitted and received via a source synchronous clock which should have similar rise/fall times. Therefore, we are more concerned with meeting the minimum setup and hold times. I encourage you to do your best to achieve a slew rate that is close to or meets the limit even when operating at a reduced frequency. The internal device delays do not scale linear to operating frequency.

    Regards,
    Paul