PROCESSOR-SDK-J784S4: Clarification on phys usage with SGMII on J784S4 CPSW9G

Tool/software:

Clarification on phys usage with SGMII on J784S4 CPSW9G:

I'm using the SGMII mode (not QSGMII or USXGMII) for a DP83869HM PHY connected via SGMII5, which maps to MAC port 5.
In k3-j784s4-evm-quad-port-eth-exp1.dtso,I’ve seen the following configuration:
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
However, since I am using SGMII, not QSGMII, I wanted to confirm the following:
Based on the phy-gmii-sel.c driver, I see that the j784s4-cpsw9g-phy-gmii-sel supports only:
static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
BIT(PHY_INTERFACE_MODE_USXGMII),
.num_ports = 8,
.num_qsgmii_main_ports = 2,
};
static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy);
const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data;
struct device *dev = if_phy->priv->dev;
struct regmap_field *regfield;
int ret, rgmii_id = 0;
u32 gmii_sel_mode = 0;

if (mode != PHY_MODE_ETHERNET)
return -EINVAL;

switch (submode) {
case PHY_INTERFACE_MODE_RMII:
gmii_sel_mode = AM33XX_GMII_SEL_MODE_RMII;
break;

case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_RXID:
gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
break;

case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
rgmii_id = 1;
break;

case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
break;

case PHY_INTERFACE_MODE_QSGMII:
if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_QSGMII)))
goto unsupported;
if (if_phy->priv->qsgmii_main_ports & BIT(if_phy->id - 1))
gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII;
else
gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB;
break;

case PHY_INTERFACE_MODE_SGMII:
if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII)))
goto unsupported;
else
gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII;
break;

case PHY_INTERFACE_MODE_USXGMII:
if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_USXGMII)))
goto unsupported;
else
gmii_sel_mode = J72XX_GMII_SEL_MODE_USXGMII;
break;

default:
goto unsupported;
}

if_phy->phy_if_mode = submode;

dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
__func__, if_phy->id, submode, rgmii_id,
if_phy->rmii_clock_external);

regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];
ret = regmap_field_write(regfield, gmii_sel_mode);
if (ret) {
dev_err(dev, "port%u: set mode fail %d", if_phy->id, ret);
return ret;
}

if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) &&
if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]) {
regfield = if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE];
ret = regmap_field_write(regfield, rgmii_id);
if (ret)
return ret;
}

if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) &&
if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]) {
regfield = if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN];
ret = regmap_field_write(regfield,
if_phy->rmii_clock_external);
}

return 0;

unsupported:
dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
if_phy->id, phy_modes(submode));
return -EINVAL;
}
Does j784s4 support SGMII?
can I safely drop the following two lines from the CPSW port node in my DTS when using SGMII?
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
phy-names = "mac", "serdes";
Is it sufficient to only define phy-handle and phy-mode = "sgmii" for the port, and optionally use the SerDes reference if needed?
&main_cpsw0_port5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&main_phy3>;
// Optional: phys = <&serdes2_sgmii_link>;
};

Just want to ensure I'm not missing any side effects of omitting the GMII_SEL path when using pure SGMII mode.

Thanks in advance for the clarification!

Regards,
B.Apuroop Kumar