PROCESSOR-SDK-J784S4: Clarification on phys usage with SGMII on CPSW9G

Hi Tanmay,

Thanks for the clarification. I also need clarification on ADIN1100 DT node placement behind DP83869 PHY bridge (J784S4).

The ethernet topology is as follows:

cpsw9g (port5) <--> SGMII <--> DP83869 (addr 3) <--> RGMII <--> ADIN1100 (addr 0)

In our current DTS setup, we have defined the ADIN1100 as a child node under the DP83869 MDIO entry like this:

&main_cpsw0_mdio {
status = "okay";

main_phy3: ethernet-phy@3 {
reg = <3>; // DP83869
ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE>;

adin1100: ethernet-phy@0 {
reg = <0>; // ADIN1100 behind DP83869
phy-mode = "rgmii";
};
};
};

Can you please confirm:

Is it valid to define ADIN1100 as a child node inside DP83869 like this?

Or should ADIN1100 be a separate sibling node under &main_cpsw0_mdio instead?

Appreciate your clarification on the correct binding for this bridging setup.

Regards,

B.Apuroop Kumar

Hi Tanmay,

As a continuation of my earlier query -we are also facing an issue where the link is not coming up in this setup:

Current DTS configuration:

• DP83869 is configured with ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE>

• fixed-link set to 10 Mbps full-duplex

• &serdes_wiz2 {
  status = "okay";
  };
  
  &serdes2 {
  status = "okay";
  #address-cells = <1>;
  #size-cells = <0>;
  serdes2_sgmii_link: phy@0 {
  reg = <0>; // lane index
  cdns,num-lanes = <1>;
  cdns,phy-type = <PHY_TYPE_SGMII>;
  #phy-cells = <0>;
  resets = <&serdes_wiz2 1>;
  };
  };
  &main_cpsw0 {
  status = "okay";
  };

  &main_cpsw0_mdio {
  status = "okay";
  pinctrl-names = "default";
  pinctrl-0 = <&main_cpsw9x1_mdio_pins_default>;
  pinctrl-1 = <&main_pmx_gpio_vddshv20_pins_default>; 

  /* DP83869 Bridge PHY - Connected to CPSW SGMII port */
  bridge_phy: ethernet-phy@3 {
  reg = <3>;// DP83869 address
  ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE>;
  fixed-link {
  speed = <10>;
  full-duplex;
  };
  };

  /* ADIN1100 - Connected via RGMII to DP83869 bridge */
  adin1100: ethernet-phy@0 {
  reg = <0>; // ADIN1100 behind DP83869
  phy-mode = "rgmii";
  };
  };

  &main_cpsw0_port5 {
  status = "okay";
  phy-mode = "sgmii";
  phy-handle = <&bridge_phy>;
  phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
  phy-names = "mac", "serdes";
  };

Both PHYs are detected on MDIO, but CPSW port shows “no link”.

Regards,
B. Apuroop Kumar

Hi,

Sorry for the delay, is the issue still present?

Without the mode as RGMII_SGMII_BRIDGE, are you able to test the  device, or would this only be in bridge mode.

We haven't tested the bridge mode on EVM. We might have to include the phy team here as well.

Regards,
Tanmay

Hi Tanmay,

In our setup we need the DP83869HM to operate in SGMII-to-RGMII bridge mode.The Linux driver’s ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE> appears to program the opposite direction (RGMII-to-SGMII), so I removed ti,op-mode.

From the datasheet, I see that the bridge can be set through strap pins (e.g. MIRROR_EN). I want to confirm , is it possible to configure this bridge direction through registers as well, or is it only strap-configurable


Regards,
B. Apuroop Kumar

Hi,

Let me forward this to the phy team and see if any more changes are required for this.

Regards,
Tanmay

Hi Apuroop, 

RGMII-SGMII bridge is programmable via register configuration as well. 
Please follow the below screenshot:

But, instead of writing 0x0043 to register 1DFh, please write the following:
Write 0x0003 to register 1DFh.

Best,
J