PROCESSOR-SDK-J784S4: Clarification on phys usage with SGMII on CPSW9G

Apuroop Kumar Bhattaram

Part Number: PROCESSOR-SDK-J784S4
Other Parts Discussed in Thread: DP83869, DP83869HM

Tool/software:

Hi,
I'm currently using SDK 09.02.00.05

My dts file looks like this

&serdes_wiz2 {
status = "okay";
};

&serdes2 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
serdes2_sgmii_link: phy@0 {
reg = <0>; // lane index
cdns,num-lanes = <1>;
cdns,phy-type = <PHY_TYPE_SGMII>;
#phy-cells = <0>;
resets = <&serdes_wiz2 1>;
};
};

&main_cpsw0 {
status = "okay";

};

&main_cpsw0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wtx_main_cpsw9x1_pins_default>;
pinctrl-1 = <&wtx_main_pmx_gpio_vddshv20_pins_default>;

main_phy3: ethernet-phy@3 {
reg = <3>;// DP83869 address
ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE>;
};
};

&main_cpsw0_port5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&main_phy3>;
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
phy-names = "mac", "serdes";
};

If I'm using SGMII mode on J784S4, is it mandatory to specify the phys = <&cpsw0_phy_gmii_sel X> and phy-names = "mac" in the DT node?
Or will it still work without that, as long as the phy-mode = "sgmii" is set?

Thanks in advance

Regards,
B. Apuroop Kumar

3 months ago

0 Tanmay Patil 3 months ago

TI__Mastermind 39750 points

Hi Apuroop,

Apuroop Kumar Bhattaram said:
If I'm using SGMII mode on J784S4, is it mandatory to specify the phys = <&cpsw0_phy_gmii_sel X> and phy-names = "mac" in the DT node?

They are needed.

Regards,
Tanmay

0 Apuroop Kumar Bhattaram 3 months ago in reply to Tanmay Patil

Prodigy 70 points

Hi Tanmay,

Thanks for the clarification. I also need clarification on ADIN1100 DT node placement behind DP83869 PHY bridge (J784S4).

The ethernet topology is as follows:

cpsw9g (port5) <--> SGMII <--> DP83869 (addr 3) <--> RGMII <--> ADIN1100 (addr 0)

In our current DTS setup, we have defined the ADIN1100 as a child node under the DP83869 MDIO entry like this:

&main_cpsw0_mdio {
status = "okay";

main_phy3: ethernet-phy@3 {
reg = <3>; // DP83869
ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE>;

adin1100: ethernet-phy@0 {
reg = <0>; // ADIN1100 behind DP83869
phy-mode = "rgmii";
};
};
};

Can you please confirm:

Is it valid to define ADIN1100 as a child node inside DP83869 like this?

Or should ADIN1100 be a separate sibling node under &main_cpsw0_mdio instead?

Appreciate your clarification on the correct binding for this bridging setup.

Regards,

B.Apuroop Kumar

0 Tanmay Patil 2 months ago in reply to Apuroop Kumar Bhattaram

TI__Mastermind 39750 points

Hi Apuroop,

Sorry for the delay in response.

Apuroop Kumar Bhattaram said:
Is it valid to define ADIN1100 as a child node inside DP83869 like this?

This depends on what kind of driver level support you have fro ADIN phy. If there is phy driver available, you should add as a sibling node to dp83869.

If you add it as a daughter node of dp83869, the dp83869 driver should take care of configuring the ADIN phy.

If no configuration is required for the ADIN phy, you can also skip adding it all-together.

Regards,
Tanmay

0 Apuroop Kumar Bhattaram 2 months ago in reply to Tanmay Patil

Prodigy 70 points

Hi Tanmay,

As a continuation of my earlier query -we are also facing an issue where the link is not coming up in this setup:

Current DTS configuration:

DP83869 is configured with ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE>
fixed-link set to 10 Mbps full-duplex
&serdes_wiz2 {
status = "okay";
};

&serdes2 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
serdes2_sgmii_link: phy@0 {
reg = <0>; // lane index
cdns,num-lanes = <1>;
cdns,phy-type = <PHY_TYPE_SGMII>;
#phy-cells = <0>;
resets = <&serdes_wiz2 1>;
};
};
&main_cpsw0 {
status = "okay";
};

&main_cpsw0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_cpsw9x1_mdio_pins_default>;
pinctrl-1 = <&main_pmx_gpio_vddshv20_pins_default>;

/* DP83869 Bridge PHY - Connected to CPSW SGMII port */
bridge_phy: ethernet-phy@3 {
reg = <3>;// DP83869 address
ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE>;
fixed-link {
speed = <10>;
full-duplex;
};
};

/* ADIN1100 - Connected via RGMII to DP83869 bridge */
adin1100: ethernet-phy@0 {
reg = <0>; // ADIN1100 behind DP83869
phy-mode = "rgmii";
};
};

&main_cpsw0_port5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&bridge_phy>;
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
phy-names = "mac", "serdes";
};

Both PHYs are detected on MDIO, but CPSW port shows “no link”.

Regards,
B. Apuroop Kumar

0 Tanmay Patil 2 months ago in reply to Apuroop Kumar Bhattaram

TI__Mastermind 39750 points

Hi,

Sorry for the delay, is the issue still present?

Without the mode as RGMII_SGMII_BRIDGE, are you able to test the device, or would this only be in bridge mode.

We haven't tested the bridge mode on EVM. We might have to include the phy team here as well.

Regards,
Tanmay

0 Apuroop Kumar Bhattaram 2 months ago in reply to Tanmay Patil

Prodigy 70 points

Hi Tanmay,

In our setup we need the DP83869HM to operate in SGMII-to-RGMII bridge mode.The Linux driver’s ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE> appears to program the opposite direction (RGMII-to-SGMII), so I removed ti,op-mode.

From the datasheet, I see that the bridge can be set through strap pins (e.g. MIRROR_EN). I want to confirm , is it possible to configure this bridge direction through registers as well, or is it only strap-configurableRegards,
B. Apuroop Kumar

0 Tanmay Patil 1 month ago in reply to Apuroop Kumar Bhattaram

TI__Mastermind 39750 points

Hi,

Let me forward this to the phy team and see if any more changes are required for this.

Regards,
Tanmay

0 J 1 month ago in reply to Tanmay Patil

TI__Genius 14936 points

Hi Apuroop,

RGMII-SGMII bridge is programmable via register configuration as well.
Please follow the below screenshot:

But, instead of writing 0x0043 to register 1DFh, please write the following:
Write 0x0003 to register 1DFh.

Best,
J

0 Apuroop Kumar Bhattaram 1 month ago in reply to J

Prodigy 70 points

Hi,

I modified the driver to write 0x0003 to register 1DFh instead of 0x0043.Below is the output:
root@j784s4-evm:~# phytool write eth1/0x03/0x0D 0x001F
root@j784s4-evm:~# phytool write eth1/0x03/0x0E 0x01DF
root@j784s4-evm:~# phytool write eth1/0x03/0x0D 0x401F
root@j784s4-evm:~# phytool read eth1/0x03/0x0E
0x0003
Below is my current dts file setup:

&serdes_ln_ctrl {
idle-states = <J784S4_SERDES2_LANE0_QSGMII_LANE5>;
};

&main_cpsw0 {
status = "okay";
};

&main_cpsw0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_cpsw9x1_mdio_pins_default>;
pinctrl-1 = <&main_pmx_gpio_vddshv20_pins_default>; //not needed for ADIN1100?

/* DP83869 Bridge PHY - Connected to CPSW SGMII port */
bridge_phy: ethernet-phy@3 {
reg = <3>;// DP83869 address
ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE>;
tx,fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx,fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};

/* ADIN1100 - Connected via RGMII to DP83869 bridge */
adin1100: ethernet-phy@0 {
reg = <0>; // ADIN1100 behind DP83869
phy-mode = "rgmii-rxid";
};
};

&main_cpsw0_port5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&bridge_phy>;
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
phy-names = "mac", "serdes";
};

&serdes_refclk {
clock-frequency = <100000000>;
};

but the link is not coming up.
ethtool eth1 shows "Link detected: no" and speed/duplex are unknown.

root@j784s4-evm:~# ethtool eth1
Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Supported pause frame use: Symmetric
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Speed: Unknown!
Duplex: Unknown! (255)
Auto-negotiation: on
master-slave cfg: forced slave
master-slave status: unknown
Port: Twisted Pair
PHYAD: 3
Transceiver: external
MDI-X: Unknown
Supports Wake-on: ubgs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x000020f7 (8439)
drv probe link ifdown ifup rx_err tx_err hw
Link detected: no
root@j784s4-evm:~# ip a
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
inet 127.0.0.1/8 scope host lo
valid_lft forever preferred_lft forever
inet6 ::1/128 scope host
valid_lft forever preferred_lft forever
2: eth0: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 04:25:e8:b7:09:f4 brd ff:ff:ff:ff:ff:ff
3: eth1: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq state DOWN group default qlen 1000
link/ether 12:e7:25:98:b0:9d brd ff:ff:ff:ff:ff:ff
root@j784s4-evm:~#

What additional configuration might be needed for SGMII-RGMII bridge mode?

Best Regards,
B.Apuroop Kumar

0 J 1 month ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

Aforementioned register configuration is all you need.
Could you check register 01h to see what the value is? Because the PHY is in bridge mode, we don't expect the PHY to report speed and duplex information necessarily.

Best,
J

0 Apuroop Kumar Bhattaram 1 month ago in reply to J

Prodigy 70 points

Hi,

The CPSW MAC is configured in SGMII mode

DP83869(connected to mdio bus at address3) is set to SGMII to RGMII bridge mode

ADIN1100(connected to same mdio bus at address0) is the PHY connected to the line.

In Linux, I modified DP83869 driver (dp83869.c) configuring the device into bridge mode, but the MAC is still treating DP83869 as the PHY.
What I would like is for DP83869 to act as a bridge and for the Linux PHY framework to use ADIN1100 as the true PHY (with DP83869 just converting SGMII<-->RGMII)

#define DP83869_SGMII_RGMII 0x0003

static int dp83869_configure_mode(struct phy_device *phydev,

struct dp83869_private *dp83869)

{

printk(KERN_DEBUG "dp83869: entered in %s\n", __func__);

int phy_ctrl_val;

int ret;

if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||

dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)

return -EINVAL;

/* Below init sequence for each operational mode is defined in

* section 9.4.8 of the datasheet.

phy_ctrl_val = dp83869->mode;

if (phydev->interface == PHY_INTERFACE_MODE_MII) {

if (dp83869->mode == DP83869_100M_MEDIA_CONVERT ||

dp83869->mode == DP83869_RGMII_100_BASE ||

dp83869->mode == DP83869_RGMII_COPPER_ETHERNET) {

phy_ctrl_val |= DP83869_OP_MODE_MII;

} else {

phydev_err(phydev, "selected op-mode is not valid with MII mode\n");

return -EINVAL;

}

ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,

phy_ctrl_val);

if (ret)

return ret;

ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);

if (ret)

return ret;

phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |

dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |

DP83869_PHY_CTRL_DEFAULT);

switch (dp83869->mode) {

case DP83869_RGMII_COPPER_ETHERNET:

ret = phy_write(phydev, MII_DP83869_PHYCTRL,

phy_ctrl_val);

if (ret)

return ret;

ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);

if (ret)

return ret;

ret = dp83869_configure_rgmii(phydev, dp83869);

if (ret)

return ret;

break;

case DP83869_RGMII_SGMII_BRIDGE:

printk(KERN_DEBUG "dp83869: mode=%x entered RGMII_SGMII_BRIDGE in %s\n",dp83869->mode, __func__);

ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,

DP83869_SGMII_RGMII);

if (ret)

return ret;

ret = phy_write_mmd(phydev, DP83869_DEVADDR,

DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);

if (ret)

return ret;

break;

case DP83869_1000M_MEDIA_CONVERT:

ret = phy_write(phydev, MII_DP83869_PHYCTRL,

phy_ctrl_val);

if (ret)

return ret;

ret = phy_write_mmd(phydev, DP83869_DEVADDR,

DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);

if (ret)

return ret;

break;

case DP83869_100M_MEDIA_CONVERT:

ret = phy_write(phydev, MII_DP83869_PHYCTRL,

phy_ctrl_val);

if (ret)

return ret;

break;

case DP83869_SGMII_COPPER_ETHERNET:

ret = phy_write(phydev, MII_DP83869_PHYCTRL,

phy_ctrl_val);

if (ret)

return ret;

ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);

if (ret)

return ret;

ret = phy_write_mmd(phydev, DP83869_DEVADDR,

DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);

if (ret)

return ret;

break;

case DP83869_RGMII_1000_BASE:

case DP83869_RGMII_100_BASE:

ret = dp83869_configure_fiber(phydev, dp83869);

break;

default:

return -EINVAL;

}

return ret;

}

Any guidance on how this topology should be represented in Device Tree and whether dp83869.c must be extended to support downstream PHY handling would be very helpful.

Best Regards,

B.Apuroop Kumar

0 J 1 month ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

What is the register content of 1h? This is to see if the link status bit is correctly being grabbed onto the driver.
The current device tree should be fine and 869 driver doesn't have to support downstream PHY. ADIN1100 should still work as an individual eth port since there is hardware connection to the Linux SoC.

Best,
J

0 Apuroop Kumar Bhattaram 1 month ago in reply to J

Prodigy 70 points

Hi,

I checked the BMSR (register 0x01) values on both PHYs:

DP83869 @ addr 3 → 0x7949
Bits set: 0, 3, 6, 8, 11, 12, 13, 14
-> Capabilities include 10/100 half/full duplex and extended status, but link status = 0.

ADIN1100 @ addr 0 → 0x1009
Bits set: 0, 3, 12
-> Only 10 Mb full duplex is advertised, link status = 0.

From my understanding, the DP83869 is still reporting standard 10/100/1G copper capabilities, while the ADIN1100 only advertises 10 Mb full duplex (as expected for 10BASE-T1L).

In SGMII–RGMII bridge mode, should the DP83869’s BMSR still reflect its legacy copper capabilities, or should it transparently pass through the downstream PHY’s (ADIN1100) status?

Since both PHYs report link down, what is the correct expectation for the DP83869’s register 0x01 when bridging to a 10BASE-T1L PHY like ADIN1100?

Does Linux CPSW need to bind directly to the ADIN1100’s MDIO node (with DP83869 only acting as a hardware bridge), or is the driver expected to interpret the DP83869’s BMSR instead?

This will help me understand if I should adjust the device tree / driver setup to ensure CPSW is monitoring the true PHY (ADIN1100) rather than the bridge.

Thanks,
Apuroop

0 J 1 month ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

Apuroop Kumar Bhattaram said:
In SGMII–RGMII bridge mode, should the DP83869’s BMSR still reflect its legacy copper capabilities, or should it transparently pass through the downstream PHY’s (ADIN1100) status?

DP83869 BMSR reflects its legacy copper capabilities.

Apuroop Kumar Bhattaram said:
Since both PHYs report link down, what is the correct expectation for the DP83869’s register 0x01 when bridging to a 10BASE-T1L PHY like ADIN1100?

DP83869 register is expected to report link down since register 0x01 reflects MDI link of DP83869, but DP83869 is in bridge mode so there is expected to be no link. Please inquire separately on ADIN1100 why the link status is down on this because the link status is usually determined by the cable connection.

Apuroop Kumar Bhattaram said:
Does Linux CPSW need to bind directly to the ADIN1100’s MDIO node (with DP83869 only acting as a hardware bridge), or is the driver expected to interpret the DP83869’s BMSR instead?

Linux CPSW needs to bind directly to the ADIN1100 MDIO node.

Because DP83869 is just acting as a bridge, there is no need to monitor the bridge as a separate PHY node.

I am inquiring the relevant team on how the bridge should be set up in Linux CPSW so I will update you once we get this information.

Best,
J

0 Apuroop Kumar Bhattaram 1 month ago in reply to J

Prodigy 70 points

Hi J,

Any information regarding bridge setup ?

Best Regards,
B. Apuroop Kumar

0 J 1 month ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

I was told to add a fixed-link configuration in the DTS to force the link UP on DP83869 all the time to make Linux think that there is a link on DP83869 node.

Best,
J

0 Apuroop Kumar Bhattaram 1 month ago in reply to J

Prodigy 70 points

Hi J,

&main_cpsw0_port5 {
status = "okay";
phy-mode = "sgmii";
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
phy-names = "mac", "serdes";

fixed-link {
speed = <10>;
full-duplex;
};
};

With the above dts change, below are the outputs:

root@j784s4-evm:/opt/edgeai-gst-apps# dmesg | grep cpsw
[ 1.343827] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 1.356686] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[ 1.363894] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[ 1.374206] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[ 1.463451] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[ 1.887829] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 1.900695] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[ 1.907903] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[ 1.918230] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[ 1.928279] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[ 2.015299] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[ 2.029152] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[ 2.035420] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.5
[ 2.042539] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[ 2.048774] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010c, freq:250000000, add_val:3 pps:0
[ 2.060076] am65-cpsw-nuss c000000.ethernet: set new flow-id-base 82
[ 7.395559] am65-cpsw-nuss c000000.ethernet eth1: configuring for fixed/sgmii link mode
[ 7.408265] am65-cpsw-nuss c000000.ethernet eth1: Link is Up - 10Mbps/Full - flow control rx/tx
[ 19.105880] NETDEV WATCHDOG: eth1 (am65-cpsw-nuss): transmit queue 0 timed out
[ 19.363127] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:9984 dql_avail:-42 free_desc:511
[ 24.989276] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:15612 dql_avail:-42 free_desc:511
[ 30.109273] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:20732 dql_avail:-42 free_desc:511
root@j784s4-evm:/opt/edgeai-gst-apps# [ 34.973265] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:25596 dql_avail:-42 free_desc:511
ethtoo[ 40.093266] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:30716 dql_avail:-42 free_desc:511
l eth1
Settings for eth1:
Supported ports: [ MII ]
Supported link modes: 10baseT/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Full
Link partner advertised pause frame use: Symmetric
Link partner advertised auto-negotiation: No
Link partner advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Full
Auto-negotiation: on
Port: MII
PHYAD: 0
Transceiver: internal
Supports Wake-on: d
Wake-on: d
Current message level: 0x000020f7 (8439)
drv probe link ifdown ifup rx_err tx_err hw
Link detected: yes
root@j784s4-evm:/opt/edgeai-gst-apps# [ 45.213265] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:35836 dql_avail:-42 free_desc:511
[ 51.101276] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:41724 dql_avail:-42 free_desc:511

I see repeated logs like eth1: txq:0 DRV_XOFF:0 tmo:xxxxx dql_avail:-42 free_desc:511. Why is the TX queue timing out with negative dql_avail even though the link is up?

Best Regards,

B. Apuroop Kumar

0 J 1 month ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

Is eth2 link going up with the modification?
If not, could you try if only initializing ADIN1100 in DTS with SGMII bring the link up? So, do not initialize DP83869 as a port.
If you could just enable DP83869 on MDIO address under &main_cpsw0_mdio, that should still keep your access to the PHY registers.

Best,
J

0 Apuroop Kumar Bhattaram 1 month ago in reply to J

Prodigy 70 points

Hi J,
With the below dts setup :

&main_cpsw0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_cpsw9x1_mdio_pins_default>;
pinctrl-1 = <&main_pmx_gpio_vddshv20_pins_default>;

/* DP83869 Bridge PHY - Connected to CPSW SGMII port */
bridge_phy: ethernet-phy@3 {
reg = <3>;
};

/* ADIN1300 - Connected via RGMII to DP83869 bridge */
adin1100: ethernet-phy@0 {
reg = <0>;
};
};
&main_cpsw0_port5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&adin1100>;
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
phy-names = "mac", "serdes";
};

Below are the outputs:
root@j784s4-evm:/opt/edgeai-gst-apps# dmesg | grep cpsw
[ 1.340732] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 1.353580] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[ 1.360787] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[ 1.371096] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[ 1.459011] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[ 1.900744] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 1.913606] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[ 1.920815] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[ 1.931132] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[ 1.941204] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[ 2.026876] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[ 2.040721] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[ 2.046989] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.5
[ 2.054108] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[ 2.060360] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010c, freq:250000000, add_val:3 pps:0
[ 2.071694] am65-cpsw-nuss c000000.ethernet: set new flow-id-base 82
[ 7.334861] am65-cpsw-nuss c000000.ethernet eth1: PHY [c000f00.mdio:00] driver [ADIN1100] (irq=POLL)
[ 7.346502] am65-cpsw-nuss c000000.ethernet eth1: configuring for phy/sgmii link mode
root@j784s4-evm:/opt/edgeai-gst-apps#
==========================================================
Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT1L/Full
Supported pause frame use: Symmetric
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT1L/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Speed: Unknown!
Duplex: Unknown! (255)
Auto-negotiation: on
master-slave cfg: preferred slave
master-slave status: unknown
Port: Twisted Pair
PHYAD: 0
Transceiver: external
MDI-X: Unknown
Supports Wake-on: d
Wake-on: d
Current message level: 0x000020f7 (8439)
drv probe link ifdown ifup rx_err tx_err hw
Link detected: no
SQI: 0/7
root@j784s4-evm:/opt/edgeai-gst-apps#
=================================================

root@j784s4-evm:/opt/edgeai-gst-apps# dmesg | grep dp83869
[ 1.426506] dp83869: entered in dp83869_probe
[ 1.426510] dp83869: entered in dp83869_of_init
[ 1.426512] dp83869: entered in dp83869_set_strapped_mode
[ 1.427345] dp83869: Hardware strapped mode = 3
[ 1.428174] dp83869: TX internal delay index from DT: 7
[ 1.433476] dp83869: entered in dp83869_config_init
[ 1.433893] dp83869: phy_modify(CFG2, DOWNSHIFT_EN) ret=0
[ 1.433896] dp83869: entered in dp83869_configure_mode
[ 1.434930] dp83869: mode=0x3 entered RGMII_SGMII_BRIDGE in dp83869_configure_mode
[ 1.435757] dp83869: phy_write_mmd(OP_MODE, RGMII_SGMII_BRIDGE) ret=0
[ 1.436584] dp83869: phy_write_mmd(FX_CTRL, DEFAULT) ret=0
[ 1.436587] dp83869: dp83869_configure_mode ret=0
[ 1.436589] dp83869: port_mirroring=2, configuring port mirroring
[ 1.436591] dp83869: entered in dp83869_config_port_mirroring
[ 1.436593] dp83869: port mirroring value = 2
[ 1.436594] if dp83869->port mirroring not equals DP83869_PORT_MIRRORING_EN in dp83869_config_port_mirroring
[ 1.437422] dp83869: dp83869_config_port_mirroring ret=0
[ 1.437425] dp83869: exiting dp83869_config_init with ret=0
[ 1.437427] dp83869: entered in dp83869_config_intr
[ 1.437429] dp83869: interrupts disabled, clearing MICR
[ 1.437638] dp83869: write MICR (clear) err=0
[ 1.437640] dp83869: entered in dp83869_ack_interrupt
[ 1.437849] dp83869: ack_interrupt (disable path) err=0
[ 1.994560] dp83869: entered in dp83869_probe
[ 1.994563] dp83869: entered in dp83869_of_init
[ 1.994566] dp83869: entered in dp83869_set_strapped_mode
[ 1.995400] dp83869: Hardware strapped mode = 3
[ 1.996230] dp83869: TX internal delay index from DT: 7
[ 2.001535] dp83869: entered in dp83869_config_init
[ 2.001746] dp83869: phy_modify(CFG2, DOWNSHIFT_EN) ret=0
[ 2.001748] dp83869: entered in dp83869_configure_mode
[ 2.002783] dp83869: mode=0x3 entered RGMII_SGMII_BRIDGE in dp83869_configure_mode
[ 2.003610] dp83869: phy_write_mmd(OP_MODE, RGMII_SGMII_BRIDGE) ret=0
[ 2.004437] dp83869: phy_write_mmd(FX_CTRL, DEFAULT) ret=0
[ 2.004440] dp83869: dp83869_configure_mode ret=0
[ 2.004442] dp83869: port_mirroring=2, configuring port mirroring
[ 2.004444] dp83869: entered in dp83869_config_port_mirroring
[ 2.004446] dp83869: port mirroring value = 2
[ 2.004448] if dp83869->port mirroring not equals DP83869_PORT_MIRRORING_EN in dp83869_config_port_mirroring
[ 2.005276] dp83869: dp83869_config_port_mirroring ret=0
[ 2.005278] dp83869: exiting dp83869_config_init with ret=0
[ 2.005281] dp83869: entered in dp83869_config_intr
[ 2.005283] dp83869: interrupts disabled, clearing MICR
[ 2.005491] dp83869: write MICR (clear) err=0
[ 2.005493] dp83869: entered in dp83869_ack_interrupt
[ 2.005702] dp83869: ack_interrupt (disable path) err=0
root@j784s4-evm:/opt/edgeai-gst-apps# dmesg | grep Reading
[ 1.427343] Reading DP83869_STRAP_STS1 register = 630
[ 1.995397] Reading DP83869_STRAP_STS1 register = 630
root@j784s4-evm:/opt/edgeai-gst-apps
=======================================
root@j784s4-evm:/opt/edgeai-gst-apps# dmesg | grep adin1100
[ 1.438858] adin1100: entered in adin_probe
[ 1.438861] adin1100: entered in adin_get_features
[ 1.438863] adin1100: phydev=(____ptrval____), priv=(____ptrval____), dev=(____ptrval____)
[ 1.439694] adin1100: phy_read_mmd(MDIO_PMA_10T1L_STAT) returned 0x3800
[ 1.439696] adin1100: priv->tx_level_2v4_able = 1 (bit=1)
[ 1.439699] adin1100: tx_level_prop_present = 0
[ 1.439701] adin1100: calling linkmode_set_bit_array()
[ 1.439703] adin1100: calling genphy_c45_pma_read_abilities()
[ 1.443004] adin1100: genphy_c45_pma_read_abilities returned 0
[ 2.006721] adin1100: entered in adin_probe
[ 2.006725] adin1100: entered in adin_get_features
[ 2.006727] adin1100: phydev=(____ptrval____), priv=(____ptrval____), dev=(____ptrval____)
[ 2.007557] adin1100: phy_read_mmd(MDIO_PMA_10T1L_STAT) returned 0x3800
[ 2.007560] adin1100: priv->tx_level_2v4_able = 1 (bit=1)
[ 2.007563] adin1100: tx_level_prop_present = 0
[ 2.007565] adin1100: calling linkmode_set_bit_array()
[ 2.007566] adin1100: calling genphy_c45_pma_read_abilities()
[ 2.010867] adin1100: genphy_c45_pma_read_abilities returned 0
[ 7.305498] adin1100: entered in adin_soft_reset
[ 7.307183] adin1100: phy_set_bits_mmd(SFT_RST) ret=0
[ 7.331048] adin1100: phy_read_mmd_poll_timeout(SYS_RDY) ret=0
[ 7.331065] adin1100: entered in adin_resume
[ 7.331067] adin1100: entered in adin_set_powerdown_mode (en=0)
[ 7.331070] adin1100: writing val=0x0 to ADIN_CRSM_SFT_PD_CNTRL
[ 7.332409] adin1100: phy_write_mmd(SFT_PD_CNTRL) ret=0
[ 7.334837] adin1100: phy_read_mmd_poll_timeout(SFT_PD_RDY) ret=0
[ 7.346522] adin1100: entered in adin_resume
[ 7.346525] adin1100: entered in adin_set_powerdown_mode (en=0)
[ 7.346527] adin1100: writing val=0x0 to ADIN_CRSM_SFT_PD_CNTRL
[ 7.347375] adin1100: phy_write_mmd(SFT_PD_CNTRL) ret=0
[ 7.361980] adin1100: phy_read_mmd_poll_timeout(SFT_PD_RDY) ret=0
[ 7.362010] adin1100: entered in adin_config_aneg
[ 7.362015] adin1100: autoneg=1, tx_level_prop_present=0, tx_level_2v4=0, tx_level_2v4_able=1
[ 7.362018] adin1100: autoneg ENABLED -> normal AN path
[ 7.362920] adin1100: phy_clear_bits_mmd(FORCED_MODE) ret=0
[ 7.369013] adin1100: genphy_c45_config_aneg ret=0
[ 7.376903] adin1100: entered in adin_read_status
[ 7.381893] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 8.418184] adin1100: entered in adin_read_status
[ 8.423187] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 9.442168] adin1100: entered in adin_read_status
[ 9.447130] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 10.462171] adin1100: entered in adin_read_status
[ 10.467137] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 11.486176] adin1100: entered in adin_read_status
[ 11.491146] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 12.510171] adin1100: entered in adin_read_status
[ 12.515137] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 13.534190] adin1100: entered in adin_read_status
[ 13.539180] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 14.558180] adin1100: entered in adin_read_status
[ 14.563248] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 15.582175] adin1100: entered in adin_read_status
[ 15.587146] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 16.606183] adin1100: entered in adin_read_status
[ 16.611185] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 17.630178] adin1100: entered in adin_read_status
[ 17.635148] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 18.654208] adin1100: entered in adin_read_status
[ 18.659263] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 19.678186] adin1100: entered in adin_read_status
[ 19.683169] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 20.706173] adin1100: entered in adin_read_status
[ 20.711145] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 21.726177] adin1100: entered in adin_read_status
[ 21.731156] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 22.750189] adin1100: entered in adin_read_status
[ 22.755195] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 23.774180] adin1100: entered in adin_read_status
[ 23.779155] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 24.798177] adin1100: entered in adin_read_status
[ 24.803150] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 25.822183] adin1100: entered in adin_read_status
[ 25.827163] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 26.846191] adin1100: entered in adin_read_status
[ 26.851178] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 27.870203] adin1100: entered in adin_read_status
[ 27.875267] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 28.894194] adin1100: entered in adin_read_status
[ 28.899190] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 29.918185] adin1100: entered in adin_read_status
[ 29.923169] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 30.942173] adin1100: entered in adin_read_status
[ 30.947145] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 31.970178] adin1100: entered in adin_read_status
[ 31.975185] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 32.990186] adin1100: entered in adin_read_status
[ 32.995163] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 34.014178] adin1100: entered in adin_read_status
[ 34.019158] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 35.038186] adin1100: entered in adin_read_status
[ 35.043159] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 36.062182] adin1100: entered in adin_read_status
[ 36.067154] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 37.086176] adin1100: entered in adin_read_status
[ 37.091155] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 38.110204] adin1100: entered in adin_read_status
[ 38.115243] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 39.134167] adin1100: entered in adin_read_status
[ 39.139134] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 40.158169] adin1100: entered in adin_read_status
[ 40.163135] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 41.182167] adin1100: entered in adin_read_status
[ 41.187116] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 42.206164] adin1100: entered in adin_read_status
[ 42.211115] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 43.230161] adin1100: entered in adin_read_status
[ 43.235117] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 44.254159] adin1100: entered in adin_read_status
[ 44.259104] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 45.278161] adin1100: entered in adin_read_status
[ 45.283110] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 46.302161] adin1100: entered in adin_read_status
[ 46.307114] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 47.326164] adin1100: entered in adin_read_status
[ 47.331113] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 48.350158] adin1100: entered in adin_read_status
[ 48.355100] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 49.374159] adin1100: entered in adin_read_status
[ 49.379101] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 50.398160] adin1100: entered in adin_read_status
[ 50.403107] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 51.422161] adin1100: entered in adin_read_status
[ 51.427109] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 52.446163] adin1100: entered in adin_read_status
[ 52.451107] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 53.470159] adin1100: entered in adin_read_status
[ 53.475105] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 54.494159] adin1100: entered in adin_read_status
[ 54.499100] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 55.518159] adin1100: entered in adin_read_status
[ 55.523104] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 56.542158] adin1100: entered in adin_read_status
[ 56.547099] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 57.566160] adin1100: entered in adin_read_status
[ 57.571101] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 58.590163] adin1100: entered in adin_read_status
[ 58.595118] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 59.614163] adin1100: entered in adin_read_status
[ 59.619107] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 60.638163] adin1100: entered in adin_read_status
[ 60.643107] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 61.662161] adin1100: entered in adin_read_status
[ 61.667105] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 62.686162] adin1100: entered in adin_read_status
[ 62.691102] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 63.535339] adin1100: entered in adin_get_sqi
[ 63.536183] adin1100: phy_read_mmd(MDIO_STAT1) ret=0x2
[ 63.536186] adin1100: Link not up, returning 0
[ 63.536188] adin1100: entered in adin_get_sqi_max
[ 63.536190] adin1100: returning ADIN_SQI_MAX=7
[ 63.710162] adin1100: entered in adin_read_status
[ 63.715107] adin1100: entered in adin_read_status and reading ADIN_AN_PHY_INST_STATUS : 51
[ 64.734160] adin1100: entered in adin_read_status

===============

Eventhough i replaced phy-handle to point adin1100, link is not up.

Best Regards,
B. Apuroop Kumar.

0 J 1 month ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

We may have to tune the RGMII delay on both ADIN1100 and DP83869 to get the link up now.
Could you see if controlling the value on 0x32 helps on DP83869?
Also, if you read the 0x01 register on ADIN1100, do you see that the link is up?

Best,
J

0 Apuroop Kumar Bhattaram 1 month ago in reply to J

Prodigy 70 points

Hi J,

I read 0x01 status register on ADIN 1100. It is reading 0x1009 . Link status bit is zero which indicates link is still not up.

Any suggestions on how to fine tune the delays when using dp83869hm in sgmii to rgmii bridge mode?

Best Regards,

B. Apuroop kumar.

0 J 1 month ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

This is ADIN1100 issue since the link should be up on the ADIN1100 PHY. The link may not be up on Linux but ADIN1100 is expected to be up when there is cable connected to ADIN1100.

Please let me know if the issue persists once you figure out the link loss issue with ADIN1100.

Best,
J

0 Apuroop Kumar Bhattaram 27 days ago in reply to J

Prodigy 70 points

Hi J,
We tried connecting adin1300 in place of adin1100 . And below are the outputs:

ethtool eth1
------------------
Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Supported pause frame use: Symmetric
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Link partner advertised pause frame use: No
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Auto-negotiation: on
master-slave cfg: preferred slave
master-slave status: master
Port: Twisted Pair
PHYAD: 0
Transceiver: external
MDI-X: off (auto)
Supports Wake-on: d
Wake-on: d
Current message level: 0x000020f7 (8439)
drv probe link ifdown ifup rx_err tx_err hw
Link detected: yes

But I am continuously getting this on terminal:
[ 7.840555] am65-cpsw-nuss c000000.ethernet eth1: PHY [c000f00.mdio:00] driver [ADIN1300] (irq=POLL)
[ 7.849698] am65-cpsw-nuss c000000.ethernet eth1: configuring for phy/sgmii link mode
[ 11.966098] am65-cpsw-nuss c000000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off
[ 17.058021] NETDEV WATCHDOG: eth1 (am65-cpsw-nuss): transmit queue 0 timed out
[ 17.504301] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:5500 dql_avail:-90 free_desc:515
[ 23.196405] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:11196 dql_avail:-90 free_desc:515
[ 28.060397] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:16060 dql_avail:-90 free_desc:515
[ 33.180397] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:21180 dql_avail:-90 free_desc:515
[ 38.044397] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:26044 dql_avail:-90 free_desc:515
[ 43.164390] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:31164 dql_avail:-90 free_desc:515
[ 48.028383] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:36028 dql_avail:-90 free_desc:515
[ 53.148380] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:41148 dql_avail:-90 free_desc:515
[ 58.012381] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:46012 dql_avail:-90 free_desc:515
[ 63.132381] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:51132 dql_avail:-90 free_desc:515
[ 67.996381] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:55996 dql_avail:-90 free_desc:515
[ 73.116380] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:61116 dql_avail:-90 free_desc:515
[ 78.236384] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:66236 dql_avail:-90 free_desc:515
[ 84.124378] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:72124 dql_avail:-90 free_desc:515
[ 85.832496] am65-cpsw-nuss c000000.ethernet eth1: Link is Down
[ 86.844388] am65-cpsw-nuss c000000.ethernet: tx timeout
[ 111.528541] am65-cpsw-nuss c000000.ethernet eth1: PHY [c000f00.mdio:00] driver [ADIN1300] (irq=POLL)
[ 111.537680] am65-cpsw-nuss c000000.ethernet eth1: configuring for phy/sgmii link mode
[ 114.622069] am65-cpsw-nuss c000000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off
[ 119.964381] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:5308 dql_avail:-90 free_desc:514
[ 125.084377] am65-cpsw-nuss c000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:10428 dql_avail:-90 free_desc:514

Can you explain why this happens?

Best Regards,
B. Apuroop Kumar.

0 J 27 days ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

This is happening because the Linux cannot transmit packets out of TX path so that is timing out and the link is dropped after the timeout.

After internal discussion, it looks like this is happening because Linux is not able to poll SGMII link up signal from the DP83869 as Linux currently thinks that ADIN1300 is connected, not DP83869.

Could you try the following DTS:

&main_cpsw0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_cpsw9x1_mdio_pins_default>;
pinctrl-1 = <&main_pmx_gpio_vddshv20_pins_default>;

/* DP83869 Bridge PHY - Connected to CPSW SGMII port */
bridge_phy: ethernet-phy@3 {
reg = <3>;
};

/* ADIN1300 - Connected via RGMII to DP83869 bridge */
adin1100: ethernet-phy@0 {
reg = <0>;
};
};
&main_cpsw0_port5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&dp83869>;
managed = "in-band-status";
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
phy-names = "mac", "serdes";
};

In-band-status enables Linux to receive link status from SGMII datapath instead of polling the register.

Please let me know if this works.

Best,
J

0 Apuroop Kumar Bhattaram 26 days ago in reply to J

Prodigy 70 points

Hi J,
With the above dts setup as mentioned,

&main_cpsw0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_cpsw9x1_mdio_pins_default>;
pinctrl-1 = <&main_pmx_gpio_vddshv20_pins_default>;

/* ADIN1100 - Connected via RGMII to DP83869 bridge */
adin1100: ethernet-phy@0 {
reg = <0>; // ADIN1100 behind DP83869
phy-mode = "rgmii";
};

/* DP83869 Bridge PHY - Connected to CPSW SGMII port */
bridge_phy: ethernet-phy@3 {
reg = <3>;// DP83869 address
};

};

&main_cpsw0_port5 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&bridge_phy>;
managed = "in-band-status";
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
phy-names = "mac", "serdes";

};

Below are the outputs:

root@j784s4-evm:/opt/edgeai-gst-apps# dmesg | grep cpsw
[    1.347180] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    1.360040] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.367247] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.377563] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[    1.463605] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[    1.887190] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    1.900059] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.907266] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.917605] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[    1.927699] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    2.011433] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[    2.025292] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[    2.031556] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.5
[    2.038677] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    2.044936] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010c, freq:250000000, add_val:3 pps:0
[    2.056288] am65-cpsw-nuss c000000.ethernet: set new flow-id-base 82
[    7.073440] am65-cpsw-nuss c000000.ethernet eth1: PHY [c000f00.mdio:03] driver [TI DP83869] (irq=POLL)
[    7.082750] am65-cpsw-nuss c000000.ethernet eth1: configuring for inband/sgmii link mode
root@j784s4-evm:/opt/edgeai-gst-apps# ifconfig
eth1: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500
        ether ba:89:36:c7:7b:c4 txqueuelen 1000 (Ethernet)
        RX packets 0 bytes 0 (0.0 B)
        RX errors 0 dropped 0 overruns 0 frame 0
        TX packets 0 bytes 0 (0.0 B)
        TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
        inet 127.0.0.1 netmask 255.0.0.0
        inet6 ::1 prefixlen 128 scopeid 0x10<host>
        loop txqueuelen 1000 (Local Loopback)
        RX packets 92 bytes 7654 (7.4 KiB)
        RX errors 0 dropped 0 overruns 0 frame 0
        TX packets 92 bytes 7654 (7.4 KiB)
        TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

root@j784s4-evm:/opt/edgeai-gst-apps# ethtool eth1
Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes:   10baseT/Half 10baseT/Full
                       100baseT/Half 100baseT/Full
                       1000baseT/Full
                       1000baseX/Full
Supported pause frame use: Symmetric
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
                       100baseT/Half 100baseT/Full
                       1000baseT/Full
                       1000baseX/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Speed: Unknown!
Duplex: Unknown! (255)
Auto-negotiation: on
master-slave cfg: forced slave
master-slave status: unknown
Port: Twisted Pair
PHYAD: 3
Transceiver: external
MDI-X: Unknown
Supports Wake-on: ubgs
Wake-on: d
        SecureOn password: 00:00:00:00:00:00
        Current message level: 0x000020f7 (8439)
                               drv probe link ifdown ifup rx_err tx_err hw
Link detected: no
root@j784s4-evm:/opt/edgeai-gst-apps#ip a
3: eth1: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq state DOWN group default qlen 1000
link/ether ba:89:36:c7:7b:c4 brd ff:ff:ff:ff:ff:ff

root@j784s4-evm:/opt/edgeai-gst-apps# phytool read eth1/0x00/0x01
0x796d
root@j784s4-evm:/opt/edgeai-gst-apps#

The status register of adin1300 indicates link is up and auto negotiation is completed. Still ethernet is not working.

Best Regards,
B. Apuroop Kumar

0 J 26 days ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

If you force eth1's link via this command:

ethtool -s eth0 autoneg off speed 1000 duplex full

does eth1 link go high and does it give the same tx error it gave us last time?
I wonder if this can be an issue with RGMII delay mismatch.

Best,
J

0 Apuroop Kumar Bhattaram 23 days ago in reply to J

Prodigy 70 points

Hi J,
We tried the command forcing autoneg off and setting speed to 1000Mbps , full duplex. Yet the link is still down. Do you know how to set delays when using dp83869hm as SGMII to RGMII bridge mode?

Best Regards,
B. Apuroop Kumar

0 Apuroop Kumar Bhattaram 23 days ago in reply to Apuroop Kumar Bhattaram

Prodigy 70 points

Also I want to mention about the changes i made to dp83869 driver code.
In the existing driver,

/* STRAP_STS1 bits */
#define DP83869_STRAP_OP_MODE_MASK		GENMASK(2, 0)

static int dp83869_set_strapped_mode(struct phy_device *phydev)
{
	struct dp83869_private *dp83869 = phydev->priv;
	int val;

	val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
	if (val < 0)
		return val;

	dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK;

	return 0;
}

But as per the datasheet , the strap_opmode bits are [11:9]

So I modified the driver like below:

/* STRAP_STS1 bits */

#define DP83869_STRAP_OP_MODE_MASK GENMASK(11, 9)

#define DP83869_STRAP_OP_MODE_SHIFT 9

static int dp83869_set_strapped_mode(struct phy_device *phydev)

{

printk(KERN_DEBUG "dp83869: entered in %s\n", __func__);

struct dp83869_private *dp83869 = phydev->priv;

int val;

val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);

if (val < 0)

return val;

printk(KERN_DEBUG "Reading DP83869_STRAP_STS1 register = %x\n", val);

dp83869->mode = (val & DP83869_STRAP_OP_MODE_MASK) >> DP83869_STRAP_OP_MODE_SHIFT ;

printk(KERN_DEBUG "dp83869: Hardware strapped mode = %d\n", dp83869->mode);

return 0;

}

With the above changes , now using strap pin configurations, it is going to proper op_mode

root@j784s4-evm:/opt/edgeai-gst-apps# dmesg | grep dp83869
[ 1.434298] dp83869: entered in dp83869_probe
[ 1.434302] dp83869: entered in dp83869_of_init
[ 1.434304] dp83869: entered in dp83869_set_strapped_mode
[ 1.435137] dp83869: Hardware strapped mode = 3
[ 1.441355] dp83869: entered in dp83869_config_init
[ 1.441770] dp83869: phy_modify(CFG2, DOWNSHIFT_EN) ret=0
[ 1.441773] dp83869: entered in dp83869_configure_mode
[ 1.442807] dp83869: mode=0x3 entered RGMII_SGMII_BRIDGE in dp83869_configure_mode
[ 1.443635] dp83869: phy_write_mmd(OP_MODE, RGMII_SGMII_BRIDGE) ret=0
[ 1.444465] dp83869: phy_write_mmd(FX_CTRL, DEFAULT) ret=0
[ 1.444468] dp83869: dp83869_configure_mode ret=0
[ 1.444470] dp83869: port_mirroring=2, configuring port mirroring
[ 1.444472] dp83869: entered in dp83869_config_port_mirroring
[ 1.444474] dp83869: port mirroring value = 2
[ 1.444476] if dp83869->port mirroring not equals DP83869_PORT_MIRRORING_EN in dp83869_config_port_mirroring
[ 1.445304] dp83869: dp83869_config_port_mirroring ret=0

Best Regards,
B. Apuroop Kumar

0 J 23 days ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

STRAP_STS register is not a writeable register. If you are changing opmode or other strap configuration via register, you will have to write on the register that strap status register impacts directly instead of changing the strap status register.

Best,

0 Apuroop Kumar Bhattaram 23 days ago in reply to J

Prodigy 70 points

Hi J,

But I am not writing to the STRAP_STS register. I am changing the mask from GENMASK(2,0) to GENMASK(11,9) since the bit positions of STRAP_OPMODE are [11:9] as per the datasheet. The existing driver code was incorrectly reading bits [2:0] instead of bits [11:9], which caused it to always report mode = 0 even though the hardware was strapped to mode 3 (SGMII-to-RGMII bridge).

My change only affects how the driver interprets the read value - no hardware registers are being written.

Best Regards,

B. Apuroop kumar

0 J 23 days ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

I see. That makes sense. With this change, is there any improvement?
Could you also share if there's any log and status of eth1 when you do ifconfig?

Best,
J

0 Apuroop Kumar Bhattaram 23 days ago in reply to J

Prodigy 70 points

Hi J,

Just wanted to let you know what modifications I did to configure dp83869hm in sgmii to rgmii bridge. But there is no improvement. Can you suggest how to define delays when operating in sgmii to rgmii bridge mode?

Best Regards,

B. Apuroop kumar.

0 J 23 days ago in reply to Apuroop Kumar Bhattaram

TI__Genius 14936 points

Hi Apuroop,

Sounds good. You can use register 32h to change the delay on RGMII line. Please refer to the datasheet for more detail, but it is configurable from 0ns to 4ns and the default is 2ns delay.

Best,

Processors

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PROCESSOR-SDK-J784S4: Clarification on phys usage with SGMII on CPSW9G