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Original question:

DRA821U: Enable DRA821U CPSW5G RGMii support in u-boot

DRA821U: Enable DRA821U CPSW5G RGMii support in u-boot (Cont)

Rich Chen
Expert 4160 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

Tool/software:

Sudheer,

This is a extend request from previous e2e. 

 RE: DRA821U: Linux configuration for DRA821U with GESI RGMii2 

Can we enable these RGMII ethernet port in u-boot?

Customer need to make all these CPSW5G RGMii port work during u-boot. 

BR, Rich

  • 0
    TI__Guru 63960 points

    Hi,

    Let  me check internally, as we haven't enabled till now.
    Will take some time to enable this.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Expert 4160 points

    Sudheer, 

    Thanks to enable the RGMII port on GESI board in Linux kernel. Customer had enable other ports on their own board.  

    Now they need these port can work in u-boot for their own firmware update tool. 

    I hope this will not take too much time to you. 

    BR, Rich 

  • 0 in reply to Rich Chen
    TI__Guru 63960 points

    Hi,

    We will work on this in next week, update the status by end of the week.

    Best Regards,
    Sudheer 

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru 63960 points

    Hi,

    I am still working on enabling CPSW5G from u-boot, kindly expect a delay in response.
    By default, only CPSW2G alone supported from u-boot.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Expert 4160 points

    Sudheer,

    Thanks for letting us know the update.

    Please work it on your availability.

    Thanks for the customized effort.

    BR, Rich

  • 0 in reply to Rich Chen
    TI__Guru 63960 points

    Hi 

    Rich Chen said:
    Please work it on your availability

    I am wokring in it, will update you the status soon. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Expert 4160 points

    Sudheer, 

    Is the porting going well?

    Please let me know if it is possible to finish it within this week.

    BR, Rich 

  • 0 in reply to Rich Chen
    TI__Guru 63960 points

    Hi Rich,

    I am able to enable CPSW5G MAC Port-2 available on TI EVM from u-boot.
    Checking for ping with external Network, will share the patch reference to you in early next week.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Expert 4160 points

    Sudheer, 

    That's great, looking forward to getting it. 

    BR, Rich

  • 0 in reply to Rich Chen
    TI__Guru 63960 points

    Hi,

    Rich Chen said:
    That's great, looking forward to getting it. 

    As informed above, will share the patch reference for you early in next week, once after confirming the communication.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru 63960 points

    Hi,

    I have enabled CPSW5G MAC Port-2 with RGMII interface and confirmed ping with the external network.

    Please find the path: J7200 Linux SDK 10.1 as a reference. (Easy to integrate the changes to the latest SDK if required)
    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/patch_5F00_to_5F00_enable_5F00_cpsw5g_5F00_rgmii_5F00_u_2D00_boot.patch

    Logs for reference:

    U-Boot 2024.04-ti-dirty (Aug 21 2025 - 16:07:10 +0530)

SoC:   J7200 SR2.0 GP
Model: Texas Instruments J7200 EVM
Board: J7200X-PM2-SOM rev E8
DRAM:  2 GiB (effective 4 GiB)
Core:  113 devices, 31 uclasses, devicetree: separate
Flash: 64 MiB
MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from nowhere... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
device name ethernet@c000000 
am65_cpsw_nuss ethernet@c000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00294104 Ports:4
device name gpio@21 
Detected: J7X-BASE-CPB rev E3
Detected: J7X-GESI-EXP rev E3
Detected: J7X-VSC8514-ETH rev E2
device name serdes@5060000 
Net:   found PHY node
uid 0x2000a231 ,phy_id = 0x2000a231 
ti,rx-internal-delay value of 10 
ti,tx-internal-delay value of 10 

Warning: ethernet@c000000port@2 (eth0) using random MAC address - 3e:12:8e:d9:68:89
eth0: ethernet@c000000port@2
Hit any key to stop autoboot:  0 
=> mdio list
mdio@f00:
0 - TI DP83867 <--> ethernet@c000000port@2
=> setenv ipaddr 192.168.5.10
=> setenv serverip 192.168.5.1
=> setenv gatewayip 192.168.5.1
=> setenv netmask 255.255.255.0
=> 
=> ping 192.168.5.20
k3-navss-ringacc ringacc@3c000000: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211
k3-navss-ringacc ringacc@3c000000: dma-ring-reset-quirk: disabled
am65_cpsw_nuss_port ethernet@c000000port@2: K3 CPSW: rflow_id_base: 5
link up on port 2, speed 1000, full duplex
Using ethernet@c000000port@2 device
host 192.168.5.20 is alive


    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Expert 4160 points

    Sudheer, 

    Thanks, I will have customer to migrate it and update. 

    BR, Rich

  • 0 in reply to Rich Chen
    TI__Guru 63960 points

    Hi,

    Rich Chen said:
    Thanks, I will have customer to migrate it and update. 

    Sure, please let us know if they have any issues.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 400 points

    HI Ti

    I apply the patch but it still enabled 1 port ethnet. 

    Our DUT had 4 rgmii (1mcu + 3 a72) , it should display eth0~eth3.

  • 0 in reply to Alvin Chen
    TI__Expert 4160 points

    Alvin, 

    DRA821 EVM with GESI board will enable one RGMii in CPSW only (RGMii 1).

    Is the eth0 show here the MCU one (CPSW2G) or CPSW5G one? 

    BR, Rich

  • 0 in reply to Rich Chen
    TI__Guru 63960 points

    Hi Alvin,

    Rich Chen said:
    DRA821 EVM with GESI board will enable one RGMii in CPSW only (RGMii 1).

    As Rich mentioned, on TI EVM we only have one port available from GESI card with RGMII interface of CPSW5G.
    You can add more ports as required.

    Rich Chen said:
    Is the eth0 show here the MCU one (CPSW2G) or CPSW5G one? 

    From U-boot logs it appears that MCU CPSW2G is loaded (as am65_cpsw_nuss @0x46000000)
    You need to disable the MCU CPSW2G and enable only CPSW5G from device tress. Which is already part of patch shared above.

    If you look at my Log, it was as like below for CPSW5G.
    am65_cpsw_nuss_port ethernet@c000000por

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 400 points

    Why disable CPSW2G ??  Can it not work both??

  • 0 in reply to Alvin Chen
    TI__Guru 63960 points

    Hi,

    Alvin Chen said:
    Why disable CPSW2G ??  Can it not work both??

    At U-boot state loading is not same as Linux. 
    We need to load the driver, only once the driver was loaded by default, it will fetch whatever the node found the compatible string map to that device tree node.

    What was the use-case to have both CPSW2G and CPSW5G at U-boot?

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 400 points

    Hi

    Our OS must download by tftp . It default download from CPSW2G , we want to CPSW5G work when port of CPSW2G broken. 

  • 0 in reply to Alvin Chen
    TI__Guru 63960 points

    Hi,

    Alvin Chen said:
    Our OS must download by tftp . It default download from CPSW2G , we want to CPSW5G work when port of CPSW2G broken. 

    Understood.

    Please refer to the following patch to enable both CPSW2G and CPSW5G from u-boot.
    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/patch_5F00_to_5F00_enable_5F00_cpsw2g_5F00_cpsw5g_5F00_rgmii_5F00_u_2D00_boot.patch


    Log:

    U-Boot 2024.04-ti-dirty (Sep 01 2025 - 13:55:42 +0530)

SoC:   J7200 SR2.0 GP
Model: Texas Instruments J7200 EVM
Board: J7200X-PM2-SOM rev E8
DRAM:  2 GiB (effective 4 GiB)
Core:  115 devices, 31 uclasses, devicetree: separate
Flash: 64 MiB
MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from nowhere... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1
am65_cpsw_nuss ethernet@c000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00294104 Ports:4
Detected: J7X-BASE-CPB rev E3
Detected: J7X-GESI-EXP rev E3
Detected: J7X-VSC8514-ETH rev E2
Net:   eth0: ethernet@46000000port@1, eth1: ethernet@c000000port@2
Hit any key to stop autoboot:  0 
=> => setenv ipaddr 192.168.5.10
Unknown command '=>' - try 'help'
=> => setenv serverip 192.168.5.1
Unknown command '=>' - try 'help'
=> => setenv gatewayip 192.168.5.1
Unknown command '=>' - try 'help'
=> => setenv netmask 255.255.255.0
Unknown command '=>' - try 'help'
=> setenv ipaddr 192.168.5.10
=> setenv serverip 192.168.5.1
=> setenv gatewayip 192.168.5.1
=> setenv netmask 255.255.255.0
=> 
=> 
=> ping 192.168.5.20              
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
am65_cpsw_nuss_port ethernet@46000000port@1: K3 CPSW: rflow_id_base: 3
ethernet@46000000port@1 Waiting for PHY auto negotiation to complete......... TIMEOUT !
am65_cpsw_nuss_port ethernet@46000000port@1: phy_startup failed
am65_cpsw_nuss_port ethernet@46000000port@1: am65_cpsw_start end error
k3-navss-ringacc ringacc@3c000000: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211
k3-navss-ringacc ringacc@3c000000: dma-ring-reset-quirk: disabled
am65_cpsw_nuss_port ethernet@c000000port@2: K3 CPSW: rflow_id_base: 5
link up on port 2, speed 1000, full duplex
Using ethernet@c000000port@2 device
host 192.168.5.20 is alive
=> ping 192.168.5.20
am65_cpsw_nuss_port ethernet@c000000port@2: K3 CPSW: rflow_id_base: 5
ethernet@c000000port@2 Waiting for PHY auto negotiation to complete......... TIMEOUT !
am65_cpsw_nuss_port ethernet@c000000port@2: phy_startup failed
am65_cpsw_nuss_port ethernet@c000000port@2: am65_cpsw_start end error
am65_cpsw_nuss_port ethernet@46000000port@1: K3 CPSW: rflow_id_base: 3
link up on port 1, speed 1000, full duplex
Using ethernet@46000000port@1 device
host 192.168.5.20 is alive
=>


    When only one port is connected, a Ping is attempted on eth0 first, and if it fails, it is attempted on eth1. Please refer to the above logs for a better understanding of where I have verified ping from both MCU CPSW2G and Main CPSW5G RGMII2.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 400 points

    Hi Ti

    It work , thanks

  • 0 in reply to Alvin Chen
    TI__Guru 63960 points

    Hi Alvin,

    Thanks for the confirmation. 

    Best Regards,
    Sudheer