AM620-Q1: Could we dynamic reduce the clock speed of the MCU M4F PLL in MCU LPM

Hello Gibbs,

Hi, Anil

Could you give us any update?

Thank You.

Gibbs

Hi, TI Expert

Update, few cues

So far, I do not find any way to "dynamic" change speed.

But it seems have another way to modify speed it in SBL. 

Pls ref this thread.

https://e2e.ti.com/support/processors-group/processors---internal/f/processors---internal-forum/1542005/am62d-q1-c7x-example-code---clock-setting-processor-speed/5955450?tisearch=e2e-sitesearch&keymatch=m4%2525252520set%2525252520speed

The file path,

/home/gibbs/work/am62_lp/mcu_plus_sdk_am62x_10_01_00_33/source/drivers/bootloader/soc/am62x/bootloader_soc.c

this is belong driver layer, you should build driver / libary first before building tiboot3

you need to replace "tiboot3.bin", project code (binary) as below. (MCU SDK, NULL_SBL)

Related build steps,

/work/am62_lp/mcu_plus_sdk_am62x_10_01_00_33$ make -s libs clean
/work/am62_lp/mcu_plus_sdk_am62x_10_01_00_33$ make -s libs PROFILE=debug
make -s examples PROFILE=debug
make -s -C examples/drivers/boot/sbl_null/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang PROFILE=debug

and then replace "tiboot3.bin" to SD boot partition

use "k3 config" to check clock after system boot complete.

 AM62L: Check CPU frequency 

Is it correct? Any comment?

Thank You Very Much

Gibbs

Hello Gibbs,

Gibbs Shih said:

(1) Do we have SW API (MCU SDK) to change MCU M4F PLL, and Do we have any example code?

(2) Does it support "dynamic" change MCU M4F PLL in MCU code.

Sorry for the delayed replies...

Users can't control the MCU_PLL changes at the Register level.

All PLL settings should be controlled through SCI call through the DM core.

If you want to change the MCU Core frequency, we need to change the frequency update in the SBL as per the method below.

Always update the core frequencies in the SBL before applications run on the core.

Regards,

Anil.

Hi, Anil

I am not sure that I post the right answer

Do we have 101 any guide to teach us to change the frequency in SBL?

Thank You.

Gibbs

Hi Meet:

  we are use yocto build and select SPL boot, then how to do this ?

Hi, Meet

I found some thing weird!

It works w/ changing A-Core clock, but it does now work for M-Core clock.

* Here is my code.

source/drivers/bootloader/soc/am62x/bootloader_soc.c

Change A530-0 to 1GHZ, and change M4 to 200KHZ

ootloader_CoreBootInfo gCoreBootInfo[] =
{
    {
        .tisciProcId    = SCICLIENT_PROC_ID_MCU_M4FSS0_CORE0,
        .tisciDevId     = TISCI_DEV_MCU_M4FSS0_CORE0,
        .tisciClockId   = TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK,
        .defaultClockHz = (uint32_t)(200*1000000),
        .coreName       = "m4f0-0",
    },   

    {
        .tisciProcId    = SCICLIENT_PROC_ID_R5FSS0_CORE0,
        .tisciDevId     = TISCI_DEV_WKUP_R5FSS0_CORE0,
        .tisciClockId   = TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK,
        .defaultClockHz = (uint32_t)(400*1000000),
        .coreName       = "r5f0-0",
    },

    {
        .tisciProcId    = SCICLIENT_PROC_ID_A53SS0_CORE_0,
        .tisciDevId     = TISCI_DEV_A53SS0_CORE_0,
        .tisciClockId   = TISCI_DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK,
        .defaultClockHz = (uint32_t)(1000*1000000),
        .coreName       = "a530-0",
    },

    {
        .tisciProcId    = SCICLIENT_PROC_ID_A53SS0_CORE_1,
        .tisciDevId     = TISCI_DEV_A53SS0_CORE_1,
        .tisciClockId   = TISCI_DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK,
        .defaultClockHz = (uint32_t)(1000*1000000),
        .coreName       = "a530-1",
    },

    {
        .tisciProcId    = SCICLIENT_PROC_ID_A53SS0_CORE_2,
        .tisciDevId     = TISCI_DEV_A53SS0_CORE_2,
        .tisciClockId   = TISCI_DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK,
        .defaultClockHz = (uint32_t)(1400*1000000),
        .coreName       = "a531-0",
    },

    {
        .tisciProcId    = SCICLIENT_PROC_ID_A53SS0_CORE_3,
        .tisciDevId     = TISCI_DEV_A53SS0_CORE_3,
        .tisciClockId   = TISCI_DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK,
        .defaultClockHz = (uint32_t)(1400*1000000),
        .coreName       = "a531-1",
    },

    {
    .tisciProcId    = SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0,
    .tisciDevId     = TISCI_DEV_HSM0,
    .tisciClockId   = TISCI_DEV_HSM0_DAP_CLK,
    .defaultClockHz = (uint32_t)(400*1000000),
    .coreName       = "m4f1-0",
    },
};

* Re-build all binary

/mcu_plus_sdk_am62x_10_01_00_33$ make -s -f makefile.am62x libs-clean
/mcu_plus_sdk_am62x_10_01_00_33$ make -s -f makefile.am62x libs
/mcu_plus_sdk_am62x_10_01_00_33$ make -s -C examples/drivers/boot/sbl_null/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang clean
/mcu_plus_sdk_am62x_10_01_00_33$ make -s -C examples/drivers/boot/sbl_null/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang all
/mcu_plus_sdk_am62x_10_01_00_33$ make -s -C examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang clean
/mcu_plus_sdk_am62x_10_01_00_33$ make -s -C examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang all

* Flash to OSPI NAND (SBL_NULL+DM)

Script as below, already make sure flash to OSPI success.

#-----------------------------------------------------------------------------#
#                                                                             #
#      DEFAULT CONFIGURATION FILE TO BE USED WITH THE FLASHWRITER SCRIPT      #
#                                                                             #
#-----------------------------------------------------------------------------#
#
# By default this config file,
# - points to pre-built flash writer, bootloader for this EVM
# - The application image points to relative path of the ipc rpmsg linux application image for this EVM
#   - Make sure this application is built before running this script
# - You can customized this config file to point to your own bootloader and/or application images
# - You can use --operation=flashverify if you just want to verify the flash contents and not flash the file.
#

# First point to sbl_uart_uniflash_stage1 binary, which initialises DDR and receives sbl_uart_uniflash_stage2 binary
--flash-writer=sbl_prebuilt/am62x-sk-lp/sbl_uart_uniflash_stage1.release.hs_fs.tiimage

# Points to sbl_uart_uniflash_stage2 binary, which function's as a server to flash one or more files
# Please note this binary is copied to DDR by sbl_uart_uniflash_stage1 and not written to any boot media like flash or eMMC
--file=../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.appimage.hs_fs --operation=flash --flash-offset=0x0

# Now send one or more files to flash or flashverify as needed. The order of sending files does not matter

# When sending bootloader make sure to flash at offset 0x0. ROM expects bootloader at offset 0x0
# --file=sbl_prebuilt/am62x-sk-lp/sbl_null.release.hs_fs.tiimage --operation=flash --flash-offset=0x0
--file=../../examples/drivers/boot/sbl_null/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_null.release.hs_fs.tiimage --operation=flash --flash-offset=0x0

# DM image is flashed at 0x880000 or to whatever offset your bootloader is configured for
--file=../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs --operation=flash --flash-offset=0xA00000

gibbs@gibbs-HP-ZBook-15-G5:~/work/am62_lp/mcu_plus_sdk_am62x_10_01_00_33/tools/boot$ python3 uart_uniflash.py -p /dev/ttyUSB0 --cfg=sbl_prebuilt/am62x-sk-lp/default_sbl_null_hs_fs.cfg

Parsing config file ...
Parsing config file ... SUCCESS. Found 4 command(s) !!!

Executing command 1 of 4 ...
Found flash writer ... sending sbl_prebuilt/am62x-sk-lp/sbl_uart_uniflash_stage1.release.hs_fs.tiimage
Sent flashwriter sbl_prebuilt/am62x-sk-lp/sbl_uart_uniflash_stage1.release.hs_fs.tiimage of size 250296 bytes in 25.57s.                                              

Executing command 2 of 4 ...
Command arguments : --file=../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.appimage.hs_fs --operation=flash --flash-offset=0x0
Sending ../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.apSending ../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.apSending ../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.apSending ../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.apSending ../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.apSending ../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.apSending ../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.ap                                                                                                                                                                      Sent ../../examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage2/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_uart_uniflash_stage2.release.appimage.hs_fs of size 129143 bytes in 13.71s.
[STATUS] SUCCESS !!!

Executing command 3 of 4 ...
Command arguments : --file=../../examples/drivers/boot/sbl_null/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_null.release.hs_fs.tiimage --operation=flash --flash-offset=0x0
Sent ../../examples/drivers/boot/sbl_null/am62x-sk-lp/r5fss0-0_nortos/ti-arm-clang/sbl_null.release.hs_fs.tiimage of size 290744 bytes in 30.31s.                     
[STATUS] SUCCESS !!!

Executing command 4 of 4 ...
Command arguments : --file=../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs --operation=flash --flash-offset=0xA00000
Sending ../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs: 186249bytes [00:18, 10Sending ../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs: 186249bytes [00:18, 10Sending ../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs: 187278bytes [00:18, 10Sending ../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs: 187279bytes [00:18, 10Sending ../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs: 187280bytes [00:20, 10Sending ../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs: 187281bytes [00:20, 10Sending ../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs: 187282bytes [00:20, 10                                                                                                                                                                      Sent ../../examples/drivers/ipc/ipc_rpmsg_echo_linux/am62x-sk-lp/r5fss0-0_freertos/ti-arm-clang/ipc_rpmsg_echo_linux.release.appimage.hs_fs of size 186135 bytes in 20.47s.
[STATUS] SUCCESS !!!

* Boot resilt as below.

We found M4 do not become 200KHZ, it still remain 400kHZ

But only A53 clock changes.

Do I miss any thing?

Could you duplicate this test on you side?

Thank You Very Much

Gibbs

Hi, Meet and Anil.

xiao-an is my customer.

His problem is : 

How to reduce (modify) MCU clock speed in Linux or u-boot source code?

After review few E2E thread, I suspect the only way to reduce "MCU clock speed" is in DM, so I try to start studying MCU SDK project. MCU SDK PROJECT  (ipc_rpmsg_echo_linux_am62x-sk-lp_r5fss0-0_freertos_ti-arm-clang) is the basic DM code w/ TISCI server, and it should be link related setting driver which include source "bootloader_soc.c", and then integrate this DM into tispl.bin  for SD linux boot.

I am not "very sure" this idea is correct, Could you have any more suggestion?

Thank You Very Much

Gibbs

Related thread,

 AM620-Q1: Replace DM and got error ti_sci_get_response with error code ret = -11 

Hi, Dear Expert

Any suggestion?

Thank You.

Gibbs

Hi Gibbs,

Please raise another thread for the following query so it can be assigned to the concerned expert:

Gibbs Shih said:

How to reduce (modify) MCU clock speed in Linux or u-boot source code?

Regarding MCU frequency not changing from 400MHz to 200MHz in SBL, I could reproduce this at my end. I am checking further to see what could be the issue.

Gibbs Shih said:

We found M4 do not become 200KHZ, it still remain 400kHZ

Best Regards,

Meet.