Tool/software:
Champ,
Per the Am67x errata i.2242, i.2243 and i.2326 and try to change PCIe clock source from internal to external clock source, we need to change the CLKSEL setting in code.
Is below register the place to modify? set 0x101?
Where driver to modify in code?
| 0010 8120h | 32 | 8120h | CTRL_MMR0_CFG0 | CTRL_MMR0_CFG0_PCIE0_CLKSEL | 31:3 | RESERVED | NONE | 0h | Reserved |
| 0010 8120h | 32 | 8120h | CTRL_MMR0_CFG0 | CTRL_MMR0_CFG0_PCIE0_CLKSEL | 2:0 | PCIE0_CLKSEL_CPTS_CLKSEL | R/W | 0h | Selects the clock source for the PCIE0 Common Platform Time Stamp module Field values (others are reserved): 3'b000 - MAIN_PLL2_HSDIV6_CLKOUT 3'b001 - MAIN_PLL0_HSDIV6_CLKOUT 3'b010 - CP_GEMAC_CPTS0_RFT_CLK (Pin) undefined - undefined 3'b011 - Reserved 3'b100 - MCU_EXT_REFCLK0 (Pin) 3'b101 - EXT_REFCLK1 (Pin) 3'b110 - SERDES1_IP1_LN0_TXMCLK 3'b111 - Reserved Reset Source: mod_por_rst_n |
Selects the clock source for the PCIE0 Common Platform Time Stamp module
Field values (others are reserved):
3'b000 - MAIN_PLL2_HSDIV6_CLKOUT
3'b001 - MAIN_PLL0_HSDIV6_CLKOUT
3'b010 - CP_GEMAC_CPTS0_RFT_CLK (Pin)
undefined - undefined
3'b011 - Reserved
3'b100 - MCU_EXT_REFCLK0 (Pin)
3'b101 - EXT_REFCLK1 (Pin)
3'b110 - SERDES1_IP1_LN0_TXMCLK
3'b111 - Reserved
Reset Source: mod_por_rst_n
BR, Rich
