AM62A7-Q1: DDR is initialization problem on custom board

Part Number: AM62A7-Q1
Other Parts Discussed in Thread: UNIFLASH

Tool/software:

Hi TI expert,

I am working on am62a7-q1 custom board. I have tried to boot with SD card and UART.

When try to boot rom SD card: -

My board is stuck after below logs: -

Then i have tried to boot from the UART and flash the binary.

1. sbl_uart_uniflash_stage1.release.hs_fs.tiimage stage1 flashed completely 

2. sbl_uart_uniflash_stage2.release.appimage.hs_fs not able to flash 

below logs i am getting while flashing: -

I tried to debug the code and found that the DDR is not initialized proper.

I found that DDR0_RESET0_N (SOC ball - P6) goes high at particular point. 

in the below image highlighted the line where DDR0_RESET0_N is goes high.

Our DDR part no is same as EVM board 

There is only difference in the DDR temperature grade and revision no

Our board DDR part NO - MT53E1G32D2FW-046 AAT:C

EVM board DDR part no - MT53E1G32D2FW-046 AUT:B

I have tried with different DDR configuration generated by tool 

some of the changes are below: -

--------------------------------------
FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

not working
--------------------------------------------------

FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

Termination: CA ODT (FSP2) - 40ohm

Not working
---------------------------------------------------
--------------------------------------------------

FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

Termination: CA ODT (FSP2) - 80ohm

Not working
---------------------------------------------------
--------------------------------------------------

FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

Termination: CA ODT (FSP2) - 40ohm
Termination: DQ ODT (FSP2) - 60Ohm

not working
---------------------------------------------------

I have built the SBL with these changes but still the same issue.

Could you please help us to generate the DDR configuration or is there any suggestion.

Regards 

Satyajeet Singh