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AM6421: Regarding the PRU Subsystems and Implementations

Keito Katafuchi
Intellectual 295 points
Part Number: AM6421

Tool/software:

I understand each PRU subsystem has the following 3 cores (two subsystems per AM64x chip)

  • PRU
  • AUX_PRU
  • TX_PRU

Looking at the TRM it seems like only the "PRU" core has R/W access to the GPIO pins?

I haven't quite figured out what all the options are for GPIO R/W.
For example, if I wanted to use the enhanced general-purpose input feature, these seem to be the applicable pins:

PRG0_PRU0_GPI0
PRG0_PRU1_GPI0
PRG1_PRU0_GPI0
PRG1_PRU1_GPI0

Are there four possible independently programmable EGPI instances possible?
Which cores are they on?

I understand GPO / GPI can't be engage at the same time, for the same PRGx / PRUx instance?
(i.e. PRG0_PRU0_GPI0 is active for the GPI feature, means the PRG0_PRU0_GPO0 can't be used?)

  • +1
    TI__Guru** 101910 points

    Hello Keito,

    How many PRU cores?

    Not quite. The PRU subsystem is divided into 2 "slices". Each SLICE in the PRU_ICSSG has 3 cores (PRU, RTU_PRU, TX_PRU). Thus, there are 6 cores per PRU_ICSSG, and 12 PRU subsystem cores total.

    "regular" GPIO vs PRU GPI / PRU GPO

    For more information about PRU GPI / PRU GPO signals and how they are different from regular GPIO, refer to
    [FAQ] What is a PRU core? Why are PRU GPIO signals different from regular GPIOs? 

    What is the connectivity for each core?

    each PRU subsystem core can read & write to the system GPIOs, just like any other processor core.

    Each PRU subsystem core can read in data from the special PRU GPI signals.

    However, only the PRU cores (not the RTU_PRU or TX_PRU) can write to the PRU GPO signals. Refer to the AM64x technical reference manual (TRM) table "PRU_ICSSG0 External Interface I/Os"

    ...

    FYI: PRU Academy coming soon 

    I wrote the AM64x academy's Multicore module over the past couple years. I suggest your team checks it out if you have not, it will hopefully save you a bunch of time when it comes to getting Linux and the R5 cores working together: https://dev.ti.com/tirex/explore/node?node=A__AJa64F6ctzZNbb.TYx4mCA__AM64-ACADEMY__WI1KRXP__LATEST 

    We are now working on a PRU academy to teach how to develop PRU firmware. If you want to get a notification when the AM64x PRU Academy is live in the next few weeks, send me a direct message.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Intellectual 295 points

    Hi Nick, 

    I have been away from digital devices this past week (Japanese summer holiday season) so haven’t had much more time to review the material. 

    What I would LOVE to be able to do is decode a proprietary NRZI encoded bitstream. It would be a gamechanger if there was a way to do clock recovery on a data stream, and use that to time the read edges. Would you have any thoughts on this? A PRU implementation seems possible with ecap and counting time between transitions, etc…but is there any material on this?