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TDA4VH-Q1: Tftp to work with LWIP on top of Enet LLD on MPU side

Krishna Kumar
Prodigy 10 points
Part Number: TDA4VH-Q1

Tool/software:

We are working on custom bootloader using TI drivers. We initialize the SBL first with following macros and then the MPU where UART and MMC drivers are working. But the enet helloworld example is not working. What are the changes required for it work in MPU? we want tftp to work with LWIP on top of Enet LLD.

    "-DSBL_LOG_LEVEL=2"
    "-DSBL_ENABLE_PLL"
    "-DSBL_ENABLE_CLOCKS"
    "-DSBL_ENABLE_DDR"
    "-DSBL_ENABLE_SERDES"
    "-DSBL_ENABLE_HLOS_BOOT"
    "-DSBL_HLOS_OWNS_FLASH"
    "-DSBL_USE_DMA=1"
    "-DSBL_SCRATCH_MEM_START=0xC2000000"
    "-DSBL_SCRATCH_MEM_SIZE=0x4000000"
    "-DBOOT_OSPI"
    "-DMAX_APP_SIZE_EMMC=0x7D000"
    "-DEEPROM_DATA_DDR_ADDRESS=0x90000000"
    "-DSBL_DISPLAY_PROFILE_INFO"
  • 0
    TI__Guru 63920 points

    Hi,

    Krishna Kumar said:
    But the enet helloworld example is not working.

    The ENET Hello World example is supported only on a few cores, like MCU1_0, MCU2_0, MCU2_1, and MCU3_0, and based on the core, the application is built for a different instance of CPSW.

    Note that these are reference examples from the SDK, expected to run standalone without any other core running. If you are running multiple cores with different applications need to take care of the memory mapping of ENET examples.

    Additionally, TI did not validate all options of the LWIP stack. Explored only a few options like TCP, iperf, UDP, and ARP.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 10 points

    Is there an any example using Enet LLD which runs on MPU1_0 core. Or is it neccessary to run from MCU cores? Currently below sequence is followed for Enet initialization. Please verify this

    1. SBL board init for pinmux (CPSW2G ) MDIO pin is configured and related inits.

    static pinmuxPerCfg_t gCpsw2g0PinCfg[] =
    {
        /* MyCPSW2G1 -> MDIO0_MDC -> AD38 */
        {
            PIN_MCASP1_AXR0, PIN_MODE(6) | \
            ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
        },
        /* MyCPSW2G1 -> MDIO0_MDIO -> AD33 */
        {
            PIN_MCASP1_AFSX, PIN_MODE(6) | \
            ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
        },
        {PINMUX_END}
    };

    static pinmuxModuleCfg_t gCpsw2gPinCfg[] =
    {
        {0, TRUE, gCpsw2g0PinCfg},
        {PINMUX_END}
    };

    2. SBL board init for serdes is done (CPSW2G ).

    #if defined(SBL_ENABLE_SERDES)
        SBL_log(SBL_LOG_MAX, "Initializing SERDES ...");
        if (CSL_PASS != Board_init(BOARD_INIT_SERDES_PHY))
        {
            retVal = CSL_EFAIL;
            SBL_log(SBL_LOG_ERR, "\n Failed to initialize Serdes PHY !! \n");
        }
        SBL_log(SBL_LOG_MAX, "done.\n");
    #endif

    3. Board init and serdes init from MPU Enet examples is removed.

    gEnetHelloWorld.boardId = ENETBOARD_SGMII_ID;
    gEnetHelloWorld.expPort = ENETBOARD_EXP_PORT_NONE;
    gEnetHelloWorld.macPort = ENET_MAC_PORT_8;

    4. Enabling of clocks and power for CPSW2G and CPSW9G is done in MPU side.

    gEnetHelloWorld.enetType = ENET_CPSW_2G;
    gEnetHelloWorld.instId = 0U;

    /* Start the clock */
    EnetAppUtils_enableClocks(gEnetHelloWorld.enetType, gEnetHelloWorld.instId);
    gEnetHelloWorld.enetType = ENET_CPSW_9G;
    gEnetHelloWorld.instId = 0U;
    gEnetHelloWorld.useSGMII = 1U;

    EnetAppUtils_enableClocks(gEnetHelloWorld.enetType, gEnetHelloWorld.instId);

    5. Enet init is done on MPU.

    6. Enet open is then done. (This gives an assert in Osal mutex function and that there is a flow error).

    If I skip this assert, below error is there

    CPSW Test
    Cpsw_openInternal: Failed to allocate RX flow via RM: -8
    Cpsw_closeInternal: : -1
    Assertion @ Line: 1209 in /home/uir1kor/ORBIX_uP/sw/ti/drv/enet/src/per/cpsw.c: hCpsw->hRxRsvdFlow != NULL

  • 0 in reply to Krishna Kumar
    TI__Guru 63920 points

    Hi,

    Krishna Kumar said:
    Is there an any example using Enet LLD which runs on MPU1_0 core. Or is it neccessary to run from MCU cores?

    We don't have examples supported by RTOS SDK to run on the MPU1_0 core.
    MPU cores are designed for application purposes, running HLOS such as Linux/QNX.

    We have a Native Linux driver supported by the TI SDK for network functionality. 
    U-Boot also supports the CPSW2G native driver, and can be used for TFTP from U-Boot.

    Krishna Kumar said:
    2. SBL board init for serdes is done (CPSW2G ).

    Please refer to the FAQ below to understand the CPSW instances supported from TI SoCs and the Software support model from TI SDK.
    [FAQ] TDA4VM: Details/information about CPSW instances supported in J7 devices and software supported from TI SDK.

    Krishna Kumar said:
    CPSW Test
    Cpsw_openInternal: Failed to allocate RX flow via RM: -8
    Cpsw_closeInternal: : -1
    Assertion @ Line: 1209 in /home/uir1kor/ORBIX_uP/sw/ti/drv/enet/src/per/cpsw.c: hCpsw->hRxRsvdFlow != NULL

    As mentioned above, examples are developed only for a few cores, we need to take care of resource allocation if we want to run examples from other cores, but not on MPU cores. 

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 10 points

    Thanks for the quick response. I am using CPSW9G which is controlled from MPU, like you said this example does not have the clks configured as per our needs as we are using serdes1 and serdes4, so serdes clk like below should be configured.

    #define TISCI_DEV_CPSW_9XUSS_J7AM0_SERDES1_RXCLK 61

    .

    /* mcu2_0 as a owner of CPSW9G needs exclusive access, preventing clock
    * changes by any other cores */
    moduleId = TISCI_DEV_CPSW_9XUSS_J7AM0;
    appFlags = TISCI_MSG_FLAG_DEVICE_EXCLUSIVE;
    cppiClkId = TISCI_DEV_CPSW_9XUSS_J7AM0_CPPI_CLK_CLK;
    rgmii250MHzClkId = TISCI_DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_250_CLK;
    rgmii50MHzClkId = TISCI_DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_50_CLK;
    rgmii5MHzClkId = TISCI_DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_5_CLK;
    clkSelMux = ENET_CPSW0_CPTS_CLKSEL_MAIN_SYSCLK0;
  • 0 in reply to Krishna Kumar
    TI__Guru 63920 points

    Hi,

    Krishna Kumar said:
    Thanks for the quick response. I am using CPSW9G which is controlled from MPU, like you said this example does not have the clks configured as per our needs as we are using serdes1 and serdes4, so serdes clk like below should be configured.

    Please refer to the board configuration files in the TI SDK for SerDes clock configuration based on the interface used.
    Additionally, as mentioned above, we don't have any examples from PDK to run on A72 cores, and TI has not validated TFTP from LWIP.
    You need to port yourself and explore TFTP support from LWIP.

    Best Regards,
    Sudheer