Tool/software:
hi!
I'm testing MCSPI slave mode of J722S in loopback (main_spi2:master <> main_spi0:slave, or mcu_spi0:master <> main_spi0:slave) configuration with jumper wires on the 40pin user expansion header on the evaluation board.
I seem to see slave side have tendency to get hang while (seemingly) waiting inside kernel when transfer test is done using the "spidev_test" program.
command reads typically like the below. with the loop count like 500, the test does succeeds sometimes but fails with slave side stuck somewhere in the middle of the loop.
changing the spi clock speed, "delay" parameter, removing the "-v" option doesn't appear to help much.
master:
(main_spi2)
./spidev_test -D /dev/spidev3.0 -s 500000 -S 32 -I 500 -v
-OR-
(mcu_spi0)
./spidev_test -D /dev/spidev1.0 -s 500000 -S 32 -I 500 -v
slave:
(main_spi0)
./spidev_test -D /dev/spidev2.0 -s 500000 -S 32 -I 500 -vare there any behavior like this seen? Any diagnostics hints are very welcome.
Thanks in advance!
jumper wire look:

dtso file
// SPDX-License-Identifier: GPL-2.0
/*
* see https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j722s/10_01_00_04/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/SPI.html
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "k3-pinctrl.h"
// mcu_spi0 = "/bus@f0000/bus@4000000/spi@4b00000";
// mcu_spi1 = "/bus@f0000/bus@4000000/spi@4b10000";
// main_spi0 = "/bus@f0000/spi@20100000";
// main_spi1 = "/bus@f0000/spi@20110000";
// main_spi2 = "/bus@f0000/spi@20120000";
/*
* Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
*/
&{/chosen} {
overlays {
k3-j722s-evm-spidev.kernel = __TIMESTAMP__;
};
};
&main_pmx0 {
// This was auto-generated by TI PinMux on 6/4/2025 at 4:06:00 PM.
main_gpio0_pins_default: main_gpio0-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x0088, PIN_INPUT, 7) /* (N22) GPMC0_OEn_REn.GPIO0_33 */
J722S_IOPAD(0x0094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36 */
J722S_IOPAD(0x009c, PIN_INPUT, 7) /* (W26) GPMC0_WAIT1.GPIO0_38 */
J722S_IOPAD(0x00a8, PIN_INPUT, 7) /* (R27) GPMC0_CSn0.GPIO0_41 */
J722S_IOPAD(0x00ac, PIN_INPUT, 7) /* (P21) GPMC0_CSn1.GPIO0_42 */
>;
};
main_gpio1_pins_default: main_gpio1-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x019c, PIN_INPUT, 7) /* (B25) MCASP0_AXR1.GPIO1_9 */
J722S_IOPAD(0x01a0, PIN_INPUT, 7) /* (F23) MCASP0_AXR0.GPIO1_10 */
J722S_IOPAD(0x01a8, PIN_INPUT, 7) /* (C26) MCASP0_AFSX.GPIO1_12 */
J722S_IOPAD(0x01b8, PIN_INPUT, 7) /* (C20) SPI0_CS1.GPIO1_16 */
>;
};
main_spi2_pins_default: main_spi2-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x01b0, PIN_INPUT, 1) /* (F24) MCASP0_ACLKR.SPI2_CLK */
J722S_IOPAD(0x01ac, PIN_INPUT, 1) /* (C27) MCASP0_AFSR.SPI2_CS0 */
J722S_IOPAD(0x0194, PIN_INPUT, 1) /* (A25) MCASP0_AXR3.SPI2_D0 */
J722S_IOPAD(0x0198, PIN_INPUT, 1) /* (A26) MCASP0_AXR2.SPI2_D1 */
>;
};
main_spi0_pins_default: main_spi0-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x01bc, PIN_INPUT, 0) /* (D20) SPI0_CLK */
J722S_IOPAD(0x01b4, PIN_INPUT, 0) /* (B20) SPI0_CS0 */
J722S_IOPAD(0x01c0, PIN_INPUT, 0) /* (E19) SPI0_D0 */
J722S_IOPAD(0x01c4, PIN_INPUT, 0) /* (E20) SPI0_D1 */
>;
};
};
// enable only spi2 and spi0. spi1 is not well arranged on TI evaluation board.
#if 0 // put to slave
&main_spi2 {
status = "okay";
pinctrl-0 = <&main_spi2_pins_default>;
pinctrl-names = "default";
dmas = <&main_pktdma 0xc308 0>, <&main_pktdma 0x4308 0>;
dma-names = "tx0", "rx0";
spi-slave;
slave {
spi-max-frequency = <24000000>;
compatible = "rohm,dh2228fv";
};
};
#else // master
&main_spi2 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&main_spi2_pins_default>;
pinctrl-names = "default";
dmas = <&main_pktdma 0xc308 0>, <&main_pktdma 0x4308 0>;
dma-names = "tx0", "rx0";
spidev@0 {
spi-max-frequency = <24000000>;
reg = <0>;
compatible = "rohm,dh2228fv";
};
};
#endif
&main_spi0 {
status = "okay";
pinctrl-0 = <&main_spi0_pins_default>;
pinctrl-names = "default";
dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
dma-names = "tx0", "rx0";
spi-slave;
slave {
spi-max-frequency = <24000000>;
compatible = "rohm,dh2228fv";
};
};
&mcu_pmx0 {
// This was auto-generated by TI PinMux on 6/4/2025 at 4:06:00 PM.
mcu_gpio0_pins_default: mcu_gpio0-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x001c, PIN_INPUT, 7) /* (B5) MCU_UART0_CTSn.MCU_GPIO0_7 */
J722S_MCU_IOPAD(0x0020, PIN_INPUT, 7) /* (C5) MCU_UART0_RTSn.MCU_GPIO0_8 */
J722S_MCU_IOPAD(0x0044, PIN_INPUT, 7) /* (B13) MCU_I2C0_SCL.MCU_GPIO0_17 */
J722S_MCU_IOPAD(0x0048, PIN_INPUT, 7) /* (E11) MCU_I2C0_SDA.MCU_GPIO0_18 */
J722S_MCU_IOPAD(0x004c, PIN_INPUT, 7) /* (B9) WKUP_I2C0_SCL.MCU_GPIO0_19 */
J722S_MCU_IOPAD(0x0050, PIN_INPUT, 7) /* (D11) WKUP_I2C0_SDA.MCU_GPIO0_20 */
>;
};
mcu_spi0_pins_default: mcu_spi0-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x0008, PIN_INPUT, 0) /* (A9) MCU_SPI0_CLK */
J722S_MCU_IOPAD(0x0000, PIN_INPUT, 0) /* (C12) MCU_SPI0_CS0 */
J722S_MCU_IOPAD(0x000c, PIN_INPUT, 0) /* (B12) MCU_SPI0_D0 */
J722S_MCU_IOPAD(0x0010, PIN_INPUT, 0) /* (C11) MCU_SPI0_D1 */
>;
};
};
&mcu_spi0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&mcu_spi0_pins_default>;
pinctrl-names = "default";
ti,pindir-d0-out-d1-in;
// dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
// dma-names = "tx0", "rx0";
spidev@0 {
spi-max-frequency = <24000000>;
reg = <0>;
compatible = "rohm,dh2228fv";
};
};
TI SDK revisions
ti-processor-sdk-linux-edgeai-j722s-evm-10_01_00_04
ti-processor-sdk-linux-edgeai-j722s-evm-11_00_00_08




