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TDA4VH-Q1: SERDES (CPSW9x, PCIe) setup in sysconfig

AnBer
Mastermind 30160 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Team,
I was looking at the below post:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1552878/tda4vh-q1-how-should-i-troubleshoot-a-link-up-failure-issue
that talks about configuring the same SERDES for two protocols.
There is the below comment in the E2E post:
    'PCIe + SGMII (1Gbps) -> Supported from TI Linux SDK. Need to configure from the boot loader i.e., U-boot.'

-How should the pinmux setup in sysconfig look like?
The setup for CPSW9x and PCIe module in sysconfig for the same SERDES pin does shows a pin conflict.
   PCIE / PCIE0_TXP1 signal -> SERDES1_TX1_P/AR6 pin
   CPSW9x / SGMII4_TXP0 signal -> SERDES1_TX1_P/AR6 pin
but I guess it is correct in case two protocols are being used on the same SERDES?

-What are you general advises when doing the pinmux config for SERDES for both sinle protocol and dual protocol in sysconfig?

- Only the Signal (like SGMII4_TXP0)  to pin (SERDES1_TX1_P/AR6 pin) assignment can be done in sysconfig. Correct?
The specific Mode (2.5Gb SGMII/XAUI, 5Gb QSGMII, ..etc) has to be done by SW. Correct?

Sysconfig:


Thanks in advance,

Anthony

  • +1
    TI__Guru 64680 points

    Hi,

    AnBer said:
    -How should the pinmux setup in sysconfig look like?
    The setup for CPSW9x and PCIe module in sysconfig for the same SERDES pin does shows a pin conflict.
       PCIE / PCIE0_TXP1 signal -> SERDES1_TX1_P/AR6 pin
       CPSW9x / SGMII4_TXP0 signal -> SERDES1_TX1_P/AR6 pin
    but I guess it is correct in case two protocols are being used on the same SERDES?

    You can't use the same pin for both functionalities. You can use either one.
    Above, what I mean by PCIe + SGMII is that Lane0 can be used for PCIe and Lane1 can be used for SGMII, but not both from the same lanes.

    AnBer said:
    - Only the Signal (like SGMII4_TXP0)  to pin (SERDES1_TX1_P/AR6 pin) assignment can be done in sysconfig. Correct?

    Sysconfig will not generate any mapping for the above lines as SerDes Lanes are directly mapped i.e,. SerDes1 TX0P, TX0N, RX0P, RX0N are pins related to Lane0 of SerDes.

    The device tree has serdes_ln_ctrl for mapping of SerDes lanes to the required functionality, like QSGMII/PCIe.

    AnBer said:
    The specific Mode (2.5Gb SGMII/XAUI, 5Gb QSGMII, ..etc) has to be done by SW. Correct?

    Yes, it is the software configuration of SerDes using phy-type property from the device tree as captured below.


    Best Regards,
    Sudheer